A Modiﬁed DSC-Based Grid Synchronization Method for a High Renewable Penetrated Power System Under Distorted Voltage Conditions

: With the increasing penetration of renewable energy, a weak grid with declining inertia and distorted voltage conditions becomes a signiﬁcant problem for wind and solar energy integration. Grid frequency is prone to deviate from its nominal value. Grid voltages become more easily polluted by unbalanced and harmonic components. Grid synchronization technique, as a signiﬁcant method used in wind and solar energy grid-connected converters, can easily become ine ﬀ ective. As probably the most widespread grid synchronization technique, phase-locked loop (PLL) is required to detect the grid frequency and phase rapidly and precisely even under such undesired conditions. While the amount of ﬁltering techniques can remove disturbances, they also deteriorate the dynamic performance of PLL, which may not meet the standard requirements of grid codes. The objective of this paper is to propose an e ﬀ ective PLL to tackle this challenge. The proposed PLL is based on quasi-type-1 PLL (QT1-PLL), which provides a good ﬁltering capability by using a moving average ﬁlter (MAF). To accelerate the transient behavior when disturbance occurs, a modiﬁed delay signal cancellation (DSC) operator is proposed and incorporated into the ﬁltering stage of QT1-PLL. By using modiﬁed DSCs and MAFs in a cascaded way, the settling time of the proposed method is reduced to around one cycle of grid fundamental frequency without degrading any disturbance rejection capability. To verify the performance, several test cases, which usually happen in high renewable penetrated power systems, are carried out to demonstrate the e ﬀ ectiveness of the proposed PLL.


Introduction
In modern power systems, more and more renewable energies such as solar and wind energy are integrated with the power grid through grid-connected power converters. To use this energy in more efficient ways, several advanced techniques, such as high voltage direct current transmission (HVDC) [1], flexible AC transmission systems (FACTS) [2] and energy storage systems (ESSs) [3], are developed. Some power electronic converter-based applications on the customer side, such as constant power load (CPL) and micro-grids with ESSs, are also widely used for some purposes, like peak load shaving. All the above yields a more complicated power system with a large amount of power converters. A typical power system integrating high penetrated renewable energy sources is depicted in Figure 1. The irregular phenomenon and uncertainty of wind and solar energy may cause undesired grid conditions [4]. Sub-and super-synchronous oscillations may emerge in wind farms if the controller is not well-designed [5]. In recent years, these issues happened several times in Oklahoma, USA [6] tripped off. This highly impacted the operation of power distribution and renewable energy utilization. The grid frequency is prone to deviate from its nominal value since the inertia of the grid decreases. Grid voltages contain an amount of undesired components, such as fundamental frequency negative sequences (FFNSs) and harmonic components, which results in unbalanced and distorted grid conditions. It is an essential requirement for a renewable energy power converter to maintain stable operation with high performance under such conditions. To achieve this goal, a proper grid synchronization method is needed for all grid-connected applications. It is a big challenge for a grid synchronization method to extract grid frequency and phase information under such adverse conditions. Among various grid synchronization techniques, phase-locked loop (PLL) is the most widely used method in grid phase and frequency detection area for its robust performance and simple implementation [9][10][11][12]. Figure 2 shows the most common employment of PLLs in practical applications. After extracting grid voltage information at the common coupling point (PCC), PLL sends estimated grid phases to the controller of the grid power converter (GPC). For a three phase power system, synchronous reference frame PLL (SRF-PLL) is an effective and typical method under ideal conditions [13,14]. However, with more utilization of renewable energy sources, a power system turns "weak" [15][16][17][18]. The grid voltages usually contain fundamental frequency negative sequence components (FFNSs) and other harmonic components. Furthermore, grid frequency does not always stay at its nominal value. To maintain the phase tracking accuracy under distorted grid voltages conditions, various filtering technique were used to remove disturbances at the cost of slowing down the transient response, which may violate the requirement on settling time in common grid codes [19][20][21][22][23]. The block diagram of SRF-PLL is depicted in Figure 3. Park transformation is utilized as a phase detector (PD). An integrator is employed as a voltage controller oscillator (VCO). A proportional-integral controller (PI) is used to mitigate the phase-tracking error. To enhance the Among various grid synchronization techniques, phase-locked loop (PLL) is the most widely used method in grid phase and frequency detection area for its robust performance and simple implementation [9][10][11][12]. Figure 2 shows the most common employment of PLLs in practical applications. After extracting grid voltage information at the common coupling point (PCC), PLL sends estimated grid phases to the controller of the grid power converter (GPC). For a three phase power system, synchronous reference frame PLL (SRF-PLL) is an effective and typical method under ideal conditions [13,14]. However, with more utilization of renewable energy sources, a power system turns "weak" [15][16][17][18]. The grid voltages usually contain fundamental frequency negative sequence components (FFNSs) and other harmonic components. Furthermore, grid frequency does not always stay at its nominal value. To maintain the phase tracking accuracy under distorted grid voltages conditions, various filtering technique were used to remove disturbances at the cost of slowing down the transient response, which may violate the requirement on settling time in common grid codes [19][20][21][22][23].
Energies 2018, 11, x FOR PEER REVIEW 2 of 20 tripped off. This highly impacted the operation of power distribution and renewable energy utilization. The grid frequency is prone to deviate from its nominal value since the inertia of the grid decreases. Grid voltages contain an amount of undesired components, such as fundamental frequency negative sequences (FFNSs) and harmonic components, which results in unbalanced and distorted grid conditions. It is an essential requirement for a renewable energy power converter to maintain stable operation with high performance under such conditions. To achieve this goal, a proper grid synchronization method is needed for all grid-connected applications. It is a big challenge for a grid synchronization method to extract grid frequency and phase information under such adverse conditions. Among various grid synchronization techniques, phase-locked loop (PLL) is the most widely used method in grid phase and frequency detection area for its robust performance and simple implementation [9][10][11][12]. Figure 2 shows the most common employment of PLLs in practical applications. After extracting grid voltage information at the common coupling point (PCC), PLL sends estimated grid phases to the controller of the grid power converter (GPC). For a three phase power system, synchronous reference frame PLL (SRF-PLL) is an effective and typical method under ideal conditions [13,14]. However, with more utilization of renewable energy sources, a power system turns "weak" [15][16][17][18]. The grid voltages usually contain fundamental frequency negative sequence components (FFNSs) and other harmonic components. Furthermore, grid frequency does not always stay at its nominal value. To maintain the phase tracking accuracy under distorted grid voltages conditions, various filtering technique were used to remove disturbances at the cost of slowing down the transient response, which may violate the requirement on settling time in common grid codes [19][20][21][22][23]. The block diagram of SRF-PLL is depicted in Figure 3. Park transformation is utilized as a phase detector (PD). An integrator is employed as a voltage controller oscillator (VCO). A proportional-integral controller (PI) is used to mitigate the phase-tracking error. To enhance the The block diagram of SRF-PLL is depicted in Figure 3. Park transformation is utilized as a phase detector (PD). An integrator is employed as a voltage controller oscillator (VCO). A proportional-integral controller (PI) is used to mitigate the phase-tracking error. To enhance the disturbance rejection capability and keep the phase tracking accuracy of SRF-PLL, a low pass filter (LPF) or moving average filter (MAF) is employed in the inner loop. However, LPF-based PLL can only attenuate but not eliminate the disturbance component. To achieve good disturbance rejection, the bandwidth of LPF-based PLL must be significantly reduced, which results in a large settling time [23]. Compared with LPF, MAF can totally remove a specific set of disturbances, which depends on its window length (T ω ). However, T ω deteriorates the dynamic response since T ω has to be 0.01 s (half grid period) to eliminate all disturbance [24].
Energies 2018, 11, x FOR PEER REVIEW 3 of 20 disturbance rejection capability and keep the phase tracking accuracy of SRF-PLL, a low pass filter (LPF) or moving average filter (MAF) is employed in the inner loop. However, LPF-based PLL can only attenuate but not eliminate the disturbance component. To achieve good disturbance rejection, the bandwidth of LPF-based PLL must be significantly reduced, which results in a large settling time [23]. Compared with LPF, MAF can totally remove a specific set of disturbances, which depends on its window length (Tω). However, Tω deteriorates the dynamic response since Tω has to be 0.01 s (half grid period) to eliminate all disturbance [24]. To tackle the problem mentioned above, many advanced methods were proposed in recent years. According to their various filtering methods, these advanced PLLs can be classified into two categories: LPF-based PLLs and MAF-based PLLs. To improve the performance of LPF-based PLLs, dual second-order generalized integrators (DSOGIs) [25], multiple complex-coefficient filters (MCCFs) [26], multiple reference frame-based filter structures (MRFs) [27] and decoupled double synchronous reference frame-based filter structures (DDSRFs) [28] were arranged before applying Park transformation. The basic idea of these PLLs is to make the filtering stage act as a hybrid filter that consists of notch filters and LPFs. Notch filters are responsible for eliminating FFNS components and other important harmonics. LPFs are used to attenuate other disturbances. These methods are not suitable when grid voltages contain several significant components. Only the disturbance components coincident with the specific frequency in a notch filter can be totally removed. Compared with LPF-based PLLs, MAF-based PLLs can provide ideal filtering capabilities at the cost of increasing time delay. With a Tω time delay, MAF can eliminate all n/Tω (n = 1, 2, 3,...) frequency components. The delay signal cancellation (DSC) operator is another effective filter, the behavior of which is similar to MAFs. However, single DSCs cannot eliminate all desired disturbances. To overcome this weakness, several DSCs with different Tω are usually employed to build an entire filtering stage in cascaded [29][30][31]. Consequently, the time delay of the filtering stage is the sum of delay introduced by all DSCs. Too many DSCs also increases the computational burden and implementation complexity.
Besides using an advanced filter, another way to improve PLLsʹ performance is to change the control structure. In [32,33], a secondary control path is built to accelerate the transient behavior. However, an inappropriate design of a secondary control path may give rise to the stability problem. It also increases the order of open loop transfer functions and the implementation complexity of a system [34]. Recently, a PLL with a new structure named quasi-type-1 PLL (QT1-PLL) was proposed in [35]. Compared with the traditional type-2 SRF-PLL, QT1-PLL provides a feed-forward control path to the output. This makes QT1-PLL able to track phase precisely without using integral operations in the controller. One more open-loop pole is provided at the origin point, which accelerate the dynamic response. Since the filtering stage of QT1-PLL is built by MAFs, QT1-PLL can also offer a satisfied filtering capability. It is a good idea to do some further performance improvement of PLL based on the QT1-PLL structure.
To improve the dynamic performance without degrading PLLsʹ filtering capability, this paper propose a new PLL based on the QT1-PLL structure. In order to provide a fast transient response, a hybrid filtering stage is designed and arranged at the inner loop of the proposed PLL. The proposed hybrid filtering stage consists of a modified DSC (MDSC) and MAFs with narrowed Tω. Our basic idea is to eliminate two sets of disturbance components by using MDSCs and MAFs, separately. Different from the conventional DSC-based PLL, there is only one MDSC unit in our method, which To tackle the problem mentioned above, many advanced methods were proposed in recent years. According to their various filtering methods, these advanced PLLs can be classified into two categories: LPF-based PLLs and MAF-based PLLs. To improve the performance of LPF-based PLLs, dual second-order generalized integrators (DSOGIs) [25], multiple complex-coefficient filters (MCCFs) [26], multiple reference frame-based filter structures (MRFs) [27] and decoupled double synchronous reference frame-based filter structures (DDSRFs) [28] were arranged before applying Park transformation. The basic idea of these PLLs is to make the filtering stage act as a hybrid filter that consists of notch filters and LPFs. Notch filters are responsible for eliminating FFNS components and other important harmonics. LPFs are used to attenuate other disturbances. These methods are not suitable when grid voltages contain several significant components. Only the disturbance components coincident with the specific frequency in a notch filter can be totally removed. Compared with LPF-based PLLs, MAF-based PLLs can provide ideal filtering capabilities at the cost of increasing time delay. With a T ω time delay, MAF can eliminate all n/T ω (n = 1, 2, 3, . . . ) frequency components. The delay signal cancellation (DSC) operator is another effective filter, the behavior of which is similar to MAFs. However, single DSCs cannot eliminate all desired disturbances. To overcome this weakness, several DSCs with different T ω are usually employed to build an entire filtering stage in cascaded [29][30][31]. Consequently, the time delay of the filtering stage is the sum of delay introduced by all DSCs. Too many DSCs also increases the computational burden and implementation complexity.
Besides using an advanced filter, another way to improve PLLs' performance is to change the control structure. In [32,33], a secondary control path is built to accelerate the transient behavior. However, an inappropriate design of a secondary control path may give rise to the stability problem. It also increases the order of open loop transfer functions and the implementation complexity of a system [34]. Recently, a PLL with a new structure named quasi-type-1 PLL (QT1-PLL) was proposed in [35]. Compared with the traditional type-2 SRF-PLL, QT1-PLL provides a feed-forward control path to the output. This makes QT1-PLL able to track phase precisely without using integral operations in the controller. One more open-loop pole is provided at the origin point, which accelerate the dynamic response. Since the filtering stage of QT1-PLL is built by MAFs, QT1-PLL can also offer a satisfied filtering capability. It is a good idea to do some further performance improvement of PLL based on the QT1-PLL structure.
To improve the dynamic performance without degrading PLLs' filtering capability, this paper propose a new PLL based on the QT1-PLL structure. In order to provide a fast transient response, a hybrid filtering stage is designed and arranged at the inner loop of the proposed PLL. The proposed hybrid filtering stage consists of a modified DSC (MDSC) and MAFs with narrowed T ω . Our basic idea is to eliminate two sets of disturbance components by using MDSCs and MAFs, separately. Different from the conventional DSC-based PLL, there is only one MDSC unit in our method, which is easy for digital implementation. To demonstrate the effectiveness, an experimental case study is carried out when grid voltage conditions are under phase jump, frequency jump, frequency ramp change and harmonic polluted voltage conditions, which usually happens to high renewable energy-penetrated power system. This paper is organized as follows. In Section 2, the modified DSC is presented based on the analysis of DSCs. The hybrid filtering stage and new PLLs are proposed in Section 3. In Section 4, the mathematics model is established. Based on this model, the parameters are designed based on analysis of the system. In Section 5, the performance of the proposed method is validated by a comprehensive case study.

Modified Delay Signal Cancellation Operator
The DSC operator has been widely studied in much literature [36]. In the Laplace domain, most of the existing DSC operators can be written as: To achieve a desired performance, several DSCs have to be connected in cascaded. For instance, five DSCs with different value of n (n = 2, 4, 8,16,32) were arranged at the pre-filtering stage in [37]. The typical block diagram of the control strategy is shown in Figure 4. Too many DSCs used in PLLs results in complicated implementation. It is a normal idea to simplify the system by reducing the number of DSCs. is easy for digital implementation. To demonstrate the effectiveness, an experimental case study is carried out when grid voltage conditions are under phase jump, frequency jump, frequency ramp change and harmonic polluted voltage conditions, which usually happens to high renewable energy-penetrated power system. This paper is organized as follows. In Section 2, the modified DSC is presented based on the analysis of DSCs. The hybrid filtering stage and new PLLs are proposed in Section 3. In Section 4, the mathematics model is established. Based on this model, the parameters are designed based on analysis of the system. In Section 5, the performance of the proposed method is validated by a comprehensive case study.

Modified Delay Signal Cancellation Operator
The DSC operator has been widely studied in much literature [36]. In the Laplace domain, most of the existing DSC operators can be written as: To achieve a desired performance, several DSCs have to be connected in cascaded. For instance, five DSCs with different value of n (n = 2, 4, 8,16,32) were arranged at the pre-filtering stage in [37]. The typical block diagram of the control strategy is shown in Figure 4. Too many DSCs used in PLLs results in complicated implementation. It is a normal idea to simplify the system by reducing the number of DSCs. Observing Equation (1), it can be found that there is only one parameter n which can decide the characteristics of DSCn. To make its property more flexible, DSCn is modified to the following form with two parameters.
In Equation (2), T is the grid period (0.02 s for 50 Hz power system). m is used to shift the original DSCn frequency characteristics along the frequency axis. n is a parameter that can decide the time delay inside the DSCn. After using Euler transformation, the implementation of MDSCm,n is shown in Figure 5. It should be noted that the input of MDSCm,n is a vector with two dimensions. The output of MDSCm,n is also a 2D vector. The effect of m can be considered as a rotating operation to the input vector. Observing Equation (1), it can be found that there is only one parameter n which can decide the characteristics of DSC n . To make its property more flexible, DSC n is modified to the following form with two parameters.
In Equation (2), T is the grid period (0.02 s for 50 Hz power system). m is used to shift the original DSC n frequency characteristics along the frequency axis. n is a parameter that can decide the time delay inside the DSC n . After using Euler transformation, the implementation of MDSC m,n is shown in Figure 5. It should be noted that the input of MDSC m,n is a vector with two dimensions. The output of MDSC m,n is also a 2D vector. The effect of m can be considered as a rotating operation to the input vector.  In Figure 7, m is 2. The solid lines, dashed lines and dotted lines are the bode diagrams of MDSCm=2,n with n = 2, 4, 8, respectively. With different value of n, the interval of the notch frequency of an MDSC can be changed. This property can be used to eliminate a set of specific harmonic frequency components. In the next section, the design procedure of the proposed hybrid filtering stage is presented based on the analysis of MDSCs above.  In Figure 7, m is 2. The solid lines, dashed lines and dotted lines are the bode diagrams of MDSCm=2,n with n = 2, 4, 8, respectively. With different value of n, the interval of the notch frequency of an MDSC can be changed. This property can be used to eliminate a set of specific harmonic frequency components. In the next section, the design procedure of the proposed hybrid filtering stage is presented based on the analysis of MDSCs above. In Figure 7, m is 2. The solid lines, dashed lines and dotted lines are the bode diagrams of MDSC m=2,n with n = 2, 4, 8, respectively. With different value of n, the interval of the notch frequency of an MDSC can be changed. This property can be used to eliminate a set of specific harmonic frequency components. In the next section, the design procedure of the proposed hybrid filtering stage is presented based on the analysis of MDSCs above.

The Proposed PLL Structure
In this section, the voltage sequence component of non-ideal grid voltages is analyzed at first to provide the basis for the design procedure of the proposed PLL. To achieve our objective, a hybrid filtering stage based on MAFs and MDSCs is suggested and analyzed in this section. Then, it is incorporated into a QT1-PLL structure.

The Component Analysis of Distorted Grid Voltages
Under distorted grid voltage conditions, three-phase grid voltages contain fundamental frequency positive sequence (FFPS), fundamental frequency negative sequences (FFNS) and other harmonic sequence components. FFPS components can be written as follows: where  1 V represents the amplitude of FFPS and ω is the grid frequency. Then, n order harmonic sequence components can be written as: By using the symmetrical component method, all voltage components can be considered as the sum of positive sequences, negative sequences and zero sequences. Applying Clark transformation to three phase voltages yields:

The Proposed PLL Structure
In this section, the voltage sequence component of non-ideal grid voltages is analyzed at first to provide the basis for the design procedure of the proposed PLL. To achieve our objective, a hybrid filtering stage based on MAFs and MDSCs is suggested and analyzed in this section. Then, it is incorporated into a QT1-PLL structure.

The Component Analysis of Distorted Grid Voltages
Under distorted grid voltage conditions, three-phase grid voltages contain fundamental frequency positive sequence (FFPS), fundamental frequency negative sequences (FFNS) and other harmonic sequence components. FFPS components can be written as follows: where V + 1 represents the amplitude of FFPS and ω is the grid frequency. Then, n order harmonic sequence components can be written as: By using the symmetrical component method, all voltage components can be considered as the sum of positive sequences, negative sequences and zero sequences. Applying Clark transformation to three phase voltages yields: In Equation (5), T αβ is the transfer matrix of Clark transformation. After applying Clark transformation, Equation (5) is as follows: Observing Equation (6), it can be found that there is no triple odd harmonic in v α and v β . In the αβ-frame, only n= +1, −5, +7, −11, +13, . . . order sequence components exist. By using Park transformation, the components in the αβ-frame turn out to be n = −2, ±6, ±12, . . . order and DC components. The voltage sequence components can be summarized in Table 1. It should be noticed that the sign of frequency represents the rotating direction of the voltage sequence vector. A negative frequency means the voltage vector rotates in a counterclockwise direction.

Harmonic
Order

The Hybrid Filtering Stage
According to the analysis of components in distorted grid voltages, a hybrid filter is well designed to eliminate the undesired components listed in Table 1. The hybrid filtering stage consists of an MDSC operator and two MAFs, which are arranged after Park transformation at the inner loop of the proposed PLL. MDSC is responsible for rejecting the FFNS component. Other dominant components are eliminated by two MAFs.
To achieve this goal, m and n, which are the parameters in MDSC, are chosen to be m = 4 and n = 8, respectively. The window length of MAF is set to be 1/300 s. The gain and phase of MDSC m=4,n=8 can be calculated by following equations.
The bode diagram of MAF and MDSC m=4,n=8 are depicted in Figure 8. The frequency characteristic reveals that MDSC m=4,n=8 (solid lines) can eliminate the FFNS component. Furthermore, MAF in Figure 8 can remove ±300 Hz, ±600 Hz, . . . sequence components. One thing should be noticed. Since the MDSC is implemented in a dq-frame, the FFPS component turns to be a DC component (0 Hz). According to Equations (7) and (8), the gain of MDSC m=4,n=8 at 0 Hz is 0.707. the phase of FFPS at 0 hz is +45 • . The impact on amplitude and phase of input vector will be discussed and compensated below. The bode plot of the entire hybrid filtering stage is depicted in Figure 9. The components list in Table 1 is totally removed. A +45 • phase deviation exists at 0 Hz owing to MDSC m=4,n=8 .

The Proposed PLL Structure
The proposed PLL structure is based on the QT1-PLL structure which is depicted in Figure 10. ωn is the nominal frequency of the grid. g  is the estimated grid frequency.

The Proposed PLL Structure
The proposed PLL structure is based on the QT1-PLL structure which is depicted in Figure 10. ωn is the nominal frequency of the grid. g  is the estimated grid frequency.

The Proposed PLL Structure
The proposed PLL structure is based on the QT1-PLL structure which is depicted in Figure 10. ω n is the nominal frequency of the grid.ω g is the estimated grid frequency.θ + 1 is the estimated phase of FFPS. The arc tangent function can remove the impact of amplitude variation of the input voltage vector. k is the only control parameter of QT1-PLL.

The Proposed PLL Structure
The proposed PLL structure is based on the QT1-PLL structure which is depicted in Figure 10. ωn is the nominal frequency of the grid. g  is the estimated grid frequency.   Replacing the MAFs in QT1-PLL by the proposed hybrid filtering stage yields the proposed PLL structure as shown in Figure 11. While arc tangent function can remove the impact of amplitude variation, phase deviation still exists. Hence, to compensate a π/4 phase deviation introduced by MDSC m=4, n=8 , which is mentioned above, −π/4 is added at the output of proposed PLL. k is the only one control parameter to be designed. Replacing the MAFs in QT1-PLL by the proposed hybrid filtering stage yields the proposed PLL structure as shown in Figure 11. While arc tangent function can remove the impact of amplitude variation, phase deviation still exists. Hence, to compensate a π/4 phase deviation introduced by MDSCm=4, n=8, which is mentioned above, −π/4 is added at the output of proposed PLL. k is the only one control parameter to be designed.

Mathematics Model and Parameters Design Procedure
According to Figure 11, the mathematics model is derived in this section. To achieve a desired dynamic response, the parameter design procedure is also given. After providing the mathematics model, the stability of the system is also examined.

Mathematics Model
After Clark transformation, the FFPS component in αβ-frame can be written as: By using Park transformation, the FFPS component in the dq-frame becomes: According to Figure 5, after MDSCm=4,n=8, the FFPS component turns out to be: (11) Since two MAFs are arrange at each control path, the arc tangent function can be considered as arranged after MDSCm=4,n=8. Then, the arc tangent operation can be expressed as: By applying trigonometric operation, Equation (12) turns out to be: Therefore, Equation (13) can be written as:

Mathematics Model and Parameters Design Procedure
According to Figure 11, the mathematics model is derived in this section. To achieve a desired dynamic response, the parameter design procedure is also given. After providing the mathematics model, the stability of the system is also examined.

Mathematics Model
After Clark transformation, the FFPS component in αβ-frame can be written as: By using Park transformation, the FFPS component in the dq-frame becomes: According to Figure 5, after MDSC m=4,n=8 , the FFPS component turns out to be: Since two MAFs are arrange at each control path, the arc tangent function can be considered as arranged after MDSC m=4,n=8 . Then, the arc tangent operation can be expressed as: By applying trigonometric operation, Equation (12) turns out to be: Therefore, Equation (13) can be written as: Energies According to the derivation of Equations (9)- (14), the mathematics model of the proposed PLL is depicted in Figure 12. D'(s) is the disturbance components injected into the input voltages. R(s) is defined as follows: Compared with the model of other existing PLLs, our mathematics model is not a small-signal model since the arc tangent function extracts phase information directly without any linearization procedure. According to the derivation of Equations (9)- (14), the mathematics model of the proposed PLL is depicted in Figure 12.

D'(s) is the disturbance components injected into the input voltages. R(s) is defined as follows:
s T e s R 8 2 1 2 1 ) (    (15) Compared with the model of other existing PLLs, our mathematics model is not a small-signal model since the arc tangent function extracts phase information directly without any linearization procedure.

Parameter design guidelines and stability analysis
To transform the proposed PLL into a traditional form of a closed-loop feedback system, block diagram algebra is utilized. The block diagram in Figure 12 is transformed to a simplified schematic shown in Figure 13. Hence, the open-loop transfer function can be written as: Then, the transfer function of phase-error can be expressed as: To calculate the settling time, inverse Laplace transformation is applied to Equations (18) and (19). Two curves of settling time as a function of k are depicted in Figure 14. When phase error is   (15) Compared with the model of other existing PLLs, our mathematics model is not a small-signal model since the arc tangent function extracts phase information directly without any linearization procedure.

Parameter design guidelines and stability analysis
To transform the proposed PLL into a traditional form of a closed-loop feedback system, block diagram algebra is utilized. The block diagram in Figure 12 is transformed to a simplified schematic shown in Figure 13. Hence, the open-loop transfer function can be written as: Then, the transfer function of phase-error can be expressed as: In this paper, a parameter is chosen by its impact on the settling time of the phase-error transfer function. With different values of k, the settling time of Ge(s) is examined. The phase-error transfer function under these two conditions is expressed by: To calculate the settling time, inverse Laplace transformation is applied to Equations (18) and (19). Two curves of settling time as a function of k are depicted in Figure 14. When phase error is

Parameter Design Guidelines and Stability Analysis
To transform the proposed PLL into a traditional form of a closed-loop feedback system, block diagram algebra is utilized. The block diagram in Figure 12 is transformed to a simplified schematic shown in Figure 13. Hence, the open-loop transfer function can be written as: Then, the transfer function of phase-error can be expressed as: In this paper, a parameter is chosen by its impact on the settling time of the phase-error transfer function. With different values of k, the settling time of G e (s) is examined. The phase-error transfer function under these two conditions is expressed by: Θ ∆ω e (s) = ∆ω s 2 G e (s) (19) To calculate the settling time, inverse Laplace transformation is applied to Equations (18) and (19). Two curves of settling time as a function of k are depicted in Figure 14. When phase error is less than 2% of step change, transient response is considered to be over. To make a trade-off under both conditions, k is selected to be 148 to achieve an optimal dynamic performance for both conditions. The settling time is around one grid period.
Energies 2018, 11, x FOR PEER REVIEW 11 of 20 less than 2% of step change, transient response is considered to be over. To make a trade-off under both conditions, k is selected to be 148 to achieve an optimal dynamic performance for both conditions. The settling time is around one grid period. Since the model of the proposed PLL contains a time delay unit, the system turns out to be a non-minimum phase system. To examine the stability, nyquist stabilization criterion is employed in this paper instead of using a bode diagram. The nyquist diagram of Gols(s) is depicted in Figure 15.  The bode diagram of the proposed PLL and QT1-PLL is depicted in Figure 16. It can be seen that the crossover frequency of the proposed PLL is larger than that in the QT1-PLL. This yields faster transient behavior for the proposed method. It is noted that the 100 Hz component is only attenuated in the bode diagram. This does not reveal the filtering capability at 100 Hz, since the Since the model of the proposed PLL contains a time delay unit, the system turns out to be a non-minimum phase system. To examine the stability, nyquist stabilization criterion is employed in this paper instead of using a bode diagram. The nyquist diagram of G ols (s) is depicted in Figure 15. The nyquist curve does not surround the (−1, j0) point, which means the closed-loop feedback system of G ols (s) is stable. The gain stability margin (GM) is 16.5 dB at 162 Hz. The phase stability margin (PM) is 45 • at 56.6 Hz.
Energies 2018, 11, x FOR PEER REVIEW 11 of 20 less than 2% of step change, transient response is considered to be over. To make a trade-off under both conditions, k is selected to be 148 to achieve an optimal dynamic performance for both conditions. The settling time is around one grid period. Since the model of the proposed PLL contains a time delay unit, the system turns out to be a non-minimum phase system. To examine the stability, nyquist stabilization criterion is employed in this paper instead of using a bode diagram. The nyquist diagram of Gols(s) is depicted in Figure 15.  The bode diagram of the proposed PLL and QT1-PLL is depicted in Figure 16. It can be seen that the crossover frequency of the proposed PLL is larger than that in the QT1-PLL. This yields faster transient behavior for the proposed method. It is noted that the 100 Hz component is only attenuated in the bode diagram. This does not reveal the filtering capability at 100 Hz, since the The bode diagram of the proposed PLL and QT1-PLL is depicted in Figure 16. It can be seen that the crossover frequency of the proposed PLL is larger than that in the QT1-PLL. This yields faster transient behavior for the proposed method. It is noted that the 100 Hz component is only attenuated in the bode diagram. This does not reveal the filtering capability at 100 Hz, since the diagram is based on the model whose input is grid phase, not grid voltages. The filtering performance is already analyzed in Section 3. Experiments are also carried out to verify the filtering capability in the next section. diagram is based on the model whose input is grid phase, not grid voltages. The filtering performance is already analyzed in Section 3. Experiments are also carried out to verify the filtering capability in the next section.

Assessment of Model Accuracy
To validate the analysis above, a simulation is implemented under two conditions. The transient behaviors of phase-errors are depicted in Figure 17. This figure shows that the phase-errors of proposed PLL and its mathematics model are equal to each other during two step change in phase and frequency. The design procedure based on the mathematics model is reasonable.

Experimental Results
In this section, experiments are carried out under several distorted grid conditions. Different from a traditional grid, when a grid is dominated by renewable energy sources, called a "weak grid", phase jump is inevitable during the process of grid faults, sudden large load tripping and other transient behavior. Wind power fluctuation is an important issue with the increasing penetration of wind power plants, which usually cause grid frequency deviation. Thus, the proposed method is also evaluated under frequency step change and frequency ramp change conditions. Owing to the existence of a large amount of power electronics elements, harmonic disturbances are injected by power converter-based equipment such as HVDC, MMC, etc. Sub/super-synchronous oscillations arising from inappropriate system configuration can also pollute grid voltages. Hence, the proposed PLL is also examined under unbalanced and harmonic distorted voltage conditions.

Assessment of Model Accuracy
To validate the analysis above, a simulation is implemented under two conditions. The transient behaviors of phase-errors are depicted in Figure 17. This figure shows that the phase-errors of proposed PLL and its mathematics model are equal to each other during two step change in phase and frequency. The design procedure based on the mathematics model is reasonable. diagram is based on the model whose input is grid phase, not grid voltages. The filtering performance is already analyzed in Section 3. Experiments are also carried out to verify the filtering capability in the next section.

Assessment of Model Accuracy
To validate the analysis above, a simulation is implemented under two conditions. The transient behaviors of phase-errors are depicted in Figure 17. This figure shows that the phase-errors of proposed PLL and its mathematics model are equal to each other during two step change in phase and frequency. The design procedure based on the mathematics model is reasonable.

Experimental Results
In this section, experiments are carried out under several distorted grid conditions. Different from a traditional grid, when a grid is dominated by renewable energy sources, called a "weak grid", phase jump is inevitable during the process of grid faults, sudden large load tripping and other transient behavior. Wind power fluctuation is an important issue with the increasing penetration of wind power plants, which usually cause grid frequency deviation. Thus, the proposed method is also evaluated under frequency step change and frequency ramp change conditions. Owing to the existence of a large amount of power electronics elements, harmonic disturbances are injected by power converter-based equipment such as HVDC, MMC, etc. Sub/super-synchronous oscillations arising from inappropriate system configuration can also pollute grid voltages. Hence, the proposed PLL is also examined under unbalanced and harmonic distorted voltage conditions.

Experimental Results
In this section, experiments are carried out under several distorted grid conditions. Different from a traditional grid, when a grid is dominated by renewable energy sources, called a "weak grid", phase jump is inevitable during the process of grid faults, sudden large load tripping and other transient behavior. Wind power fluctuation is an important issue with the increasing penetration of wind power plants, which usually cause grid frequency deviation. Thus, the proposed method is also evaluated under frequency step change and frequency ramp change conditions. Owing to the existence of a large amount of power electronics elements, harmonic disturbances are injected by power converter-based equipment such as HVDC, MMC, etc. Sub/super-synchronous oscillations arising from inappropriate system configuration can also pollute grid voltages. Hence, the proposed PLL is also examined under unbalanced and harmonic distorted voltage conditions. In this section, experiments are implemented on a real-time experimental platform to examine the performance of the proposed PLL. Three phase voltage signals are generated by a personal computer with a data acquisition board. Through the Digital-Analogy output ports, the voltages signals are exported. PLL is implemented on a digital signal processor (DSP TMS320F28335) board. After receiving voltage signals, the estimated phase and frequency are exported through DA ports on a DSP board. Oscilloscope is used to capture all waveforms.
The grid nominal frequency is 50 Hz. The sampling frequency of a digital system is 10 kHz. The zero-order hold method is used for discretization. Besides this, the proposed PLL, EGDSC-PLL [37] is also implemented as a traditional DSC-based PLL for comparative study. QT1-PLL [36] and MAF-PLL [38] are also compared to assess the performance. Figure 18 shows the setup of the experimental platform. In this section, experiments are implemented on a real-time experimental platform to examine the performance of the proposed PLL. Three phase voltage signals are generated by a personal computer with a data acquisition board. Through the Digital-Analogy output ports, the voltages signals are exported. PLL is implemented on a digital signal processor (DSP TMS320F28335) board. After receiving voltage signals, the estimated phase and frequency are exported through DA ports on a DSP board. Oscilloscope is used to capture all waveforms.
The grid nominal frequency is 50 Hz. The sampling frequency of a digital system is 10 kHz. The zero-order hold method is used for discretization. Besides this, the proposed PLL, EGDSC-PLL [37] is also implemented as a traditional DSC-based PLL for comparative study. QT1-PLL [36] and MAF-PLL [38] are also compared to assess the performance. Figure 18 shows the setup of the experimental platform.

Test Case 1: Phase Jump
The performance is evaluated when phase jump occurs in grid voltages. Figure 19 shows the waveform of three phase voltages. A +40° phase jump came up during the experiments. Figure 20 shows the transient behavior after a phase jump. It is observed that the proposed PLL provides the fastest transient response. The settling times of phase-error and estimated frequency are around one grid period. The dynamic behavior of QT1-PLL takes over 30 ms to converge. The dynamic performance of EGDSC-PLL and MAF-PLL are even more unacceptable, owing to their more than two grid period settling time. According to the requirement of a transient response in some grid codes [21,22], an accurate estimation of grid voltage information should be extracted after undesired injection of disturbance within 25 ms. EGDSC-PLL and MAF-PLL can definitely not fulfill this requirement.

Test Case 1: Phase Jump
The performance is evaluated when phase jump occurs in grid voltages. Figure 19 shows the waveform of three phase voltages. A +40 • phase jump came up during the experiments. Figure 20 shows the transient behavior after a phase jump. It is observed that the proposed PLL provides the fastest transient response. The settling times of phase-error and estimated frequency are around one grid period. The dynamic behavior of QT1-PLL takes over 30 ms to converge. The dynamic performance of EGDSC-PLL and MAF-PLL are even more unacceptable, owing to their more than two grid period settling time. According to the requirement of a transient response in some grid codes [21,22], an accurate estimation of grid voltage information should be extracted after undesired injection of disturbance within 25 ms. EGDSC-PLL and MAF-PLL can definitely not fulfill this requirement.
Energies 2018, 11, x FOR PEER REVIEW 13 of 20 In this section, experiments are implemented on a real-time experimental platform to examine the performance of the proposed PLL. Three phase voltage signals are generated by a personal computer with a data acquisition board. Through the Digital-Analogy output ports, the voltages signals are exported. PLL is implemented on a digital signal processor (DSP TMS320F28335) board. After receiving voltage signals, the estimated phase and frequency are exported through DA ports on a DSP board. Oscilloscope is used to capture all waveforms.
The grid nominal frequency is 50 Hz. The sampling frequency of a digital system is 10 kHz. The zero-order hold method is used for discretization. Besides this, the proposed PLL, EGDSC-PLL [37] is also implemented as a traditional DSC-based PLL for comparative study. QT1-PLL [36] and MAF-PLL [38] are also compared to assess the performance. Figure 18 shows the setup of the experimental platform.

Test Case 1: Phase Jump
The performance is evaluated when phase jump occurs in grid voltages. Figure 19 shows the waveform of three phase voltages. A +40° phase jump came up during the experiments. Figure 20 shows the transient behavior after a phase jump. It is observed that the proposed PLL provides the fastest transient response. The settling times of phase-error and estimated frequency are around one grid period. The dynamic behavior of QT1-PLL takes over 30 ms to converge. The dynamic performance of EGDSC-PLL and MAF-PLL are even more unacceptable, owing to their more than two grid period settling time. According to the requirement of a transient response in some grid codes [21,22], an accurate estimation of grid voltage information should be extracted after undesired injection of disturbance within 25 ms. EGDSC-PLL and MAF-PLL can definitely not fulfill this requirement.

Test Case 2: Frequency Step Change
Test case 2 is carried out when grid voltages are under +5 Hz frequency step change. Figure 21 depicts the waveform of three phase voltages. The waveform of estimated frequency and phase error are shown in Figure 22. It is observed that the proposed PLL can accurately estimate grid frequency in less than one period. The phase error of the proposed PLL can converge to zero within only 15 ms. The settling time of QT1-PLL is around one period in both estimated frequency and phase error, which is acceptable for most practical application. While EGDSC-PLL can track grid frequency as fast as QT1-PLL, the phase error takes over 30 ms to converge.

Test Case 2: Frequency Step Change
Test case 2 is carried out when grid voltages are under +5 Hz frequency step change. Figure 21 depicts the waveform of three phase voltages. The waveform of estimated frequency and phase error are shown in Figure 22. It is observed that the proposed PLL can accurately estimate grid frequency in less than one period. The phase error of the proposed PLL can converge to zero within only 15 ms. The settling time of QT1-PLL is around one period in both estimated frequency and phase error, which is acceptable for most practical application. While EGDSC-PLL can track grid frequency as fast as QT1-PLL, the phase error takes over 30 ms to converge.

Test Case 2: Frequency Step Change
Test case 2 is carried out when grid voltages are under +5 Hz frequency step change. Figure 21 depicts the waveform of three phase voltages. The waveform of estimated frequency and phase error are shown in Figure 22. It is observed that the proposed PLL can accurately estimate grid frequency in less than one period. The phase error of the proposed PLL can converge to zero within only 15 ms. The settling time of QT1-PLL is around one period in both estimated frequency and phase error, which is acceptable for most practical application. While EGDSC-PLL can track grid frequency as fast as QT1-PLL, the phase error takes over 30 ms to converge.

Test Case 2: Frequency Step Change
Test case 2 is carried out when grid voltages are under +5 Hz frequency step change. Figure 21 depicts the waveform of three phase voltages. The waveform of estimated frequency and phase error are shown in Figure 22. It is observed that the proposed PLL can accurately estimate grid frequency in less than one period. The phase error of the proposed PLL can converge to zero within only 15 ms. The settling time of QT1-PLL is around one period in both estimated frequency and phase error, which is acceptable for most practical application. While EGDSC-PLL can track grid frequency as fast as QT1-PLL, the phase error takes over 30 ms to converge.

Test Case 3: Frequency Ramp Change
In practical conditions, grid frequency can hardly have a step change. Most of time, grid frequency varies bit by bit continuously. Consequently, a ramp change is implemented to the grid frequency to examine PLLs' performance. The grid frequency rises from 50 Hz to 55 Hz with a +100 Hz/s ramp rising rate. The whole behavior last for 50 ms. Figure 23 shows the waveform of grid voltages during this rising procedure. Figure 24 shows the transient behavior of four advanced PLLs. It can be seen that the proposed PLL provides 0.5 • phase error during the frequency rising procedure. The phase error of QT1-PLL is less than 2 • , which is also acceptable. By contrast, the phase errors of EGDSC-PLL and MAF-PLL are too big, which means PLL cannot provide acceptable phase information during the frequency changing procedure.

Test Case 3: Frequency Ramp Change
In practical conditions, grid frequency can hardly have a step change. Most of time, grid frequency varies bit by bit continuously. Consequently, a ramp change is implemented to the grid frequency to examine PLLsʹ performance. The grid frequency rises from 50 Hz to 55 Hz with a +100 Hz/s ramp rising rate. The whole behavior last for 50 ms. Figure 23 shows the waveform of grid voltages during this rising procedure. Figure 24 shows the transient behavior of four advanced PLLs. It can be seen that the proposed PLL provides 0.5 o phase error during the frequency rising procedure. The phase error of QT1-PLL is less than 2°, which is also acceptable. By contrast, the phase errors of EGDSC-PLL and MAF-PLL are too big, which means PLL cannot provide acceptable phase information during the frequency changing procedure.

Test Case 4: Unbalanced and Distorted Grid Voltages
To examine the filtering capability, the proposed PLL is evaluated under unbalanced and distorted grid voltages condition. A frequency step change occurs during the experimental procedure. The parameters of voltage components in the polluted grid voltages are listed in Table 2. To achieve a satisfactory performance, the delay and MAF units in the proposed PLL, QT1-PLL and MAF-PLL are frequency adaptive. The corresponding implementation of a frequency adaptive structure can be found in [36] and [38]. While EGDSC-PLL can also improve its performance by

Test Case 3: Frequency Ramp Change
In practical conditions, grid frequency can hardly have a step change. Most of time, grid frequency varies bit by bit continuously. Consequently, a ramp change is implemented to the grid frequency to examine PLLsʹ performance. The grid frequency rises from 50 Hz to 55 Hz with a +100 Hz/s ramp rising rate. The whole behavior last for 50 ms. Figure 23 shows the waveform of grid voltages during this rising procedure. Figure 24 shows the transient behavior of four advanced PLLs. It can be seen that the proposed PLL provides 0.5 o phase error during the frequency rising procedure. The phase error of QT1-PLL is less than 2°, which is also acceptable. By contrast, the phase errors of EGDSC-PLL and MAF-PLL are too big, which means PLL cannot provide acceptable phase information during the frequency changing procedure.

Test Case 4: Unbalanced and Distorted Grid Voltages
To examine the filtering capability, the proposed PLL is evaluated under unbalanced and distorted grid voltages condition. A frequency step change occurs during the experimental procedure. The parameters of voltage components in the polluted grid voltages are listed in Table 2. To achieve a satisfactory performance, the delay and MAF units in the proposed PLL, QT1-PLL and MAF-PLL are frequency adaptive. The corresponding implementation of a frequency adaptive structure can be found in [36] and [38]. While EGDSC-PLL can also improve its performance by

Test Case 4: Unbalanced and Distorted Grid Voltages
To examine the filtering capability, the proposed PLL is evaluated under unbalanced and distorted grid voltages condition. A frequency step change occurs during the experimental procedure. The parameters of voltage components in the polluted grid voltages are listed in Table 2. To achieve a satisfactory performance, the delay and MAF units in the proposed PLL, QT1-PLL and MAF-PLL are frequency adaptive. The corresponding implementation of a frequency adaptive structure can be found in [36] and [38]. While EGDSC-PLL can also improve its performance by making DSCs adaptive, too many DSCs used in its filtering stage increases its computational burden dramatically. Hence, EGDSC-PLL with non-adaptive DSCs is more practical for the comparison. Fundamental positive sequence (+1st order) 1 Fundamental negative sequence (−1st order) 0.1 5 th harmonic negative sequence (−5th order) 0.1 7 th harmonic positive sequence (+7th order) 0.05 11 th harmonic negative sequence (−11th order) 0.05 13 th harmonic positive sequence (+13th order) 0.05 The polluted grid voltages are depicted in Figure 25. The transient responses of four PLLs are depicted in Figure 26. It can be observed that all PLLs can eliminate disturbances completely when grid frequency is at its nominal value. When grid frequency jumps from 50 Hz to 55 Hz, transient behavior occurs for every PLL. Thanks to frequency adaptive implementation, the proposed PLL, QT1-PLL and MAF-PLL can still provide a satisfactory filtering capability after frequency change. However, oscillation of phase error occurs in the transient behavior of EGDSC-PLLs for its non-adaptive DSCs. While this problem can be solved by applying adaptive DSCs, a huge computational burden is still a big problem for designers to solve.  Voltage Component (in αβ-frame) Amplitude (p.u.) Fundamental positive sequence (+1st order) 1 Fundamental negative sequence (−1st order) 0.1 5 th harmonic negative sequence (−5th order) 0.1 7 th harmonic positive sequence (+7th order) 0.05 11 th harmonic negative sequence (−11th order) 0.05 13 th harmonic positive sequence (+13th order) 0.05 The polluted grid voltages are depicted in Figure 25. The transient responses of four PLLs are depicted in Figure 26. It can be observed that all PLLs can eliminate disturbances completely when grid frequency is at its nominal value. When grid frequency jumps from 50 Hz to 55 Hz, transient behavior occurs for every PLL. Thanks to frequency adaptive implementation, the proposed PLL, QT1-PLL and MAF-PLL can still provide a satisfactory filtering capability after frequency change. However, oscillation of phase error occurs in the transient behavior of EGDSC-PLLs for its non-adaptive DSCs. While this problem can be solved by applying adaptive DSCs, a huge computational burden is still a big problem for designers to solve.

Conclusions
With more and more wind and solar energy plants connected to power systems, grid voltages are prone to be distorted. To keep grid frequency and phase tracking accuracy during distorted and  Voltage Component (in αβ-frame) Amplitude (p.u.) Fundamental positive sequence (+1st order) 1 Fundamental negative sequence (−1st order) 0.1 5 th harmonic negative sequence (−5th order) 0.1 7 th harmonic positive sequence (+7th order) 0.05 11 th harmonic negative sequence (−11th order) 0.05 13 th harmonic positive sequence (+13th order) 0.05 The polluted grid voltages are depicted in Figure 25. The transient responses of four PLLs are depicted in Figure 26. It can be observed that all PLLs can eliminate disturbances completely when grid frequency is at its nominal value. When grid frequency jumps from 50 Hz to 55 Hz, transient behavior occurs for every PLL. Thanks to frequency adaptive implementation, the proposed PLL, QT1-PLL and MAF-PLL can still provide a satisfactory filtering capability after frequency change. However, oscillation of phase error occurs in the transient behavior of EGDSC-PLLs for its non-adaptive DSCs. While this problem can be solved by applying adaptive DSCs, a huge computational burden is still a big problem for designers to solve.

Conclusions
With more and more wind and solar energy plants connected to power systems, grid voltages are prone to be distorted. To keep grid frequency and phase tracking accuracy during distorted and

Conclusions
With more and more wind and solar energy plants connected to power systems, grid voltages are prone to be distorted. To keep grid frequency and phase tracking accuracy during distorted and even faulty conditions without degrading dynamic performance, a hybrid filter-based PLL is proposed. By using well designed MDSCs and MAFs with narrowed window length, time delay introduced by filtering stage is reduced. The hybrid filtering stage is incorporated with a QT1-PLL structure. A comprehensive experimental study is implemented to examine the effectiveness. Test cases concerning several conditions, which are easily triggered in high renewable penetration power systems, are carried out. Experimental results illustrate that the proposed PLL can provide a more satisfactory dynamic response than other traditional methods. The filtering capability and implementation complexity are also better than the conventional DSC-based PLLs.