Review, Comprehensive Analysis and Derivation of Analytical Power Loss Calculation Equations for Two- to Three-Level Midpoint Clamped Inverter Topologies with Hybrid Switch Configurations

Abstract

Increased performance requirements in new power electronics areas of application, such as electric aircraft, make innovations on different design levels necessary. In order to quickly compare different topologies, analytical loss equations provide a fast and straightforward way to narrow down the possible solution space. The approach widely used in the literature results in long and complex terms, which can only be compared between different literature sources with great effort. Moreover, the literature lacks a detailed summarizing description of these analytical equations and their derivation, starting from the standard two-level VSI up to three-level midpoint clamped inverter topologies, such as the ANPC topology in its different modulation schemes. The application of such higher-level inverter topologies allows hybrid device configurations to become performant solutions. This work aims to give a closed-form description of the analytical loss modeling and the theoretical background and provide an implementation approach for a wide span of inverter topologies and for different modulation methods.

1. Introduction

In power electronics, increasing converter performance and thus entering new application areas is usually achieved by the introduction of new building blocks for converter design. Such building blocks can be, for example, new components, topologies, or control schemes. The benefits that can be achieved are always limited by the current state of research and, thus, availability. Examples of novel power components are new or significantly improved semiconductors, but also magnetics, capacitors, or cooling solutions [1]. On the semiconductor side, this includes novel switch types, such as the high-electron-mobility transistor (HEMT) [2]; materials, such as wide-bandgap (WBG) materials (currently primarily SiC and GaN); and novel packaging options. As innovative novel topologies, the H5 topology for PV inverters [3] or the ANPC topology [4] (Figure 1) can be named. Beyond this, the integration of, e.g., emerging semiconductors and existing topologies offers new solutions for challenges faced in new areas of application.

One such application area currently being strongly researched is the electrification of aircraft, where global mobility is increasingly confronted with the societal need to reduce the impact of air travel on the environment significantly. The proposed solutions in this sector range from the electrification of some peripheral systems, such as pneumatic loads in so-called More Electric Aircraft (MEA), to All-Electric Aircraft (AEA), where all thrust components are replaced by electric machines [5].

The set of required performance parameters for this novel application area is shown in Figure 2. In aerospace applications, efficiency, size (weight and volume), reliability, and electromagnetic compatibility (EMC), as well as electromagnetic interference (EMI), are especially pronounced. Power electronics in general and the drive inverters play a crucial role in interconnecting sources and loads as part of the electric energy distribution system. They have to be designed in such a way that they can contribute to these goals while functioning in the overall system.

Generally speaking, the electric system of an AEA is expected to be characterized by the presence of a high DC voltage, and a high inverter output power will be required. DC voltages are preferred to decouple sources and loads, and high voltages are preferred for the transmission of high power because, in this way, the current per conductor and, with it, the conductor diameter is decreased. This reduces the system weight and contributes to a higher overall power density [5]. Furthermore, high requirements on the efficiency and power density of the inverter itself, as well as the inverter output power quality, prevail.

The use of new WBG semiconductor devices is particularly attractive for aerospace applications, where efficiency and power density are of primary concern. The use of WBG components enables the efficient utilization of higher switching frequencies and, thus, a reduction in the size of passive components.

However, using WBG devices in variable-speed drive applications also poses some challenges. The fast switching transitions at the inverter output can have a negative impact on the driven electrical machine. Either additional stress and losses in the machine are imposed, or the effect is counteracted by dedicated filtering at the inverter output, which in turn negatively affects the power density of the system [7].

Further, the application of such WBG devices is hindered by high DC link voltages, which require the use of switches with high breakdown voltages, especially in aerospace applications, where an additional voltage safety margin has to be considered due to, for example, cosmic radiation. In particular, for the emerging WBG devices, where development is not as advanced in terms of breakdown voltages (see

Table 1. Power semiconductor technologies and available breakdown voltage range [8].

	Available Voltage Classes	Switching Frequency Range	Output Power Range
Si IGBTs	up to 6.5 kV	up to 100 kHz	up to several hundred kilowatts
Si SJ MOSFETs	up to 950 V	up to 1 MHz	up to several kilowatts
SiC MOSFETs	650 V up to 3.3 kV	up to 1 MHz	up to several hundred kilowatts
GaN eHEMTs	up to 650 V	up to 10 MHz	up to several kilowatts

), multi-level topologies, which do not stress the individual switches with the full DC link voltage, could be used. In the following, neutral-point clamped—more specifically, three-level midpoint clamped—topologies will be discussed.

Besides these neutral-point clamped-type topologies, which are being most frequently investigated for electric aircraft applications due to their high power densities [9,10], other topologies such as multi-level flying capacitor (FC) converters, modular multi-level converters (MMCs), or cascaded H-bridge multi-level inverters (CHBs) exist. Cascaded H-bridge multi-level inverters (CHBs) consist of multiple single-phase H-bridges connected in a cascade. The modular setup allows a cost reduction. The CHB topology requires an isolated DC power supply per H-bridge power cell, necessitating additional circuit hardware [11]. Modular multi-level converters (MMCs) consist of series connections of half bridges, each in the upper and lower leg branches. However, especially for weight-sensitive application areas, the required branch inductors increase the converter weight significantly, resulting in low power density compared to the other topologies [9]. Multi-level inverters with flying capacitors (FC) [12] represent another important type of multi-level topology. In this topology, so-called flying capacitor cells are connected by a capacitor [13]. Increasing the number of steps in the AC output voltage is possible by adding more flying capacitor cells and capacitors. Extra passive components are required, which compromise the converter power density, especially because every flying capacitor is sequentially charged and discharged with the load current [14]. The suitability of FC converters for aviation is deemed critical due to the additional weight and reduced reliability associated with the flying capacitors, and they, therefore, are not considered in this work. To overcome the inherent limitations of this topology, innovative control strategies and sophisticated hardware designs are required. To take advantage of GaN semiconductors by using these devices in combination with a high voltage level count [15,16,17] and in combination with interleaving to increase the power rating [18], this topology can be applicable.

In order to increase the power density and efficiency of the overall system, multi-level topologies, as well as novel WBG power semiconductors that enable high-frequency switching, must be employed. The following work is intended to help to identify inverter topologies and devices to be used in order to unlock their full potential.

For the prediction of losses and, therefore, efficiency in power semiconductors, various methods exist. One possibility is the complete numerical simulation of the circuit. This allows detailed information to be obtained not only in terms of efficiency but also, for example, to investigate the influence of parasitic elements. However, the disadvantage of this approach is that computational resources are required, and the simulations can take a long time [19]. To quickly compare different topologies utilizing different types of switches, analytical models provide a fast and straightforward way to narrow down the possible solution space. The most widely used approach to the setup of these analytical equations is the use of conduction as well as switching intervals and modulation functions in combination with device parameters that can be obtained easily from the manufacturer’s data sheets.

In [9], analytical loss equations are used to establish an analytical efficiency and power density model for a study on future all-electric aircraft propulsion systems. However, the derivation, explanation, and application of these equations are not part of this work. Furthermore, the different active neutral-point clamped (ANPC) modulation schemes are not fully discussed. Ref. [20] presents analytical loss calculation expressions for the semiconductor devices in a T-type neutral-point clamped (TNPC) topology and proposes a loss-balancing scheme for this topology. Equations for the conventional neutral-point clamped (NPC) topology are also provided.

In [21], a comprehensive overview of various ANPC modulation schemes and associated analytical power dissipation equations is provided. The microcontroller implementation of the pulse width modulation (PWM) channels is discussed, and state diagrams are provided for the different modulation strategies, also discussing the transitions between the switching states.

Publication [22] discusses the analytical approach to determining the converter’s efficiency. However, as in [21], the motivation for using such multi-level inverter topologies, as well as much of the theoretical background, is not discussed. In addition, the two-level voltage source inverter (VSI) or the TNPC topology is not discussed in detail. This would be desirable for comparison reasons and a more complete overview of the inverter landscape.

The modeling in [23] includes the standard two-level inverter, as well as TNPC and NPC topologies for hybrid switch configurations. However, the ANPC topology and its associated degrees of freedom in different modulation strategies are not considered. Meanwhile, ref. [24] utilizes analytical equations for the power loss modeling of a GaN HEMT-based three-level ANPC inverter for different PWM techniques. While it provides a good overview of the different carrier-based modulation techniques (comparable to the one in [25]), only unipolar devices are considered, and switching loss calculation is simplified.

While all publications refer to the use of part of the analytical loss equations discussed in this work, not all provide a closed set of complete equations or the complete disclosure of the modulation functions and conduction intervals to be applied. Research that, in a closed form, examines the theoretical background and provides implementation approaches while covering the range from standard two-level VSI topologies up to the three-level ANPC topology in its various modulation schemes, does not exist.

Despite requiring significantly fewer data than numerical models, one distinct disadvantage of the analytical power loss calculation approach for multi-level inverters is that they quickly result in long and complex terms. The integration that has to be performed to obtain the loss equations (see Section 4) is both prone to human error and time-consuming to implement. The equations’ implementation has to be performed with great care. To aid this, this publication aims to establish a shared foundation for the understanding and cross-verification of the analytical power loss calculations of two- to three-level topologies.

In the first section, a general introduction to the motivation in using multi-level inverter topologies is given. In Section 2, this work provides a comprehensive overview of the most widespread midpoint clamped three-level topologies and the conventional two-level VSI as a reference. Their general setup, advantages, and disadvantages are discussed. With respect to the extended degrees of freedom and, therefore, the capabilities offered by the ANPC topology, the inverter modulation methods and schemes are discussed in Section 3. Section 4 aims to offer a deep understanding of the fundamentals of analytical power loss calculation for each topology and for different pulse width modulation methods. Modulation functions, conduction as well as switching intervals, and the obtainment of the analytical loss formulas through integration are reviewed in detail. In Section 5, design, packaging, and thermal aspects for the realization of such (multi-level) inverters are discussed. Using the previously described approach, power loss analysis is performed for different topologies, (hybrid) device configurations, and modulation schemes. Section 6 concludes and provides readers with potential future research directions.

2. Inverter Circuit Topology

Different inverter topologies can be grouped and characterized according to a variety of properties. One possible means of classifying these topologies is by the design of the DC link, especially the DC link’s number of discrete voltage levels. In theory, e.g., to improve the inverter output voltage quality, high-number-level topologies exist. In practice, however, a compromise must be found between the achievable benefits and resulting complexity. In this work, two- to three-level midpoint clamped topologies will be reviewed. This selection has been explained in Section 1.

In the following sections, first, the standard two-level VSI topology and subsequently the three-level midpoint clamped topologies shown in Figure 1 will be discussed. For the reasons stated above, the previously named topologies are not considered suitable for higher-power and weight-sensitive applications and are therefore not part of the following analysis.

2.1. Two-Level Topologies

Standard Two-Level Voltage Source Inverter

The standard inverter topology used today is the two-level voltage source inverter (VSI). With a few exceptions (such as applications related to photovoltaics [26]), this topology is commonly used in the industrial sector, e.g., to drive electrical machines through DC busses [27]. The main reasons for its widespread use are its minimal component count, simplicity, and therefore cost [28]. However, the blocking voltage of the applied semiconductors has to be as large as or larger than the DC bus voltage. In general, a higher blocking voltage results in increased switching loss (for a fixed current/voltage combination), which is due to the non-linear relation between the blocking voltage and switching energy (see Figure 3). This leads to a reduction in the efficiency of this topology for higher switching frequencies due the increased switching losses [29]. Because the overall goal generally is efficient converters, a lower switching frequency could be used to decrease the power losses. However, when broadening the view from efficiency alone to other performance measures, such as volume and weight, the size reduction of passive components to achieve a high power density mainly is achieved by higher switching frequencies. For two reasons, the application of emerging wide-bandgap (WBG) semiconductors in this two-level topology is challenging. First, one prominent advantage when applying WBG power semiconductors is the allowable decrease in the size of passive devices through a higher switching frequency [29]. Moreover, a high blocking voltage requirement limits the applicability of these promising technologies, which generally still have lower breakdown voltages compared to their silicon counterparts (see Table 1).

Especially for aerospace applications, these limitations are challenging. A higher DC link voltage, which results in lighter cables or loss and higher power density, and is therefore desired, is difficult to achieve with the use of WBG power devices. Moreover, the required low switching frequency for the efficient operation of the two-level VSI, and its poor output voltage quality, make heavy and bulky passive filter components necessary. The intrinsically higher EMI noise emissions at the inverter output are problematic [28] due to strict regulations in this application area.

Introducing more than two voltage levels in so-called multi-level inverters helps to address the challenges previously mentioned. A lower breakdown voltage requirement allows for the use of low-voltage-rating WBG semiconductors. Since the inverter output voltage is generated in steps depending on the level number, its waveform approximates the desired sinusoidal shape more closely. Due to the lower dependence of the inverter efficiency on the switching frequency [32], high-frequency operation and its associated benefits are feasible.

On the machine side, introducing another voltage level is beneficial in many ways. Three-level topologies contain lower harmonic content in the AC output [9,27]. Reduced $dv/dt$ at the motor terminal leads to less electrical stress on the motor insulation [33]. Overvoltages at motor terminals are reduced, because the less steep rising and falling edges mitigate the impedance mismatch, which would otherwise cause problematic reflection phenomena along the cable [15]. Moreover, unwanted bearing currents and shaft voltages are reduced [34].

On the other hand, multi-level inverters feature a higher part count, increased complexity, and therefore higher initial costs. Additional gate drives are needed as the number of semiconductor switches increases and, due to the more possible switching states [35], the modulation method that generates the control signals for the inverter is also more complex. Issues such as DC link balancing or the selection of redundant space vectors in the case of ANPC space-vector modulation [36] arise. DC link balancing is not discussed in this paper. However, it may be mentioned that greater freedom in the choice of different redundant switching states allows for better controllability of the DC link imbalance (see Section 3.2).

A large number of multi-level topologies are described in the literature and each topology has its own advantages and disadvantages. In theory, the number of levels could be high, but, in practice, a compromise must be found between the resulting benefits and increasing complexity. In this study, three-level midpoint clamped inverter topologies will be discussed in detail. The following Section 2.2 aims to explore their characteristics and give an insight into the topologies’ functioning principles.

2.2. Three-Level Topologies

2.2.1. Neutral-Point Clamped (NPC) Converter

A three-level NPC converter phase leg using MOSFETs is shown in Figure 1b. In comparison to the previously discussed two-level inverter, this topology, proposed first in [37], employs two extra semiconductor switches with their associated freewheeling diodes and clamps the neutral point to the phase output using two extra so-called clamping diodes. This configuration allows the required blocking voltage to be divided between two devices (T1 and T2 or T3 and T4). For standard two-level VSI, the general consensus suggests a blocking voltage of $1/2$ up to $2/3$ larger than the DC bus voltage, which is due to expected voltage overshoots and, especially in aircraft applications, also the influence of cosmic radiation [5]. In a three-level NPC converter, however, $650$V or $1200$V semiconductors can be considered suitable, or, for DC link voltages, $800$V or $1500$V, respectively [35]. Both of these voltage levels are repeatedly named values when discussing future electric aircraft energy systems. Given its additional voltage level, an NPC inverter’s AC output current THD and $dv/dt$ can be reduced in comparison to two-level topologies. This, however, comes at the cost of a more sophisticated switching pattern, and an imbalance in losses for the different switching positions occurs. The switch positions heat up differently and losses concentrate at certain positions [20]. All three-level inverter topologies, influenced by the different modulation strategies, are faced with the issue of DC link capacitor voltage balance, which, influenced by the different modulation strategies, has different effects on the charging and discharging of the DC link series capacitors. Different voltage ripples in these capacitors result in different losses. However, in this article, only the losses of the active switching devices are studied, and therefore the problem of DC link imbalance is not discussed further. Without additional measures, DC link imbalance issues generally lead to larger required DC link capacitance [27,29], which increases this component’s weight.

2.2.2. T-Type Neutral-Point Clamped (TNPC) Converter

The T-type NPC converter is shown in Figure 1c as well. This topology can be seen as a two-level VSI, extended by a bidirectional switch connecting the DC link capacitor’s midpoint to the phase output, combining the two-level VSI’s advantages (e.g., low conduction losses) with the three-level NPC converter’s benefits [27]. While the upper (high-side) and lower (low-side) switches still have to block at least the full DC link voltage, the bidirectional switch is subjected to only half the DC link voltage. This reduced required blocking voltage results in acceptable conduction losses despite the series connection of two devices and low switching losses in the middle switch [20] (see Figure 3). Moreover, only one switch at a time has to block the full DC link voltage in this topology; therefore, the conduction losses in this current path can be reduced. The same switching pattern can be used for both the three-level NPC and TNPC topologies [32].

2.2.3. Active Neutral-Point Clamped (ANPC) Converter

The ANPC converter, first proposed by [4], is an extension of the NPC topology where two extra active switches are connected in parallel with the clamping diodes. Using these extra two switches, a more uniform loss distribution among the semiconductors can be achieved while not significantly altering the system efficiency. As for the NPC topology, all switches are subjected to only half the DC link voltage. The increased circuit complexity also becomes evident in the required number of semiconductor devices. The six required transistor–diode pairs in a three-phase two-level VSI stand in contrast to the required 18 in an ANPC topology. Additional gate drive circuits are needed. Using these extra two switches, the neutral state current flow can be actively controlled since two current paths for the neutral state exist, leading to a more uniform loss distribution. In addition to a better loss distribution between semiconductor devices, the redundant switching states can be used to balance the voltages of the DC link capacitors, tackling the DC link voltage unbalance, which occurs periodically in three-level topologies. The upper neutral path is formed by switches T5 and T2 (and their antiparallel diodes), and the lower one is formed by T6 and T3 (and their antiparallel diodes). A better power loss distribution can be achieved by careful selection of the current paths [20,27,38]. This added degree of freedom offers the possibility of multiple modulation schemes to generate the gate signals of an ANPC inverter. Four typical modulation schemes will be discussed in Section 3.2.

In summary, despite the increased circuit complexity and the number of required semiconductors, the three-level topologies described have significant advantages. Depending on the three-level topology, they do not stress the individual switches with the full DC link voltage and are, therefore, a viable option to increase the DC link voltage without having to increase the voltage requirements for the individual switches. Through the increased number of switching positions, losses are distributed over many semiconductors, which provides extended degrees of freedom in converter operation and thermal design. For some topologies, the flexibility offered by the increased number of switch positions and resulting multiple redundant commutation paths results in improved post-fault performance. Furthermore, compared to the standard two-level inverter topology, multi-level inverters incorporate intrinsically lower EMI noise emissions at the inverter output since the waveform approximates the desired sinusoidal shape better [27]. This is beneficial in applications with stringent noise emission regulations but also helps to reduce the size of passive filter components and shift losses away from the already heavily stressed electrical machines.

As mentioned, there exist a variety of possibilities to control the switches applied in the described topologies. With an increasing level number and circuit complexity, more such possibilities result. In the following Section 3, the modulation methods to generate the switches’ gate signals are discussed. A special emphasis is placed on the extended degrees of freedom and, therefore, the capabilities offered by the ANPC topology.

3. Modulation

3.1. Modulation Schemes

The modulation method generates the gate signals for the inverters’ switching elements. Common modulation methods are carrier-based methods, space-vector-based pulse width modulation (PWM) methods, and selective harmonic elimination schemes [11].

Space vector modulation (SVM) represents the state-of-the-art method to control the power transistors of an inverter. In this method, the concept of space vectors is used. These represent discrete voltage vectors, to which appropriate dwell times are assigned. This method generates low harmonic distortion at the inverter output. The RMS fundamental line-to-line voltage utilization ratio of $70.7$% of the DC link voltage in the linear modulation range is larger than for the subsequently described simple carrier-based modulation.

A well-known carrier-based modulation method is the so-called sinusoidal width pulse modulation (SPWM). For a two-level voltage source inverter, the control pulses are generated by comparing a low-frequency sinusoidal reference signal, or modulating wave (which represents the desired line-to-neutral voltage at fundamental frequency), to a high-frequency triangular carrier signal. The ratio of the amplitudes of these two signals to each other is known as the (amplitude) modulation index $m_a$ or simply m. The ratio of the two signals’ period times is called the frequency modulation index $m_f$. Generally, the frequency of the carrier wave is a large multiple of the frequency of the modulating wave [39], resulting in so-called synchronous PWM [11]. A drawback of this simple modulation method is the poorer voltage utilization, with a utilization ratio of $61.2$% of the DC link voltage in the linear modulation range. Compared to SVM, this is lower by a factor of $0.865$. Furthermore, this method generates more harmonic distortion in the output currents. Especially as the modulation index increases, SPWM’s performance in terms of harmonic distortion rapidly degrades.

This drawback can be overcome by inserting a so-called zero-sequence signal $v_0$, or common mode offset (CMO), into the modulating signal. Through the insertion of such an offset, the output current THD can be reduced and the linearity range of the output voltage can be increased [40]. One example of this is the third harmonic injection (THI) PWM. Here, the third harmonic of the fundamental wave is used as the zero-sequence signal (see Figure 4 and Equation (1)). Similarly, SVM can be implemented by carrier-based PWM [39] through the insertion of a zero-sequence signal (SVPWM). In this case, the CMO consists of the minimum and maximum instantaneous values of the three 120° phase-shifted sinusoidal modulating waves [24] (Figure 4). The zero-sequence signals to be injected in order to obtain the waveforms pictured in Figure 4 can be found in (1). The insertion of such a (time) continuous signal leads to so-called continuous PWM (CPWM). Discontinuous PWM (DPWM) results when discontinuous modulation waves are used to further increase the voltage linearity range and reduce switching losses [40].

$$\begin{array}{cc}\hfill & v_{0,SPWM}=0\hfill \\ \hfill & v_{0,THIPWM}=+\frac{1}{6}sin\left(3\theta \right)\hfill \\ \hfill & v_{0,SVPWM}=-\frac{max(u_a,u_b,u_c)+min(u_a,u_b,u_c)}{2}\hfill \end{array}$$

(1)

An advantage of this carrier-based modulation is that it can be easily adapted to multi-level topologies. Multi-level inverter-adapted SPWM is achieved by using offset carrier signals (multi-carrier PWM) to compare to a modulating wave and thus generate the control pulses. In a three-level topology, two (triangular) carriers are needed. There are several options to rearrange these two carrier signals in relation to each other. Examples are the phase disposition (PD), phase shift (PS), phase opposition disposition (POD), or alternative phase opposition disposition (APOD) methods. More information on multi-level inverter multi-carrier PWM techniques can be found, for instance, in [36,40,41]. Examples of PD, PS, and POD carrier signals (three-level case) are shown in Figure 5.

In the following Section 3.2, a more detailed review of the modulation of the gate signals for a three-level ANPC topology will be given. The focus will not be on evaluating the resulting differences in the application of the different carriers—for instance, in terms of the THD and line voltage, which vary slightly [36]. Instead, the different switching frequencies of the switches at different intervals of the fundamental period in the different modulation schemes, as well as their complementary switching behavior, shall be emphasized and visualized (see Figure 6) In order to do so, PD-PWM will be used since no additional overlap or shift in phase angles has to be considered, and the carrier signals are simply placed above and below the zero reference. However, e.g., POD could have been used to emphasize these points equally well.

3.2. Three-Phase Three-Level (A)NPC Modulation

In this section, the generation of the gate signals for the NPC and ANPC topology is discussed. As described in Section 3.1, with an ANPC converter, in contrast to a two-level topology, there are extended possibilities for shifting between switching states. The main difference between the modulation schemes is the neutral current path to output the zero state. The modulation schemes intentionally configure this neutral current path while not affecting each leg’s output voltage. This neutral current path enables a greater number of voltage levels in the output compared to traditional two-level inverters, which reduces the harmonic content and improves the output quality, making the ANPC topology suitable for applications where high-quality output voltage waveforms are required. The flexibility offered by the increased number of switch positions and multiple redundant commutation paths results in improved post-fault performance. ‘Limp home’ operational mode can be implemented, and the inverter can continue to operate at reduced power [42,43]. This is essential for safety-critical application areas such as aviation. The extended degrees of freedom make the implementation of novel modulation algorithms possible, which helps to optimize the loss distribution and EMI performance. Optimizing the distribution of losses allows for the equalization of the junction temperatures, which improves the reliability and benefits the cooling system. Furthermore, the extended degrees of freedom in ANPC inverters enable better voltage balancing among the switching devices and within the DC link.

Four typical modulation schemes for the ANPC topology will be discussed [21,22,24,25]. Figure 6 gives an overview of the different modulation strategies and resulting switching patterns for each switching position in the ANPC topology. As mentioned in the previous Section 3.1, a zero-sequence signal can be injected into the modulating sine wave to alter the output voltage. This approach is also applicable here but is not shown or described for simplicity reasons. It will be addressed again later in the course of this work.

3.2.1. ANPC Modulation Scheme 0

As with the three-level TNPC topology, where an equivalent to the standard two-level VSI is achieved by permanently turning off the bidirectional switch, the ANPC topology can also be operated in an NPC manner. Therefore, this modulation scheme practically equals the NPC modulation. Modulation scheme 0 constantly keeps the switches T5 and T6 off, making only their anti-parallel diodes available for midpoint clamping. The switching pattern for this modulation scheme is shown in Figure 6a. In this case, the gate signals are generated by a modulating sine wave and two triangular carrier signals in PD-PWM. The upper carrier is used to switch on T1 and T3 complementarily over half the line cycle, while the lower carrier is responsible for generating the control signals for T2 and T4 over the other half of the fundamental period. While T1 and T3 operate at $f_{sw}$, T2 and T4 are kept on and off, respectively. As mentioned, the transistors T5 and T6 are switched off over the whole fundamental period [24,25].

3.2.2. ANPC Modulation Scheme 1

In this scheme, only T1 and T4, as well as T5 and T6, are modulated at the switching frequency and in a complementary manner over half the fundamental period, while remaining in a constant state over the other half. The inner switches T2 and T3 are turned on during the entire positive or negative half cycle of the current, respectively. While not being operated at a high switching frequency, switches T1 and T4 are constantly kept off, and switches T5 and T6 are constantly kept on [22,24,25]. The resulting gate signals for this scheme are given in Figure 6b. The switching losses in the slow-switching inner switches are expected to be low and the conduction losses in these switches are not dependent on the modulation index [22]. This makes a hybrid construction using different semiconductor material switch types feasible. The inner switches T2 and T3 could be realized by Si IGBTs, with excellent conduction but poor switching characteristics, therefore allowing for a cost reduction considering the good availability of Si IGBTs. The outer switches could be realized with SiC MOSFETs. In this modulation scheme, the neutral current path is located in the upper cell for the positive half cycle (top cell commutation) and the lower cell for the negative half cycle (bottom cell commutation), resulting in so-called ‘same-side clamping’. Making use of only these short, low-stray-inductance commutation paths results in the good suitability of this modulation scheme for a setup where each cell is implemented by a half-bridge module [21]. For more details on the application aspects, refer to Section 5.

3.2.3. ANPC Modulation Scheme 2

In contrast to the previous modulation scheme 1, in modulation scheme 2, there is only one high-frequency switch pair (T2 and T3), but four switches operate at the fundamental frequency (T1 and T4, T5, and T6) [21]. This modulation scheme again allows for the possibility of using higher-performance components only for inner switches T2 and T3, where high switching losses are expected. Here, the complementary switch pair T2 and T3 is modulated by the upper carrier for the positive and by the lower carrier for the negative half cycle [24,25] (see Figure 6c). T1 and T6 are kept off for the negative half cycle. T4 and T5 are kept off for the positive half cycle. This scheme uses only long commutation paths (‘opposite-side clamping’), which accentuates parasitic elements in this longer commutation circuit and makes the use of integrated and optimized three-level power modules advisable.

3.2.4. ANPC Modulation Scheme 3

In modulation scheme 3, we alternate between the fundamental and switching frequency [22]. T3 and T5 are switched simultaneously and are operated complementarily to T1. The gate signals of these switches are generated using the upper carrier wave. T4 is switched complementarily to the switches T2 and T6, the latter of which are turned on and off simultaneously. The lower carrier wave is used. In this scheme, the upper and lower neutral current paths are used together, which yields the name ‘full-path clamping’ [24,25]. The two parallel current paths reduce the conduction loss during the neutral state and allow for more uniform switch utilization. The trade-off is higher switching loss. This scheme is well suited for the use of SiC MOSFETs, not only due to their good switching performance but also their higher $R_{DS\left(on\right)}$ positive temperature coefficient, resulting in excellent current sharing capabilities [44].

While the various ANPC modulation schemes, as discussed, do not alter the output voltage waveforms of the individual phase legs, a more uniform loss distribution can be achieved. Analytical models can be used to predict the losses and their distribution over the different switch positions, not only for the ANPC but also for the other discussed topologies.

4. Analytical Power Loss Modeling

Power losses consist of a number of individual loss components. While components such as driving as well as blocking losses are usually neglected, the static on-state (conduction) losses and the switching losses (turn-on, turn-off, reverse recovery losses) mainly determine the expected power dissipation in the switching component [8]. Various methods exist for the prediction of losses in power semiconductors. One possibility is the complete numerical simulation of the circuit. This allows detailed information to be obtained not only in terms of efficiency but also, for example, to investigate the influence of parasitic elements. For basic investigations, however, in order to gain a general understanding, and to compare different inverter topologies, analytical calculations are beneficial [19,22]. This allows us to identify the dependencies of the losses on different device parameters (e.g., conduction and switching characteristics), operating conditions (e.g., current, voltage, power factor), topologies, and modulation schemes. In the following subsections, first, the analytical calculation of the conduction losses is reviewed. Subsequently, the approach for the switching losses is described.

Some simplifying assumptions have to be made when formulating the analytical loss equations. Simplifications made are as follows.

• The constant switching frequency is assumed to be large in comparison to the fundamental frequency ($f_{sw}>>f_{out}$).
• For the phase current, a sinusoidal waveform is assumed, not considering current ripple.
• Dead times or transistor and diode switching times are not taken into account. This may lead to a systematic underestimation of the total losses.
• There are limitations for reverse conducting power devices such as MOSFETs: current sharing between parallel paths is not taken into account.

In the first step, as for the description of the modulation schemes, sine-triangle PWM (SPWM) will be used to simplify the analysis. The literature suggests SPWM as a good approximation for the power loss calculation [19]. However, with the later presented calculation approach, it will be possible to investigate other continuous PWM schemes.

4.1. Conduction Losses

The calculation of the conduction losses is based on a simple analytical description of the operating point and subsequent integration of the loss formulas over a fundamental period [45]. For the steady state of the circuit, the conduction losses of a power semiconductor can be calculated using the following universal equation.

$$P_{cond}=\frac{1}{2\pi }{\int }_{{\theta }_1}^{{\theta }_2}i\left(\theta \right)·v\left(\theta \right)d\theta$$

(2)

$v\left(\theta \right)$ is the voltage over the component for a given current flow $i\left(\theta \right)$. For a (bipolar) IGBT, $i\left(\theta \right)$ equals the collector current $i_C\left(\theta \right)$ and $v\left(\theta \right)$ is the collector–emitter voltage $v_{CE}\left(\theta \right)$. For a (unipolar) MOSFET, $i\left(\theta \right)$ and $v\left(\theta \right)$ would be the drain current $i_D\left(\theta \right)$ and the drain–source voltage $v_{DS}\left(\theta \right)$, respectively. $\theta$ is the electrical angle, and ${\theta }_1$ and ${\theta }_2$ are the integration limits or conduction intervals.

Conventionally, an IGBT’s output characteristic is approximated using an on-state slope resistance $r_{CE}$ and the collector–emitter threshold voltage $V_{CE0}$ (see Figure 7). For MOSFETs, the drain–source turn-on resistance $R_{DS\left(on\right)}$ and no knee voltage have to be considered. For a more consistent description, $r_0$ and $V_0$ will be used in the following, resulting in a linearized output characteristic: $v\left(\theta \right)=V_0+r_0·i\left(\theta \right)$.

The (linearized) output characteristic in combination with the modulation function $M\left(\theta \right)$, a term that takes into account the switching states, represents a well-known approach to the calculation of the on-state power loss [22,45,46].

$$\begin{array}{cc}\hfill P_{cond}& =\frac{1}{2\pi }{\int }_{{\theta }_1}^{{\theta }_2}i\left(\theta \right)·(V_0+r_{0}i\left(\theta \right))·M\left(\theta \right)d\theta \hfill \\ \hfill & =\frac{1}{2\pi }{\int }_{{\theta }_1}^{{\theta }_2}(V_{0}i\left(\theta \right)+r_{0}i{\left(\theta \right)}^2)·M\left(\theta \right)d\theta \hfill \\ \hfill & =V_0{I}_{avg}+r_0{I}_{rms}^2\hfill \end{array}$$

(3)

$M\left(\theta \right)$ is a continuous function in the range of 0 to 1, which replaces the discrete-time switching function $\tau \left(\theta \right)$ in the shift to infinitesimally small switching periods. The modulation function is dependent on the power factor $cos\left(\phi \right)$ and the modulation index or modulation factor m. The power factor accounts for the phase shift $\phi$ between the fundamental components of the inverter output voltage and phase current. For an energy flow from the DC to the AC side, i.e., for inverter operation, $cos\left(\phi \right)>0$ applies. The modulation index is referenced to the virtual neutral point of the load (phase-neutral) and the (virtual) midpoint of the DC link voltage [8]. m is defined as the ratio of the fundamental amplitude of the phase-neutral AC voltage to half the DC link voltage.

$$m=\frac{{\widehat{V}}_{phase}}{\frac{V_{DC}}{2}}$$

(4)

The modulation function $M\left(\theta \right)$ and the integration limits ${\theta }_1$ and ${\theta }_2$ vary for different topologies and modulation schemes. The terms to be applied in the corresponding case are shown in

Table 2. Modulation functions and conduction loss intervals for different topologies and modulation schemes (SPWM).

Switch		B6		TNPC		NPC (ANPC MS0)
T1T4	Conduction interval	$(\phi ,\pi )$	$(\pi ,\pi +\phi )$	$(\phi ,\pi )$		$(\phi ,\pi )$
	Modulation function	$\frac{1+m·sin\left(\theta \right)}{2}$	$\frac{1+m·sin\left(\theta \right)}{2}$	$m·sin\left(\theta \right)$		$m·sin\left(\theta \right)$
D1D4	Conduction interval	$(\phi ,\pi )$	$(\pi ,\pi +\phi )$	$(0,\phi ){}^{*1}$		$(0,\phi ){}^{*1}$
	Modulation function	$\frac{1-m·sin\left(\theta \right)}{2}$	$\frac{1-m·sin\left(\theta \right)}{2}$	$m·sin\left(\theta \right){}^{*1}$		$m·sin\left(\theta \right){}^{*1}$
T2T3	Conduction interval			$(\phi ,\pi )$	$(\pi ,\pi +\phi )$	$(\phi ,\pi )$	$(\pi ,\pi +\phi )$
	Modulation function			$1-m·sin\left(\theta \right)$	$1+m·sin\left(\theta \right)$	1	$1+m·sin\left(\theta \right)$
D2D3	Conduction interval			$(\phi ,\pi )$	$(\pi ,\pi +\phi )$	$(0,\phi ){}^{*1}$
	Modulation function			$1-m·sin\left(\theta \right)$	$1+m·sin\left(\theta \right)$	$m·sin\left(\theta \right){}^{*1}$
T5T6	Conduction interval
	Modulation function
D5D6	Conduction interval					$(\phi ,\pi )$	$(\pi ,\pi +\phi )$
	Modulation function					$1-m·sin\left(\theta \right)$	$1+m·sin\left(\theta \right)$

For the entries marked with ${}^{*1}$, negative current has to be considered in the integration.

and

Table 3. Modulation functions and conduction loss intervals for the ANPC topology in its different modulation schemes (SPWM).

Switch		ANPC MS1		ANPC MS2		ANPC MS3
T1T4	Conduction interval	$(\phi ,\pi )$		$(\phi ,\pi )$		$(\phi ,\pi )$
	Modulation function	$m·sin\left(\theta \right)$		$m·sin\left(\theta \right)$		$m·sin\left(\theta \right)$
D1D4	Conduction interval	$(0,\phi ){}^{*1}$		$(0,\phi ){}^{*1}$		$(0,\phi ){}^{*1}$
	Modulation function	$m·sin\left(\theta \right){}^{*1}$		$m·sin\left(\theta \right){}^{*1}$		$m·sin\left(\theta \right){}^{*1}$
T2T3	Conduction interval	$(\phi ,\pi )$		$(\phi ,\pi )$	$(\pi ,\pi +\phi )$	$(\phi ,\pi ){}^{*2}$	$(\pi ,\pi +\phi ){}^{*2}$
	Modulation function	1		$m·sin\left(\theta \right)$	$1+m·sin\left(\theta \right)$	$1+m·sin\left(\theta \right){}^{*2}$	$1+m·sin\left(\theta \right){}^{*2}$
D2D3	Conduction interval	$(0,\phi ){}^{*1}$		$(0,\phi ){}^{*1}$	$(\pi +\phi ,2\pi ){}^{*1}$	$(0,\phi ){}^{*1}{}^{*2}$	$(\pi +\phi ,2\pi ){}^{*1}{}^{*2}$
	Modulation function	$1{}^{*1}$		$m·sin\left(\theta \right){}^{*1}$	$1+m·sin\left(\theta \right){}^{*1}$	$1+m·sin\left(\theta \right){}^{*1}{}^{*2}$	$1+m·sin\left(\theta \right){}^{*1}{}^{*2}$
T5T6	Conduction interval	$(0,\phi ){}^{*1}$		$(\pi +\phi ,2\pi ){}^{*1}$		$(0,\phi ){}^{*1}{}^{*2}$	$(\pi +\phi ,2\pi ){}^{*1}{}^{*2}$
	Modulation function	$1-m·sin\left(\theta \right){}^{*1}$		$1+m·sin\left(\theta \right){}^{*1}$		$1-m·sin\left(\theta \right){}^{*1}{}^{*2}$	$1+m·sin\left(\theta \right){}^{*1}{}^{*2}$
D5D6	Conduction interval	$(\phi ,\pi )$		$(\pi ,\pi +\phi )$		$(\phi ,\pi ){}^{*2}$	$(\pi ,\pi +\phi ){}^{*2}$
	Modulation function	$1-m·sin\left(\theta \right)$		$1+m·sin\left(\theta \right)$		$1-m·sin\left(\theta \right){}^{*2}$	$1+m·sin\left(\theta \right){}^{*2}$

For the entries marked with ${}^{*1}$, negative current has to be considered in the integration. For the entries marked with ${}^{*2}$, only half the current has to be considered in the integration due to ‘full-path clamping’.

[9,21,22]. However, when applying the modulation functions given in this table, it should be considered that different combinations of modulating functions and conduction intervals can lead to the correct loss equation and subsequent integration. As an example of this, position D1 in the NPC topology can be named. Here, the integration interval $(\pi ,\pi +\phi )$ in combination with the modulating function $-m·sin\left(\theta \right)$ would lead to exactly the same result if the opposite sign of current is considered in the following integration.

Moreover, it is important that in one given loss formula, due to the loss symmetry of the upper and lower half of each phase leg, always two devices are described.

To illustrate the procedure, first, the determination of the analytical conduction loss formula for the switch position T1 (and T4) of a standard two-level VSI will be described. This is followed by a detailed review of the derivation of the loss formulas of T1 and D1 in ANPC modulation scheme 1. Current waveforms and corresponding modulation functions for the other discussed ANPC modulation schemes are given in Figure 8 [21,24,25].

For the switches T1 and T4 of a standard two-level VSI, the modulation function $(1+m·sin\left(\theta \right))/2$ will be used. Substituting this modulation function (see Table 3), as well as the phase current $i\left(\theta \right)=\widehat{I}sin\left(\theta \right)$ (sinusoidal phase current assumed; see previously listed simplifications), into (3) yields

$$\begin{array}{cc}\hfill P_{cond,T_1}& =\frac{1}{2\pi }{\int }_{\phi }^{\pi +\phi }(V_0\widehat{I}sin(\theta -\phi )\hfill \\ \hfill & +r_0{(\widehat{I}sin(\theta -\phi ))}^2)·\frac{1+m·sin(\theta )}{2}d\theta \hfill \\ \hfill & =\frac{1}{2\pi }{\int }_0^{\pi }(V_0\widehat{I}sin(\theta )\hfill \\ \hfill & +r_0{(\widehat{I}sin(\theta ))}^2)·\frac{1+m·sin(\theta +\phi )}{2}d\theta \hfill \\ \hfill \end{array}$$

(5)

Solving this integral results in the analytical formula for the calculation of the conduction losses (cf. Appendix A

Table A1. Conduction loss formula. Valid only for SPWM.

	Conduction Loss Formula
B6
T1T4	$P_{cond,T1}=\frac{1}{24\pi }\left(V_0\widehat{I}3\left(4+m\pi cos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(3\pi +8mcos\left(\phi \right)\right)\right)$
D1D4	$P_{cond,D1}=\frac{1}{24\pi }\left(V_0\widehat{I}3\left(4-m\pi cos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(3\pi -8mcos\left(\phi \right)\right)\right)$
TNPC
T1T4	$P_{cond,T1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(sin\left(\phi \right)+(\pi -\phi )cos\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\right)$
D1D4	$P_{cond,D1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(sin\left(\phi \right)-\phi cos\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1-cos\left(\phi \right))}^2\right)\right)$
T2T3	$P_{cond,T2}=\frac{1}{12\pi }\left(V_0\widehat{I}3\left(4-m(2sin\left(\phi \right)-(2\phi -\pi )cos\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -4m{(1+cos\left(\phi \right))}^2\right)\right)$
D2D3	$P_{cond,D2}=\frac{1}{12\pi }\left(V_0\widehat{I}3\left(4-m(2sin\left(\phi \right)-(2\phi -\pi )cos\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -4m{(1+cos\left(\phi \right))}^2\right)\right)$
NPC
T1T4	$P_{cond,T1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left((\pi -\phi )cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\right)$
D1D4	$P_{cond,D1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1-cos\left(\phi \right))}^2\right)\right)$
T2T3	$P_{cond,T2}=\frac{1}{12\pi }\left(V_0\widehat{I}3\left(4+m(\phi cos\left(\phi \right)-sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -2m{(1-cos\left(\phi \right))}^2\right)\right)$
D2D3	$P_{cond,D2}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1-cos\left(\phi \right))}^2\right)\right)$
D5D6	$P_{cond,D5}=\frac{1}{12\pi }\left(V_0\widehat{I}3\left(4+m\left(\right(2\phi -\pi )cos\left(\phi \right)-2sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -4m{(1+cos\left(\phi \right))}^2\right)\right)$
ANPC modulation scheme 1
T1T4	$P_{cond,T1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left((\pi -\phi )cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\right)$
D1D4	$P_{cond,D1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left((1-cos\left(\phi \right))\right)\right)$
T2T3	$P_{cond,T2}=\frac{1}{8\pi }\left(V_0\widehat{I}4\left(1+cos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(2(\pi -\phi )+sin\left(2\phi \right)\right)\right)$
D2D3	$P_{cond,D2}=\frac{1}{8\pi }\left(V_0\widehat{I}4\left(1-cos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(2\phi -sin\left(2\phi \right)\right)\right)$
T5T6	$P_{cond,T5}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1-cos\left(\phi \right))+m(\phi cos\left(\phi \right)-sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(6\phi -3sin\left(2\phi \right)-4m{(1-cos\left(\phi \right))}^2\right)\right)$
D5D6	$P_{cond,D5}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1+cos\left(\phi \right))+m\left(\right(\phi -\pi )cos\left(\phi \right)-sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(6(\pi -\phi )+3sin\left(2\phi \right)-4m{(1+cos\left(\phi \right))}^2\right)\right)$
ANPC modulation scheme 2
T1T4	$P_{cond,T1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left((\pi -\phi )cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\right)$
D1D4	$P_{cond,D1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1-cos\left(\phi \right))}^2\right)\right)$
T2T3	$P_{cond,T2}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1-cos\left(\phi \right))+\pi mcos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(3(2\phi -sin\left(2\phi \right))+16mcos\left(\phi \right)\right)\right)$
D2D3	$P_{cond,D2}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1+cos\left(\phi \right))-\pi mcos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(6(\pi -\phi )+3sin\left(2\phi \right)-16mcos\left(\phi \right)\right)\right)$
T5T6	$P_{cond,T5}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1+cos\left(\phi \right))+m\left(\right(\phi -\pi )cos\left(\phi \right)-sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(6(\pi -\phi )+3sin\left(2\phi \right)-4m{(1+cos\left(\phi \right))}^2\right)\right)$
D5D6	$P_{cond,D5}=\frac{1}{24\pi }\left(V_0\widehat{I}6\left(2(1-cos\left(\phi \right))+m(\phi cos\left(\phi \right)-sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(6\phi -3sin\left(2\phi \right)-4m{(1-cos\left(\phi \right))}^2\right)\right)$
ANPC modulation scheme 3
T1T4	$P_{cond,T1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left((\pi -\phi )cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\right)$
D1D4	$P_{cond,D1}=\frac{m}{12\pi }\left(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)+r_0{\widehat{I}}^{2}2\left({(1-cos\left(\phi \right))}^2\right)\right)$
T2T3	$P_{cond,T2}=\frac{1}{48\pi }\left(V_0\widehat{I}6\left(4+\pi mcos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(3\pi +8mcos\left(\phi \right)\right)\right)$
D2D3	$P_{cond,D2}=\frac{1}{48\pi }\left(V_0\widehat{I}6\left(4-\pi mcos\left(\phi \right)\right)+r_0{\widehat{I}}^2\left(3\pi -8mcos\left(\phi \right)\right)\right)$
T5T6	$P_{cond,T5}=\frac{1}{48\pi }\left(V_0\widehat{I}6\left(4+m\left(\right(2\phi -\pi )cos\left(\phi \right)-2sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -4m{(1+cos\left(\phi \right))}^2\right)\right)$
D5D6	$P_{cond,D5}=\frac{1}{48\pi }\left(V_0\widehat{I}6\left(4+m\left(\right(2\phi -\pi )cos\left(\phi \right)-2sin\left(\phi \right))\right)+r_0{\widehat{I}}^2\left(3\pi -4m{(1+cos\left(\phi \right))}^2\right)\right)$

):

$$\begin{array}{cc}\hfill P_{cond,T_1}& =V_0·\widehat{I}(\frac{1}{2\pi }+\frac{mcos\phi }{8})+r_0·{\widehat{I}}^2(\frac{1}{8}+\frac{mcos\phi }{3\pi })\hfill \\ \hfill & =\frac{1}{24\pi }\left(V_0\widehat{I}·3\left(4+m\pi cos(\phi )\right)\right)\hfill \\ \hfill & \left(+r_0{\widehat{I}}^2·\left(3\pi +8mcos\left(\phi \right)\right)\right)\hfill \end{array}$$

(6)

Figure 9 shows the phase current, modulating signal, phase angle, as well as conduction and switching loss intervals for D1 and T1 of a three-level ANPC topology in modulation scheme 1. One can see that T1 conducts a positive (forward) current not over the full AC line cycle of length $2\pi$, but only over half of this period. As previously, substituting the correct modulation function (Table 3), as well as a sinusoidal phase current into (3), yields

$$\begin{array}{cc}\hfill P_{cond,T_1}& =\frac{1}{2\pi }{\int }_{{\theta }_1}^{{\theta }_2}(V_{0}i\left(\theta \right)+r_{0}i{\left(\theta \right)}^2)·M\left(\theta \right)d\theta \hfill \\ \hfill & =\frac{1}{2\pi }{\int }_{\phi }^{\pi }(V_0\widehat{I}sin(\theta -\phi )\hfill \\ \hfill & +r_0{(\widehat{I}sin(\theta -\phi ))}^2)·m·sin\left(\theta \right)d\theta \hfill \\ \hfill & =\frac{1}{2\pi }{\int }_0^{\pi -\phi }(V_0\widehat{I}sin\left(\theta \right)\hfill \\ \hfill & +r_0{(\widehat{I}sin(\theta ))}^2)·m·sin(\theta +\phi )d\theta \hfill \\ \hfill & =\frac{m}{12\pi }\left(V_0\widehat{I}3\left((\pi -\phi )cos\left(\phi \right)+sin\left(\phi \right)\right)\right)\hfill \\ \hfill & +r_0{\widehat{I}}^{2}2\left({(1+cos\left(\phi \right))}^2\right)\hfill \end{array}$$

(7)

Note that the equation greatly simplifies when unipolar devices are considered since the term associated with $V_0$ does not have to be considered.

For the diode D1 in ANPC modulation scheme 1, the modulation function and integration limits can also be derived from Table 3 or Figure 9 as follows:

$$\begin{array}{cc}\hfill P_{cond,D_1}=& \frac{1}{2\pi }{\int }_0^{\phi }(V_0(-\widehat{I})sin(\theta -\phi )\hfill \\ \hfill & +r_0{((-\widehat{I})sin(\theta -\phi ))}^2)·m·sin\left(\theta \right)d\theta \hfill \\ \hfill & =\frac{m}{12\pi }(V_0\widehat{I}3\left(-\phi cos\left(\phi \right)+sin\left(\phi \right)\right)\hfill \\ \hfill & +r_0{\widehat{I}}^{2}2(1-cos\left(\phi \right)))\hfill \end{array}$$

(8)

Note the negative sign of the current in (8), due to the prevailing negative phase current during the conduction interval of the diode.

It can be observed that this approach quickly results in complex equations, which can take many different forms and can therefore only be compared between different literature sources with great effort [20,21,22,23,24]. Furthermore, for every entry in Table 2 and Table 3, one such equation is required. Although switches as well as diodes in the upper and lower half of a phase leg are stressed equally due to the prevailing symmetry, still a great number of equations is necessary to describe every topology and modulation scheme. For example, the previously discussed ANPC modulation scheme 1 needs a total of six such equations. For the other ANPC modulation schemes, even more integrations are required, since, for one device, more than one modulation function and integration interval apply. The full set of loss equations can be found in Appendix A (Table A1). Note that these equations are only valid for SPWM. Moreover, note that the equations simplify when unipolar devices such as SiC MOSFETs are used, since only the term associated with $I_{rms}^2$ has to be considered in the integration.

As mentioned earlier, this approach can be extended to other modulation strategies, such as SVPWM or THIPWM, by inserting a zero-sequence waveform into the modulation signal (Figure 4). See an example in [19], where this approach for two-level VSI is extended to SVPWM by using a modified modulation factor, which is a composition of sine functions expressed as a Fourier series. In this case, the term $m·sin\left(\theta \right)$ in the modulation function $(1+m·sin\left(\theta \right))/2$ will be replaced by the following expression:

$$\begin{array}{cc}\hfill m·sin\left(\theta \right)& +\frac{3\sqrt{3}}{8\pi }\sum _{k=0}^{\infty }(\frac{sin(3·(4k+1)·\theta )}{18k^2+9k+1}\hfill \\ \hfill & -{\displaystyle \frac{sin\left(3\right(4k+3)·\theta )}{18k^2+27k+10}})\hfill \end{array}$$

(9)

This modulation function can then be used in the integration, cf. (5), which results in [19]

$$\begin{array}{cc}\hfill P_{cond,T_1}& =V_0·\widehat{I}(\frac{1}{2\pi }+\frac{mcos\phi }{8})\hfill \\ \hfill & +r_0·{\widehat{I}}^2(\frac{1}{8}+m·(\frac{cos\phi }{3\pi }+\frac{F_{SVPWM}}{2\pi }))\hfill \end{array}$$

(10)

While, for the previously discussed SPWM, $F_{SVPWM}$ would be zero, for SVPWM, the following term has to be used:

$$\begin{array}{cc}\hfill & F_{SVPWM}=\frac{6\sqrt{3}}{\pi }\sum _{\nu }^{\infty }\left(\frac{cos(k·\phi )}{k^5-5k^5+4k}-\frac{cos(l·\phi )}{l^5-5l^3+4l}\right)\hfill \\ \hfill & \mathrm{for}l=3(4\nu +1);k=3(4\nu +3);\nu =0,1,2,\dots \hfill \end{array}$$

(11)

It becomes apparent that extending the loss equations to other modulation strategies further adds to the complexity and is therefore usually avoided in the literature [24]. This holds especially true for topologies and modulation schemes requiring a greater number of integrations. This is why the extension to SVPWM for, e.g., the ANPC topology will not be discussed in this work. Implementing these equations in a simulation script is prone to human error and should therefore be avoided. Instead, this paper proposes to compute the definite integrals using numerical integration methods already incorporated in state-of the art programming languages such as Python or MATLAB. For more details, see Appendix A and Appendix B.

4.2. Switching Losses

While the conduction losses are mainly determined by the flowing current, the switching losses depend proportionally on the switching frequency $f_{sw}$. Therefore, the switching losses are obtained by multiplying $f_{sw}$ with the switching energy loss $E_{sw}$. The same applies to the diodes, where, instead of the turn-on and turn-off energy loss ($E_{on}$ and $E_{off}$), the reverse recovery energy $E_{rr}$ is considered [8].

$$\begin{array}{cc}\hfill P_{sw,T}& =f_{sw}·E_{sw}=f_{sw}·(E_{on}+E_{off})\hfill \\ \hfill P_{sw,D}& =f_{sw}·E_{rr}\hfill \end{array}$$

(12)

Manufacturers’ datasheets specify the switching energy losses in dependency on a certain (nominal) current and voltage, as well as a temperature [8]. Oftentimes, a particular $di/dt$ is also defined. Adaptation to the real application can, in the simplest case, be done by linear interpolation of the given values, as shown in (13) [8,22,45,46].

$$\begin{array}{cc}\hfill E_{on}(i,v)& =E_{on,nom}(I_{nom},V_{nom})·{(\frac{i}{I_{nom}})}^{k_{i,T}}·{(\frac{v}{V_{nom}})}^{k_{v,T}}\hfill \\ \hfill E_{off}(i,v)& =E_{off,nom}(I_{nom},V_{nom})·{(\frac{i}{I_{nom}})}^{k_{i,T}}·{(\frac{v}{V_{nom}})}^{k_{v,T}}\hfill \\ \hfill E_{rr}(i,v)& =E_{rr,nom}(I_{nom},V_{nom})·{(\frac{i}{I_{nom}})}^{k_{i,D}}·{(\frac{v}{V_{nom}})}^{k_{v,D}}\hfill \end{array}$$

(13)

However, it becomes evident from the switching energy curves in the manufacturers’ datasheets that these energies are not linearly dependent on the current and voltage. Therefore, various possibilities exist to better approximate the energy loss value for a given device. One approach is the introduction of exponents for the linear scaling terms (see (13)). For Si IGBTs, ref. [8] suggests the use of $k_{v,T}\approx 1.3\dots 1.4$ for the voltage scaling term while keeping the linear interpolation over the current. For Si diodes, no linear dependency for the loss energy over the current can be assumed. $k_{v,D}\approx 0.6$ and $k_{i,D}\approx 0.6$ are stated for the diodes. Other sources such as [46] suggest the use of a term $(0.45·\frac{i}{I_{nom}}+0.55)$ instead of the linear current scaling, while linearly interpolating over the voltage. However, caution is advised when using these extensions since they may have to be taken into account in the subsequent transition to the average current value and complicate the integral to be solved. In this publication, these exponents are set equal to 1 to preserve the generality of the results. A temperature coefficient [8] can be used to account for the switching energy loss temperature dependency.

In addition to the (improved) linear interpolations, the second basic principle for the present analytical switching loss calculation is the assumption that the switching losses during a half-wave of the sinusoidal current are equal to the switching losses for an equivalent direct current, which is the average value of the respective current [8,46].

To calculate the switching losses, the switching energies are integrated over a half-wave and multiplied with the switching frequency. In the following, two examples of this integration will be given—one for the conventional two-level VSI, and one for T1 (T4) and D1 (D4) in the previously discussed ANPC topology in modulation scheme 1 (see Figure 9).

For the two-level topology, the full DC link voltage is switched and is therefore used as v. The (phase-shifted) current is assumed to be sinusoidal: $i=\widehat{I}·sin(\theta -\phi )$. The switching angles or integration limits are $(\phi ,\pi +\phi )$

$$\begin{array}{cc}\hfill P_{sw,T_1}& =f_{sw}·\frac{1}{2\pi }{\int }_{{\theta }_1}^{{\theta }_2}{E}_{sw}·\frac{i}{I_{nom}}·\frac{v}{V_{nom}}d\theta \hfill \\ \hfill & =f_{sw}·\frac{1}{2\pi }{\int }_{\phi }^{\pi +\phi }{E}_{sw}·\frac{\widehat{I}·sin(\theta -\phi )}{I_{nom}}·\frac{V_{DC}}{V_{nom}}d\theta \hfill \\ \hfill & =f_{sw}·\frac{1}{2\pi }{\int }_0^{\pi }{E}_{sw}·\frac{\widehat{I}·sin\left(\theta \right)}{I_{nom}}·\frac{V_{DC}}{V_{nom}}d\theta \hfill \\ \hfill & =f_{sw}·\frac{1}{\pi }·E_{sw}·\frac{\widehat{I}}{I_{nom}}·\frac{V_{DC}}{V_{nom}}\hfill \end{array}$$

(14)

For three-level topologies, half the DC voltage has to be used as v. Furthermore, different switching loss intervals have to be considered. For an ANPC topology, the integration limits for T1 would be $(\phi ,\pi )$ (see Figure 9 and

Table 4. Switching loss intervals and resulting factors for different topologies and modulation schemes (MS).

Switch		B6	TNPC	NPC	ANPC MS1	ANPC MS2	ANPC MS3
T1T4	Switching Loss Interval	$(\phi ,\pi +\phi )$	$(\phi ,\pi )$	$(\phi ,\pi )$	$(\phi ,\pi )$	-	$(\phi ,\pi )$
	Resulting Factor	$\frac{1}{\pi }$	$\frac{1+cos\left(\theta \right)}{2\pi }$	$\frac{1+cos\left(\theta \right)}{2\pi }$	$\frac{1+cos\left(\theta \right)}{2\pi }$	0	$\frac{1+cos\left(\theta \right)}{2\pi }$
D1D4	Switching Loss Interval	$(\phi ,\pi +\phi )$	$(0,\phi ){}^{*1}$	$(0,\phi ){}^{*1}$	$(0,\phi ){}^{*1}$	-	$(0,\phi ){}^{*1}$
	Resulting Factor	$\frac{1}{\pi }$	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}$	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}$	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}$	0	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}$
T2T3	Switching Loss Interval		$(\pi ,\pi +\phi )$	$(\pi ,\pi +\phi )$	-	$(\phi ,\pi +\phi )$	$(\pi ,\pi +\phi ){}^{*2}$
	Resulting Factor		$\frac{1-cos\left(\theta \right)}{2\pi }$	$\frac{1-cos\left(\theta \right)}{2\pi }$	0	$\frac{1}{\pi }$	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*2}$
D2D3	Switching Loss Interval		$(\phi ,\pi )$	-	-	$(\pi +\phi ,2\pi +\phi ){}^{*1}$	$(\pi +\phi ,2\pi ){}^{*1}{}^{*2}$
	Resulting Factor		$\frac{1+cos\left(\theta \right)}{2\pi }$	0	0	$\frac{1}{\pi }{}^{*1}$	$\frac{1+cos\left(\theta \right)}{2\pi }{}^{*1}{}^{*2}$
T5T6	Switching Loss Interval				$(0,\phi ){}^{*1}$	-	$(0,\phi ){}^{*1}{}^{*2}$
	Resulting Factor				$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}$	0	$\frac{1-cos\left(\theta \right)}{2\pi }{}^{*1}{}^{*2}$
D5D6	Switching Loss Interval			$(\phi ,\pi )$	$(\phi ,\pi )$	-	$(\phi ,\pi ){}^{*2}$
	Resulting Factor			$\frac{1+cos\left(\theta \right)}{2\pi }$	$\frac{1+cos\left(\theta \right)}{2\pi }$	0	$\frac{1+cos\left(\theta \right)}{2\pi }{}^{*2}$

Linear scaling of the switching energies applied. For the entries marked with ${}^{*1}$, negative current has to be considered in the integration. For the entries marked with ${}^{*2}$, only half the current has to be considered in the integration due to ‘full-path clamping’.

), resulting in the following expression for the switching losses:

$$\begin{array}{cc}\hfill P_{sw,T_1}& =f_{sw}·\frac{1}{2\pi }{\int }_{\phi }^{\pi }{E}_{sw}·\frac{\widehat{I}·sin(\theta -\phi )}{I_{nom}}·\frac{\frac{V_{DC}}{2}}{V_{nom}}d\theta \hfill \\ \hfill & =f_{sw}·\frac{1+cos\left(\phi \right)}{2\pi }·E_{sw}·\frac{\widehat{I}}{I_{nom}}·\frac{\frac{V_{DC}}{2}}{V_{nom}}\hfill \end{array}$$

(15)

However, it should be noted that for some elements, the negative sign of the current has to be considered in this integration. An example of this would be D1 in the previous topology with the switching loss interval $(0,\phi )$:

$$\begin{array}{cc}\hfill P_{sw,D_1}& =f_{sw}·\frac{1}{2\pi }{\int }_0^{\phi }{E}_{rr}·\frac{-\widehat{I}·sin(\theta -\phi )}{I_{nom}}·\frac{\frac{V_{DC}}{2}}{V_{nom}}d\theta \hfill \\ \hfill & =f_{sw}·\frac{1-cos\left(\phi \right)}{2\pi }·E_{rr}·\frac{\widehat{I}}{I_{nom}}·\frac{\frac{V_{DC}}{2}}{V_{nom}}\hfill \end{array}$$

(16)

An overview of the switching loss intervals, as well as the resulting factors for the switching loss calculation, is given in Table 4. Note that these, as for the modulation functions in Table 2 and Table 3, are valid only for SPWM. The factors in Table 4 only apply to pure linear scaling of the switching energies.

Here, too, an approach that avoids manual integration, as presented in Section 4.1, could be used. However, since less complex equations result from the integration, this might not be as beneficial. Further, note that the switching losses of switches switching with output frequency are not considered here and thus are set to zero. This simplification is possible because the output frequency is much smaller than the switching frequency. This approach only applies to continuous PWM [19]. To assess losses in DPWM techniques, a so-called switching loss factor (SLF) could be used [47].

In the following section, the design, packaging, and thermal aspects for the realization of such (multi-level) inverters will be discussed. Using the approach described in this section, power loss analysis is performed for different topologies, device configurations, and modulation schemes.

5. Application Aspects and Results

5.1. Design, Packaging, and Thermal Aspects

For the realization of inverters in general and multi-level inverters in particular, several packaging forms of power semiconductors exist. They range from single switches, such as the typical TO-247 or a surface mount package, to packages with all transistors and diodes fully integrated into one module. For a standard two-level VSI, this would be a full-bridge or so-called ‘six pack’ package. Often, a single-phase leg is integrated into one package. Half-bridge modules are common, also due to the widespread use of the B6 topology. Moreover, modules with integrated peripheries exist, which could include (gate) driving, protective units, or (current) measurement circuits (so-called intelligent power modules, IPM). However, it should be noted that the universality of these power modules is reduced with the increasing integration level [8].

In the industrial drive and automotive EV sector, the use of power modules with multiple power semiconductors in one package is common. These power module integration capabilities offer more simplicity in design, higher reliability, and, as they provide better heat spreading properties, higher output power and power density in direct comparison to discrete switches [48]. However, when the application of WBG devices or a hybrid device configuration is desired, the availability of such modules is limited, especially for configurations with more than two levels. Other solutions, such as discrete switches, have to be applied. In order to further decrease EMC/EMI issues, the system footprint, and the integration effort—and to increase the overall power density—multi-level power modules will be necessary in the future. Besides the parasitic elements, thermal aspects are also challenging. The power loss model represents the interface between electrical and thermal considerations. The equations can be used to evaluate the junction temperatures of discrete components. Especially for power modules employing a larger number of semiconductor chips on a common base plate, the thermal behavior and heat spread within this module must be examined in more detail. In terms of temperature distribution, for example, a high-loss Si device could limit the junction temperature of a SiC device in one power module. The study [49] gives a good impression of the challenges faced when designing such power modules with particular respect to the mandatory low-inductive design. An exemplary implementation of an ANPC inverter with a hybrid switch configuration in an ‘Easy3B’ package is given in [26]. Another such three-level ANPC module available would be the Infineon F3L11MR12W2M1_B74 EasyPACK™ module [50]. Here, too, a hybrid configuration using different semiconductor materials is used. This power module utilizes SiC MOSFETs as inner switches while keeping Si IGBTs on the outer and midpoint switch positions [22]. However, it should be noted that due to the diverse modulation strategies, especially for the ANPC topology, a variety of optimized solutions are conceivable in terms of the types of power semiconductors and module layouts. For example, ref. [18] uses GaN HEMTs for positions T2 and T3 since they can achieve high switching frequencies due to their low output capacitances. The challenge of the limited current carrying capability of state-of-the-art GaN switches is overcome by interleaving respective switches. Besides the use of discrete power devices or dedicated three-level modules, the construction of such multi-level topologies from two-level modules is possible. In practice, however, this approach leads to very long conduction paths and commutations across module boundaries. Especially for the opposite-side clamping used in ANPC modulation scheme 2 (see Section 3.2), these long commutation paths have a negative effect. Stray inductance caused by the long commutation paths leads to voltage overshoots, so part of the advantage over two-level designs can be lost [35]. Ref. [35] provides a good overview of the advantages and drawbacks and discusses how to set up three-level configurations from two-level half-bridge modules.

In addition to the setup of multi-level inverters from different power semiconductor packaging technologies, the design of the inverter itself and the thermal management—for instance, under the consideration of cryogenic cooling [51]—are crucial. For multi-level inverters with their increased number of switch positions and offered degrees of freedom in terms of current paths, the optimization of the commutation loop is one of the primary challenges. Sources of inductance here are the commutation loop stray inductance, the semiconductor device self-inductance, and the DC link capacitor self-inductance, which all should be optimized to improve efficiency and mitigate voltage overshoots. Besides their self-inductance, the DC link capacitors also play a crucial role in inverters and have, therefore, to be optimized [52]—for instance, to achieve high power density requirements. The design and optimization of the cooling system for a multi-level inverter has to be carried out. For multi-level topologies, consideration of the type of cooling and the number of switches per heat sink is relevant. The use of WBG semiconductors, which are capable of higher-temperature operation, in combination with the mentioned higher-level topologies, incorporating a larger number of switches and therefore improved loss distribution, place forced [15] and even natural convection [53] air cooling into the focus for aircraft power electronics. Additive manufacturing technologies and optimization algorithms have recently been used to fabricate more complex structured heat sinks [54]. This allows cooling performance and weight to be improved simultaneously. Furthermore, innovative materials and the combination of different materials within a heat sink structure are also feasible to achieve lighter and more efficient heat sinks [55]. Applying such sophisticated heat sink structures is quite realistic, as seen in the example of the Siemens SD104 aircraft inverter, which has already been operated onboard the Magnus eFusion electric test plane. It utilizes silicon-carbide semiconductors and incorporates a micro-channel cooling plate [56].

5.2. Exemplary Power Loss Analysis

In the literature, often, fictive module configurations are assumed. These are based on the data of semiconductors, which are used in, e.g., half-bridge modules. This allows for an analysis of a large number of configurations in the desired power range despite the limited number of three-level modules currently available on the market. However, this approach lacks practicality in that it will not be possible to actually use and test such configurations easily in practice. For this reason, a different approach is taken in this work. To show the effects of different (hybrid) switch configurations, the overall system is scaled down so that discrete devices in the TO-247 package can be utilized for every switching position. In this scaled down system, no paralleling of devices has to be considered.

In the following, a power loss analysis will be performed and discussed for different topologies, modulation schemes, and device configurations using the previously described approach. The calculations aim to evaluate which semiconductors will work best in which topology and which PWM scheme would be best suited.

For this study, a three-phase system with a DC link voltage of $800$V is assumed. The output power is varied around a nominal value of $40$kW. With an assumed $V_{rms,line-line}$ of $490$V ($m=1$), an approximate nominal phase current of $50$A is present. The power factor is assumed to be $cos\left(\phi \right)=0.95$, and the fundamental frequency is set at $250$Hz. This relatively high output frequency is due to the intended application as an aircraft propeller inverter. Propeller applications tend to be high-torque rather than high-speed, resulting in an increased number of pole pairs. For the switching frequency, a range between 5 kHz and 70 kHz is swept, as shown in the following figures. For the frequency sweep, a fixed inverter output power of $50$kW is set. Thermal considerations must be taken into account. For this section’s power loss calculation, discrete parameters were extracted from the power semiconductor datasheets. The considered semiconductor devices and their associated parameters are shown in

Table 5. Semiconductor device parameters as extracted from manufacturers’ datasheets.

				Transitor Parameters					Diode Parameters				${\mathit{V}}_{\mathit{ref},{\mathit{E}}_{\mathbf{on},\mathbf{off},\mathbf{rr}}}$ ${\mathit{I}}_{\mathit{ref},{\mathit{E}}_{\mathbf{on},\mathbf{off},\mathbf{rr}}}$
${\mathbf{V}}_{\mathit{br}}$	Config.	Description	Device	${\mathbf{I}}_{\mathit{nom}}$	${\mathbf{V}}_{\mathbf{0}}$	${\mathbf{r}}_{\mathbf{0}}$	${\mathbf{E}}_{\mathit{on}}$	${\mathbf{E}}_{\mathit{off}}$	${\mathbf{I}}_{\mathit{nom}}$	${\mathbf{V}}_{\mathbf{0}}$	${\mathbf{r}}_{\mathbf{0}}$	${\mathbf{E}}_{\mathit{rr}}$
V				A	V	m$\Omega$	mJ	mJ	A	V	m$\Omega$	mJ	V A
650	Si	Si IGBT with copacked Si FRD	Infineon IKW75N65ET7	79	0.8	9	3.45	2.05	74	1.0	7.50	1.76	400 75
650	Hyb	Si IGBT with copacked SiC SBD	Infineon IKW75N65RH	75	1.5	7	0.45	0.40	31	0.7	27.5	0.00	400 37.5
650	SiC1	SiC MOSFET and its body diode	Wolfspeed C3M0025065K	70	0.0	33	0.12	0.05	52	5.2	25.7	0.12	400 33.5
650	SiC2	SiC MOSFET with additional SiC SBD	Wolfspeed C3M0025065K and Wolfspeed C3D16065A	70	0.0	33	0.07	0.08	39	0.8	80.0	0.00	400 33.5
1200	Si	Si IGBT with copacked Si FRD	Infineon IKZA75N120CH7	94	1.5	6	3.16	4.04	75	1.7	11.5	2.93	600 75
1200	Hyb	Si IGBT with additional SiC SBD	Infineon IKZA75N120CH7 and Infineon IDWD40G120C5	94	1.5	6	3.16	4.04	51	0.9	21.7	0.00	600 75
1200	SiC1	SiC MOSFET and its body diode	Wolfspeed C3M0021120K	74	0.0	38	1.58	0.34	90	4.1	14.0	0.74	800 50
1200	SiC2	SiC MOSFET with additional SiC SBD	Wolfspeed C3M0021120K and Wolfspeed C4D20120A	74	0.0	38	0.69	0.42	55	0.7	76.0	0.00	800 50

Transistor nominal currents are given for $T_c=100$ °C. For the IGBT configurations, diode nominal currents are given for $T_c=100$ °C. The nominal currents of the diodes in association with the SiC MOSFETS are given for $T_c=25$ °C only. Output characteristic parameters ($V_0$ and $r_0$), as well as the switching energies, are given for either $T_j=150$ °C or for $T_j=175$ °C.

. The device’s non-linear output characteristics are described by first-degree functions (c.f. Equation (3)). A more accurate representation in the form of higher-degree functions would influence the subsequent integration and the complexity of the resulting power loss equations and is therefore omitted here. For the switching energies, the datasheet specifications were scaled linearly over the current and voltage in accordance with common scientific practice (cf. (13)). The parameters required for this are also listed in Table 5. Note that these parameters are temperature-dependent. This dependency could be, depending on the relation of electrical to thermal time constant, introduced into this model by modeling the device parameters as multi-dimensional, temperature-dependent functions or the use of parameter look-up tables. However, in this work, mean-value analysis with temperature considered as a stationary parameter is performed. The plot of losses over switching frequency, as well as efficiency over output power, is limited to the thermally safe region. A maximum device junction temperature $T_j$ of 150 °C is assumed for all calculations. The limits of the curves in Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15, where present, indicate the thermal limits of the various topology device configurations at an assumed case temperature of $T_c=70$ °C. In order to fully explore all possible semiconductor device combinations in the different topologies, all device combinations are considered. For the switches subjected to the full DC link voltage, $1200$V components are employed. Otherwise, $650$V components are used. The figures showing the resulting power losses for different switching frequencies, the efficiencies over the output power, as well as power loss distributions for the different topologies and device combinations are discussed in the following.

Figure 10a shows the resulting power losses for the named operating point over the described switching frequency range for a standard two-level VSI. It can be seen that the inverter consisting of Si components only (configuration 0) performs worse than its counterparts over almost the full switching frequency range. For even lower switching frequencies, however, it is the SiC-MOSFET-based configurations (deemed as SiC1 and SiC2) that are expected to have higher losses. Furthermore, it can be seen that the SiC-based solution, which employs an additional Schottky barrier diode (SBD) (SiC2, configuration 3), has an even flatter dependence on $f_{sw}$, compared to the solution only utilizing the MOSFET’s body diode (SiC1, configuration 2). This is partly due to the SBD’s negligible reverse recovery losses. Moreover, the on and off switching energies for these two configurations vary, even though the same chip is used as the transistor (see Section 5). This is due to the fact that the switching characteristics of the transistor are influenced to a non-negligible degree by its commutation partner—in this case, the anti-parallel Schottky barrier diode. In contrast to the losses over the frequency, the Si-based solutions have a less pronounced drop in efficiency over the output power than the MOSFET configurations (see Figure 10b). Figure 10c shows the power loss distribution for different device configurations and for two switching frequencies of 20 kHz and 50 kHz, respectively.

Figure 10. Power losses for two-level VSI. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 10. Power losses for two-level VSI. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

A similar behavior is present for the TNPC topology (Figure 11a). Here, the configurations employing Si IGBTs (e.g., configurations 0 and 3) also have a steeper loss dependency on the switching frequency. The configurations with SiC-MOSFETs perform better for higher switching frequencies. Since the utilized co-packed hybrid switches are highly optimized for higher switching frequencies, even though IGBTs are used, they perform well for higher $f_{sw}$ (see configuration 13 in Figure 11a). Bipolar Si IGBTs typically offer lower conduction losses than unipolar SiC-based switches for a given current, further reducing the losses of these configurations. In configuration 12, it is mainly the switching losses of the diodes in positions 2 and 3 that lead to higher losses at higher switching frequencies, while the switching losses of the transistors in positions 1 and 4 increase only marginally. Compared to the standard two-level VSI, lower total losses prevail.

Figure 11. Power losses for three-level TNPC. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 11. Power losses for three-level TNPC. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

The NPC topologies’ loss behavior is shown in Figure 12a. The losses and loss distribution shown correspond to the ones of an ANPC topology in modulation scheme 0. All Si IGBT-based solutions perform better for lower switching frequencies, but the losses strongly rise for higher $f_{sw}$. The advantage of using SiC diodes as midpoint clamping diodes becomes evident when comparing configurations 0 and 3 or configurations 12 and 15. While, for configuration 12, the diode switching losses increase drastically for higher $f_{sw}$, this is not the case for the SiC SBDs, e.g., in configuration 15, as can be seen in Figure 12c. For the latter configuration, the middle switches become the most heated devices. For higher switching frequencies, SiC MOSFETs, preferably with an additional SBD, should be used with regard to the expected power dissipation. It should be noted, however, that their efficiency decreases more sharply at higher output powers (see Figure 12b).

Figure 12. Power losses for three-level NPC or ANPC in modulation scheme 0. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 12. Power losses for three-level NPC or ANPC in modulation scheme 0. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 13a and Figure 14a show the power losses over the switching frequency for the ANPC topology in modulation schemes 1 and 2, respectively. As expected, in both modulation schemes, the use of IGBTs for the switching positions that switch at $f_{sw}$ results in poor performance. For modulation scheme 1, where the outer switches T1, T4 and T5 and T6 switch at $f_{sw}$, this is shown for configurations 0 and 3, where either both or only one pair of these switches is Si-based. Figure 13c shows that there is a sharp increase in switching losses in T1 and T4, as well as in D5 and D6, for higher $f_{sw}$ for configuration 0 in this modulation scheme.

Figure 13. Power losses for three-level ANPC modulation scheme 1. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 13. Power losses for three-level ANPC modulation scheme 1. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

In modulation scheme 2, only T2 and T3 operate at the switching frequency. Here, for example, configurations 0 and 12 are increasingly less efficient as the switching frequency increases. Configuration 12 for modulation scheme 1 and configuration 3 for modulation scheme 2 impose even lower losses than configuration 15, which is due to the IGBTs’ excellent conduction behavior on the slow switching positions 2, 3 and 1, 4, 5, 6, respectively. As for the previously discussed topologies, the Si-based solutions have a less pronounced drop in efficiency over the output power compared to the MOSFET configurations (see Figure 13b and Figure 14b). As the complexity of the circuit, compared to the standard two-level VSI, increases, the loss distribution among the switch positions, as well as the semiconductor devices (transistors and diodes), becomes more non-uniform.

Figure 14. Power losses for three-level ANPC modulation scheme 2. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 14. Power losses for three-level ANPC modulation scheme 2. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

The loss characteristics for modulation scheme 3 are shown in Figure 15a–c. In modulation scheme 3, all switches are operated at a high switching frequency, potentially leading to higher switching losses, which can be seen in Figure 15c. As postulated earlier, more uniform switch utilization is achieved in comparison to modulation schemes 1 and 2 (cf. Figure 15c). In this modulation scheme, no solution with Si IGBTs performs well because the higher switching energies of this device have a negative effect in all switch positions. The main difference between configuration 15 and configuration 10 is the increased diode conduction losses in the latter configuration, where the MOSFET’s body diode is used for reverse conduction, in contrast to configuration 15’s additional SiC SBD.

Figure 15. Power losses for three-level ANPC in modulation scheme 3. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

Figure 15. Power losses for three-level ANPC in modulation scheme 3. (a) Inverter total power losses ($P_{out}=40$kW) and (b) inverter total efficiency ($f_{sw}=20$ kHz), where a number is assigned to each (hybrid) switch configuration (e.g., ‘Config.0’) and the type of switch used for each switching position is stated subsequently (e.g., Si for switch position(s) 1 and 4: ‘14:Si’). For the naming of the configurations, see Table 5. (c) Power loss distribution in one phase leg for different configurations and for frequencies of 20 kHz (left) and 50 kHz (right).

6. Conclusions

The exploration of new power electronics application areas presents opportunities and imposes requirements on the application of new power electronics topologies. The use of higher-level inverter topologies allows hybrid switching device configurations to become efficient solutions. Various methods exist for the prediction of power losses in such inverters. Analytical loss models provide, despite their drawbacks, a fast and straightforward way to narrow down the possible solution space in order to identify the dependencies of the losses on different device parameters, operating conditions, topologies, and modulation schemes. In this work, the analytical approach to power loss calculation for multi-level inverter topologies is discussed. An extensive review of the most widespread midpoint clamped three-level inverter topologies is provided. The setup and operation of these topologies are discussed. A particular emphasis is placed on the specifics of ANPC topologies with respect to these topologies’ extended degrees of freedom, e.g., the different applicable modulation schemes. The analytical loss calculation approach is thoughtfully described and a closed-form description of the switching and conduction loss calculation procedure for a broad range of inverter topologies is given. Modulation functions, conduction, and switching intervals, and the associated integration to obtain the analytical loss formulas, are reviewed in detail. The limitations and expandability of these equations are stressed. Furthermore, the application aspects of multi-level inverters are discussed. Exemplary power loss analysis is performed for different topologies, hybrid material device configurations, and modulation schemes. Future work to enhance analytical power loss calculation for multi-level inverter topologies should consider additional effects beyond those presented in the equations. Examples include the dead time or parallel conducting current paths within one switching position. An improved description of device parameters—for instance, through a more accurate representation of the device output characteristic—promises higher accuracy, especially at lower currents for bipolar devices. The extension to additional modulation techniques, such as SVPWM, by modifying the modulation waves (see Figure 4) also can be explored. Besides improving the accuracy of the analytical equations, potential future research directions for multi-level midpoint clamped inverter topologies, which are also associated with power loss prediction, can be identified. With respect to the ANPC topology, since it offers the most degrees of freedom, the implementation of novel modulation algorithms should be mentioned in order to optimize the discussed loss distribution and EMI performance. The optimization of the loss distribution is closely related to hot spot minimization, which in turn is linked to the cooling concept. In this context, heat sinks with more complex structures, possibly produced by novel manufacturing technologies, are interesting for thermal management, especially for multi-level topologies with their higher number of loss sources. This would benefit both efficiency and reliability. The design of optimized low-inductive commutation loops is critical since it significantly influences the efficiency and, more specifically, the switching losses, which are also calculated within this publication.