Figure 1.
Mesh DC microgrid.
Figure 1.
Mesh DC microgrid.
Figure 2.
Distributed generator unit i with local primary voltage controller: (a) electrical scheme and (b) state feedback primary control loop.
Figure 2.
Distributed generator unit i with local primary voltage controller: (a) electrical scheme and (b) state feedback primary control loop.
Figure 3.
Hierarchical control scheme of the microgrid under study: (a) consensus-based secondary controller and (b) state feedback primary controller.
Figure 3.
Hierarchical control scheme of the microgrid under study: (a) consensus-based secondary controller and (b) state feedback primary controller.
Figure 4.
Voltage cyber-attack detection and mitigation layer proposed for the primary controller of DGUi.
Figure 4.
Voltage cyber-attack detection and mitigation layer proposed for the primary controller of DGUi.
Figure 5.
Current cyber-attack detection and mitigation layer proposed for the secondary controller of DGUi.
Figure 5.
Current cyber-attack detection and mitigation layer proposed for the secondary controller of DGUi.
Figure 6.
Overall system with the distributed control strategy blocks for a single DGU.
Figure 6.
Overall system with the distributed control strategy blocks for a single DGU.
Figure 7.
Flowchart for the overall control strategy with cyber-attack mitigation layers.
Figure 7.
Flowchart for the overall control strategy with cyber-attack mitigation layers.
Figure 8.
Flowchart for voltage and current cyber-attack ANNs training.
Figure 8.
Flowchart for voltage and current cyber-attack ANNs training.
Figure 9.
Simulation case studies: objectives and targets.
Figure 9.
Simulation case studies: objectives and targets.
Figure 10.
First case study: (a) DGU voltages , (b) DGU output currents , (c) percentage errors in DGU voltages , (d) percentage change in current sharing , (e) voltage cyber-attack mitigation signals for DGUs, .
Figure 10.
First case study: (a) DGU voltages , (b) DGU output currents , (c) percentage errors in DGU voltages , (d) percentage change in current sharing , (e) voltage cyber-attack mitigation signals for DGUs, .
Figure 11.
Second case study: (a) , (b) , (c) , (d) , and (e) voltage cyber-attack mitigation signals for DGUs, .
Figure 11.
Second case study: (a) , (b) , (c) , (d) , and (e) voltage cyber-attack mitigation signals for DGUs, .
Figure 12.
Third case study: (a) , (b) , (c) , (d) , and (e) current cyber-attack mitigation signals for DGUs, .
Figure 12.
Third case study: (a) , (b) , (c) , (d) , and (e) current cyber-attack mitigation signals for DGUs, .
Figure 13.
Fourth case study: (a) , (b) , (c) , (d) , and (e) current cyber-attack mitigation signals for DGUs, .
Figure 13.
Fourth case study: (a) , (b) , (c) , (d) , and (e) current cyber-attack mitigation signals for DGUs, .
Figure 14.
Fifth case study: (a) , (b) , (c) , (d) , (e) voltage cyber-attack mitigation signals for DGUs, , and (f) current cyber-attack mitigation signals for DGUs, .
Figure 14.
Fifth case study: (a) , (b) , (c) , (d) , (e) voltage cyber-attack mitigation signals for DGUs, , and (f) current cyber-attack mitigation signals for DGUs, .
Figure 15.
Experimental setup.
Figure 15.
Experimental setup.
Figure 16.
DGU voltages during sequential voltage attacks.
Figure 16.
DGU voltages during sequential voltage attacks.
Figure 17.
DGUs output currents during sequential voltage attacks.
Figure 17.
DGUs output currents during sequential voltage attacks.
Figure 18.
Mitigation signals during sequential voltage attacks.
Figure 18.
Mitigation signals during sequential voltage attacks.
Figure 19.
DGUs voltages during mixed voltage attacks.
Figure 19.
DGUs voltages during mixed voltage attacks.
Figure 20.
DGUs output currents during mixed voltage attacks.
Figure 20.
DGUs output currents during mixed voltage attacks.
Figure 21.
Mitigation signals during mixed voltage attacks.
Figure 21.
Mitigation signals during mixed voltage attacks.
Figure 22.
Voltages during sequential current attacks.
Figure 22.
Voltages during sequential current attacks.
Figure 23.
Output currents during sequential current attacks.
Figure 23.
Output currents during sequential current attacks.
Figure 24.
Mitigation signals during sequential current attacks.
Figure 24.
Mitigation signals during sequential current attacks.
Figure 25.
Voltages during simultaneous current attacks.
Figure 25.
Voltages during simultaneous current attacks.
Figure 26.
Output currents during simultaneous current attacks.
Figure 26.
Output currents during simultaneous current attacks.
Figure 27.
Mitigation signals during simultaneous current attacks.
Figure 27.
Mitigation signals during simultaneous current attacks.
Table 1.
Line parameters.
Table 1.
Line parameters.
Connected DGUs (i,j) | Resistance Rij (Ω) | Inductance Lij (µH) |
---|
Line 1–3 | 0.07 | 2.1 |
Line 2–3 | 0.04 | 2.3 |
Line 2–4 | 0.08 | 1.8 |
Line 3–4 | 0.07 | 1 |
Table 2.
Buck converters and filter parameters.
Table 2.
Buck converters and filter parameters.
Input/Output Voltages: 100 V /48 V |
---|
DGU i | Resistance Rti (Ω) | Inductance Lti (mH) | Capacitance Cti (mF) | Local Load (Ω) |
---|
DGU 1 | 0.2 | 1.8 | 2.2 | 10 |
DGU 2 | 0.3 | 2.0 | 1.9 | 9 |
DGU 3 | 0.1 | 2.2 | 1.7 | 8 |
DGU 4 | 0.5 | 3.0 | 2.5 | 7 |
Table 3.
Primary and secondary layer controller parameters.
Table 3.
Primary and secondary layer controller parameters.
| Primary Controllers’ Gains |
---|
DGU 1 | = |
DGU 2 | |
DGU 3 | |
DGU 4 | |
Secondary Integral Controller Gain: = 0.02 |
Table 4.
Sequential voltage FDIA parameters.
Table 4.
Sequential voltage FDIA parameters.
DGU i | FDIA Value | Attack Instant |
---|
DGU 1 | | t = [8–10 s] |
DGU 2 | | t = [12–14 s] |
DGU 3 | | t = [16–18 s] |
DGU 4 | | t = [20–22 s] |
Table 5.
Simultaneous voltage FDIA parameters.
Table 5.
Simultaneous voltage FDIA parameters.
DGU i | FDIA Value | Attack Instant |
---|
DGU 1 | | t = [5–7 s] |
DGU 2 | | t = [5–7 s] |
DGU 4 | | t = [5–7 s] |
Table 6.
Simultaneous current FDIA parameters.
Table 6.
Simultaneous current FDIA parameters.
DGU i | FDIA Value | Attack Instant |
---|
DGU 1 | | t = [7–10 s] |
DGU 2 | | t = [7–10 s] |
DGU 3 | | t = [7–10 s] |
DGU 4 | | t = [7–10 s] |
Table 7.
Sequential current FDIA parameters.
Table 7.
Sequential current FDIA parameters.
DGU i | FDIA Value | Attack Instant |
---|
DGU 1 | | t = [8–10 s] |
DGU 2 | | t = [12–14 s] |
DGU 3 | | t = [16–18 s] |
DGU 4 | | t = [20–22 s] |
Table 8.
Mixed current and voltage FDIA parameters.
Table 8.
Mixed current and voltage FDIA parameters.
DGU i | FDIA Value | Attack Instant |
---|
DGU 1 |
| t = [7–9 s] |
DGU 2 |
| t = [12–14 s] |
DGU 3 | | t = [16–18 s] |
DGU 4 | | t = [16–18 s] |
Table 9.
Performance metrics for all case studies during cyber-attacks.
Table 9.
Performance metrics for all case studies during cyber-attacks.
Case Study | Average Percentage Voltage Error
| Average Percentage Change in Current Sharing
|
---|
Sequential voltage attack | 0.1% | 10% |
Simultaneous voltage attack | 1% | 10% |
Simultaneous current attack | 0% | 2% |
Sequential current attack | 0% | 0% |
Mixed current & voltage attack | 0.2% | 5% |