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Article

One-Cycle Fourier Finite Position Set PLL

by
Fernando Lino
1,†,
Jefferson Assis
2,†,
Darlan A. Fernandes
2,†,
Rogerio Jacomini
3,†,
Fabiano F. Costa
4,† and
Alfeu J. Sguarezi Filho
1,*,†
1
Engineering, Modeling and Applied Social Sciences Center, Federal University of ABC, Santo André 09210-180, Brazil
2
Department of Electrical Engineering, Federal University of Paraíba, João Pessoa 58051-900, Brazil
3
Instituto Federal de São Paulo, Hortolândia 13183-250, Brazil
4
Polytechnic School, Federal University of Bahia, Salvador 40210-630, Brazil
*
Author to whom correspondence should be addressed.
These authors contributed equally to this work.
Energies 2021, 14(7), 1824; https://doi.org/10.3390/en14071824
Submission received: 19 January 2021 / Revised: 8 February 2021 / Accepted: 10 February 2021 / Published: 25 March 2021
(This article belongs to the Section F: Electrical Engineering)

Abstract

:
This work introduces a new method for computing the angular position of the voltage of the grid—based on a finite set of angles—in the condition of failures in the distribution systems, as symmetrical and asymmetric voltage sags, unbalance, harmonic distortions, and frequency changes. This method is inspired in the model predictive control finite control set principles. In this way, the proposal employs the One-Cycle Fourier filter (OCF) to estimate the positive sequence of the voltage vector into the stationary α β -frame. The positive sequence voltages extracted from this filter is then handled by an algorithm that is implemented by a finite position set (FPS) for estimating the phase angle. In this way, the minimized cost function chooses the optimal angular position while using the predicted behavior of the grid voltage vector elements in d q frame. The structure, called One-Cycle Fourier Finite position Set Phase Locked Loop (OCF-FS-PLL), here is a composition of the OCF and the FPS. The results that were obtained in an experimental test bench validate the proposed method.

1. Introduction

One of the common uses of Phase-Locked Loop (PLL) is for the grid synchronization. Its application is essential and widely used in grid-connected power converters, such as distributed generation, static synchronous compensators, uninterrupted power supplies, and active power filters. The PLL is basically composed by three main components: the phase detector (PD), the loop filter (LP), and the voltage-controlled oscillator (VCO) [1]. Most of the use of PLL needs to occur in a fast and accurate way for detecting the phase angle of the positive sequence component, for the stable operation and dynamic recovery of these systems, especially under cases of distorted grid conditions, such as three-phase imbalances, harmonics, and low-voltage ride-through. Therefore, only the use of PLL is not sufficient. For such disturbance conditions, it becomes necessary to add a technique for extracting the positive sequence component.
The Synchronous Reference Frame PLL (SRF-PLL) is the most popular PLL used for synchronization in the control of distribute generation (DG) [2,3], where the three-phase voltages of the grid are decomposed into synchronous voltages v d and v q . The mentioned technique can be degrade its performance due to voltage distortions caused by the harmonics elements or due to the unbalanced voltages. Approaches for this limitation in the SRF-PLL were proposed, as in [4]. In this work, the SRF-PLL processes the computed positive sequence. In this way, it permits canceling out the effect of any harmonic elements from the positive sequence that is represented in the d q frame using a decoupling network.
The grid voltage with 90 -delayed versions without harmonics elements in three from four enhanced single-phase PLLs (EPLL) was presented in [5]. The six signals are employed to calculate the fundamental positive sequence while using the instantaneous sequence component (ISC) theory. The mentioned theory that allows for the sequence elements determined in the frequency-domain be computed in the time-domain is presented in [6], where six signals are employed to estimate the fundamental positive sequence. To realize the delay of 90 it is used the relation e ± j 2 π / 3 = 1 / 2 ± ( 3 / 2 ) e j π / 2 , which is, a gradient descend-based method to calculate the grid voltages instantaneous sequence components.
In order to build orthogonal signals, a dual second order generalized integrator (DSOGI) pre-filter was implemented [7], providing an effective harmonics attenuation that is caused by the negative sequence component due to unbalanced voltages [8]. However, the second-order generalized integrator (SOGI) can degrade its operation due to the presence of harmonics elements and frequency deviations [9]. The work [10] introduces one proposal to fix the cited problems. The quadrature voltage amplitude employing the frequency diversion a proposal was provided in [11] order to eliminate the second-harmonic oscillations in the computed parameters of SOGI-PLL correcting. To eliminate the presence of harmonics elements in the quadrature voltages, filters are used for harmonic robustness [12]. Adaptive notch filters (ANF) to build orthogonal signals using a sinusoidal wave were also proposed in [13,14]. The works [13] suggest inserting control loops into DSOGI-PLL and in the ANF-PLL to eliminate the DC component that is caused by saturation in the core of the voltage transformers or by second-order harmonics across the DC inverter bus.
In Ref. [15], the authors propose complex-coefficient filters (CCF-PLL) with the capability of harmonic rejection and also with fast dynamic response. In Ref. [16], a proposal to tuning of PI controllers enhances the CCF-PLL. A version for this proposal in the z domain can be seen in [17]. In order to reduce higher order harmonics and eliminate the interference arising from the negative sequence, complex filters of second and third-order is proposed in [18]. An effective frequency feedback in the loop of the PLL is implemented in the CCF-PLL as a proposal in [16].
A filter in the inner of the control loop of the PLL with the insertion of a lead compensator and a moving-average filter (MAF) rejects voltage asymmetrics and also harmonic interferences counteracting the dynamics that were introduced in that control loop [19]. A proportional gain component incoroprated in the MAF enables the PLL to reject low-order harmonics [20].
In Ref. [21], a one cycle Fourier PLL (OCF-PLL) is presented. This method employs the OCF to estimate positive sequence of the voltage of the grid that feeds the SRF-PLL; even the voltage has distortions caused by harmonics and DC elements.
Hence, OCF-PLL implementation fixes the frequency adaptability that is present in DSC-PLL and the DSOGI-PLL, providing adaptability in the case of frequency deviations. This implementation is also able to reject DC components of the voltages and with the capability to filter harmonics of different orders.
It is worth mentioning that, in all the works mentioned, PI controllers are used in their implementations of PLLs, which have to define their gain parameters for each operation point.
Model Predictive Control (MPC) propositions [22,23,24,25,26,27,28] have been presented in control scheme for power converters-inverters. The finite position set-phase locked loop (FPS-PLL) applied to the permanent-magnet synchronous generators (PMSG) was presented in [29,30]. The FPS-PLL stimates the optimal rotor position of the PMSG while using a finite number of rotor positions and the PMSG equations in the minimized cost function. This application do not need the classical PI controller. This a solution was not employed in grid voltage synchronization applications.
This work presents a new method for estimating the phase angle of the voltage of the grid based on a finite set of angles in the condition of failures in the distribution systems as symmetrical and asymmetric voltage sags, unbalance, harmonic distortions, and frequency changes.
In this way, the proposal employs the one-cycle Fourier filter (OCF) in order to estimate the positive sequence of the voltage vector into the stationary α β -frame. The positive sequence voltages extracted from this filter are then handled by an algorithm that is implemented by a finite position set (FPS) for estimating the phase angle. The structure that is composed of the OCF and the FPS is called one-cycle Fourier finite position set phase locked loop (OCF-FS-PLL). The experimental results show the good performance of the proposed work. A Dual Second-Order PLL (DOSGI-PLL) is used to compare it with the proposed work for balanced grid voltage with sag in the presence of the 5th and another voltage test under presence of harmonics as 5th, 7th, 11th, 13th, 17th, and 19th.
The rest of this work is structured in three sections. Section 2 is a systemic description for both of the algorithms: One-cycle Fourier and Finite Position Set. Section 3 presents the experimental results to evaluate the behavior of the OCF-FPS-PLL proposed and Section 4 concludes the article.

2. System Description—One-Cycle Fourier Finite Set Predictive Control PLL

The proposed work has two main components. The first component takes advantage of the extraction of the positive sequence while using the one-cycle Fourier filter (OCF), which is referred in [21], and the second one uses the finite position set (FPS) idea, as referred in [29].
Figure 1 depicts a flowchart with the first part of this work, where a sequence of operations is shown to compute the positive sequence extraction.
The positive sequence is present when the phase voltages are sinusoidal, with v s rotating counterclockwise and ω and v s being positive constants. If the power grid suffers an unbalance, then the vector v s will be the sum of two vectors: one of the negative sequence, v that rotates clockwise, with angular velocity − ω , and another of positive sequence, v + , rotating counterclockwise with velocity ω . The magnitudes of these vectors will be constant V and V + . Accordingly, for the positive sequence, the angular position will be θ + = ω t + ϕ + and, for the negative sequence, it will be θ = ω t + ϕ .

2.1. One-Cycle Fourier Algorithm

The v α signal that is distorted by harmonics and a DC component can be represented as:
v α ( t ) = X 0 + k = 1 X k c c o s ( k ω t ) + k = 1 X k s s i n ( k ω t )
The fundamental components X 1 c and X 1 s can be computed according the OCF algorithm as:
X 1 c = t T t v α ( t ) c o s ( ω t ) d t , X 1 s = t T t v α ( t ) s i n ( ω t ) d t
In the same way:
Y 1 c = t T t v β ( t ) c o s ( ω t ) d t , Y 1 s = t T t v β ( t ) s i n ( ω t ) d t
where the fundamental period is represented by T.
So, according [21]:
v α 0 + = V + cos ϕ + = 1 2 ( X 1 c + Y 1 s ) , v β 0 + = V + sin ϕ + = 1 2 ( Y 1 c X 1 s ) , v α 0 = V cos ϕ = 1 2 ( X 1 c Y 1 s ) , v β 0 = V sin ϕ = 1 2 ( Y 1 c + X 1 s )
Using the Equations (4), the magnitudes of the positive and negative sequences can be expressed:
V + = ( v α 0 + ) 2 + ( v β 0 + ) 2 , V = ( v α 0 ) 2 + ( v β 0 ) 2
and the initial phase-angles by:
ϕ + = arctan v β 0 + v α 0 + , ϕ = arctan v β 0 v α 0
The positive sequence can be computed while using the following set of equations:
v a + = V + cos ( ω 0 t + ϕ + ) , v b + = V + cos ω 0 t + ϕ + 2 π 3 , v c + = V + cos ω 0 t + ϕ + + 2 π 3
where the nominal frequency is ω = ω o .

2.2. Finite Position Set

Using the extraction of the positive sequence with the OCF algorithm, an algorithm utilizing the (FPS) predictive control scheme uses the finite number of angle positions to predict its future behavior over a given prediction horizon.
The first step is to sample and hold the positive sequence that is extracted from the first component, as shown in the Figure 2, by the block ZOH (zero order hold). That is, this block will obtain samples v a + [ k ] , v b + [ k ] and v c + [ k ] from the grid positive sequence v a + , v b + and v c + .
The continuous-time for the grid positive voltage, v g , α + and v g , β + , in the reference α β -frame is shown by Equation (8) and the same voltage v g , q + and v g , d + in the reference dq -frame by Equation (9), below:
v g , α + = 2 3 v a + 1 2 v b + 1 2 v c + , v g , β + = 1 3 ( v b + v c + )
v g , q + = v g , β + cos θ 1 v g , α + sin θ 1 , v g , d + = v g , α + cos θ 1 + v g , β + sin θ 1
where θ 1 is the angular position of the grid positive voltage.
Adopting the grid voltage-oriented as the reference frame, aligning the direct axis of the reference system with the vector of voltage, i.e., the grid voltage q-component is zero, as stated in Equation (10), below.
v g , q + = 0
This second part works with samples. Accordingly, Equations (11) and (12) are the discretized Equations (8) and (9).
v g , α + [ k ] = 2 3 v g , a + [ k ] 1 2 v g , b + [ k ] 1 2 v g , c + [ k ] , v g , β + [ k ] = 1 3 ( v g , b + [ k ] v g , c + [ k ] )
v g , q + [ k , i , j ] = v g , β + [ k ] cos θ 1 [ k , i , j ] v g , α + [ k ] sin θ 1 [ k , i , j ] , v g , d + [ k , i , j ] = v g , α + [ k ] cos θ 1 [ k , i , j ] + v g , β + [ k ] sin θ 1 [ k , i , j ]
The strategy is based on a finite number of positions (eight positions for every iteration) due to the fact that the phase of the voltage of the grid changes between 0 and 2 π rad. Its implementation was based on the iteration-based algorithm that was presented in [29].
Hence, defining the initial position θ i n [ k , i ] in order to obtain a finite number of angles, through the use of two nested iteration loops with indices i and j (each linked to discrete values), a finite number of positions for the grid positive sequence q-component can be obtained. The discretized angular position can be expressed as:
θ 1 [ k , i , j ] = θ i n [ k , i ] + [ ( j 1 ) 4 ] Δ θ [ k , i ] ,
where:
Δ θ [ k , i ] = π 4 2 ( i 1 )
Now, a cost function is defined in order to select the optimal (estimated) angular position:
g [ k , i , j ] = | 0 v g , q + [ k , i , j ] |
Thus, the angular position that minimizes the cost function was obtained using 64 interactions. Hence, v g , q + [ k , i , j ] reaches the closest value of the zero.
In order to understand how the technique works, suppose that θ i n [k,1] = 0 rad and g i n = . Looking at Equation (14), in the first round of the first loop, ( i = 1 ) and Δ θ [k,1] = π 4 rad, and using the Equation (13), the generated angles are: π , 3 π 4 , π 2 , π 4 , 0, π 4 , π 2 , 3 π 4 rad. With each one of these values, θ 1 [k,i,j] permits computing the q -axis element v g , q + . In this way, the second round employs the angle that allows for minimizing the cost function θ i n [k,2]. Hence, the accuracy of the technique is increased by a factor of 2. In this way, eight new angular positions can be computed while using Equation (13). Hence, they can be π 8 , π 4 , 3 π 8 , π 2 , 5 π 8 , 3 π 4 , 7 π 8 rad. The algorithm reaches the optimal grid angular position due to the increment of the number of iterations. Continuing with the iteration, in the last one (i = 8), the estimator grid angular position is found. Thereby, the algorithm provides an accuracy of 1 2 × π 4 × 2 7 = π 1024 = 0.003 rad. To clarify, a supposition that π 2 is the optimal angle computed in the first round of the loop. Hence, in the second round (i = 2) and Δ θ [k,2] = π 8 rad, and so on. Figure 3 shows the flowchart of the proposed search technique.
The estimated angular speed ω ^ 1 [ k ] (Equation (16)) is then calculated, as indicated in Figure 2, where T s is the sampling time.
ω ^ 1 [ k ] = θ ^ 1 [ k ] θ ^ 1 [ k 1 ] T s
where k−1 and k are the previous and actual values at the sampling instants, respectively.
A second-order Butterworth filters the signal ω ^ 1 [ k ] . Its output ( ω 1 ) is the estimated angular speed voltage ( ω ^ 1 [ k ] ) filtered, as depicted in Figure 2.
No matter how time consuming this solution is, it is better when compared to conventional PLLs, as tuning often becomes time effort. This solution has a long execution time when compared to the SRF-PLL. However, the systems of energy conversion systems employs sampling frequency below (≤5 kHz) [31]. In this way, the sampling period is enough to compute the proposal technique and the control algorithm due to the high capacity of the digital signal processors.
One of the drawbacks of the proposed OCF-FS-PLL is the ripples in the estimated angular position when compared with the conventional SRF-PLL. The mentioned ripple was produced because of the finite set of angles that permits to select the optimal angular position. Hence, the mentioned angle may not represent the actual value of the position exactly. Accordingly, this angular position contains (much) lower oscillations.
The precision of the proposal can be increased when the number of rounds are improved. Hence, the oscillations can be smoothed in the estimated position/frequency. In this way, a trade-off between precision and computational burden must be reached. In this work, the values of the rounds were fixed to i, j [ 1 , 8 ] and a sampling frequency as 50 kHz.
A point to be highlighted is that, although the OCF-FS-PLL rejects harmonics very well, the operation with the presence of interharmonics is not supported by it, as it is designed according to the fundamental component; therefore, being the subject of future work.

3. Experimental Results

The evaluation of the proposed OCF-FS-PLL performance in a experimental bench depicted in Figure 4 was built using programmable power source connected to a three-phase restive load, digital signal processor (DSP) from Texas Instruments TMS 320F28335 and electronic boards for signal conditioning and data acquisition of voltage signals to interface with the TMS 320F28335 DSP. The DSP was programmed while using the Code Composer Studio of Texas instruments and one has a sampling frequency of 50 KHz. The algorithmic rule computes the ω 1 , the estimated angular speed, and the constructed grid voltage positive sequence components.
Using the programmable power source, it is possible to set up a maximum voltage value of 220 V and power of 3 kW, and it can program performing unbalanced and balanced voltage sags while adding or not harmonic components. It is also possible to program the fundamental component with harmonics up to the 30th order. The DSP is a C2000 real-time micro-controller that includes a development ANSI C/C++ compiler/assembler/linker for easy adaptation from simulation code of MATLAB. Figure 5 presents a block diagram of the experimental platform to clarify the connections between the components of the practical test.
In order to evaluate the behavior of the OCF-FPS-PLL proposed, four different scenarios were generated and compared with the strategy DSOGI-PLL. (1) The voltage sag had a reduction in peak value of the voltage in 0.5 p.u. in two phases of the three ones, where v a = 1 p.u., v b = 0.5 p.u., and v c = 0.5 p.u. (2) balanced grid voltage sag of 50% under the presence of the 5th harmonic with 14% of the rated voltage. (3) balanced grid voltage distorted by 5th, 7th, 11th, 13th, 17th, and 19th harmonics components (4) balanced grid voltage with frequency deviation from 60 to 65 Hz. The base voltage value is 100 V.

3.1. Unbalanced Voltage with Sag in Two Phases

In this test, a sag was inserted in two phases of the grid voltage. This insertion was at a time near 1.103 s and it was removed near 1.445 s, as shown in Figure 6. This figure shows the unbalanced voltage sag in the two phases of the grid voltage (Figure 6), the phase for the OCF-FS-PLL (Figure 7), the d-component from the OCF-FS-PLL, the DSOGI-PLL, and the SRF-PLL (Figure 8), and the estimated output frequency for them (Figure 9). In this last figure, the SRF-PLL output frequency of 120 Hz can be seen [32].
The test showed that the OCF-FS-PLL has a better dynamics when compared to DSOGI-PLL, as can be seen in Figure 9 and Table 1. M p is the percentage of overshoot, t s is the settling time in frequency and in the d-component ( V d ). The column oscillation shows the limits in frequency amplitudes and the column Δ V d is the variation range for V d in p.u.

3.2. Balanced Grid Voltage Sag under the Presence of 5th Harmonic

In this test, it was inserted in the grid voltage with the presence of 5th harmonic. A balanced voltage sag was inserted at a time close to 0.724 s, and it was removed near 1.057 s, as shown in Figure 10.
Figure 10 shows the balanced voltage sag under the presence of 5th harmonic and Figure 11 shows the phase of the OCF-FS-PLL. Figure 12 shows the d-component from the OCF-FS-PLL, the DSOGI-PLL, and the SRF-PLL, and Figure 13 shows the estimated output frequency for them.
In the same way, the test showed that OCF-FS-PLL has better dynamics than DSOGI-PLL, as can be seen in Figure 13 and in Table 1.
The obtained result also showed that OCF-FS-PLL has better THD (Total Harmonic Distortion) when compared to DSOGI-PLL. This is due to the better immunity to harmonic noise being performed by the OCF filter, as can be seen in Table 2.

3.3. Balanced Grid Voltage Distorted by 5th, 7th, 11th, 13th, 17th and 19th Harmonics Components

In this test, it was inserted a balanced grid voltage distorted by 3.94% in 5th, 3.15% in 7th, 2.36% in 11th, 1.50% in 13th, 1.10% in 17th, and 0.70% in 19th harmonics components. Figure 14 shows the input balanced grid voltage that was distorted by harmonics. Figure 15 shows the phase of the OCF-FS-PLL. Figure 16 shows the d-component from the OCF-FS-PLL, the DSOGI-PLL, and also the SRF-PLL, and Figure 17 shows the estimated output frequency for them.
The test showed that OCF-FS-PLL has better dynamics than DSOGI-PLL, as can be seen in Figure 17 and Table 1.
As can be seen, the results showed that OCF-FS-PLL has better THD (Total Harmonic Distortion) when compared to DSOGI-PLL. As already mentioned, this is due to the better immunity to harmonic noise being performed by the OCF filter, as can be seen in Table 3.

3.4. Balanced Grid Voltage with Frequency Deviation

In this test, a change in frequency from 60 to 65 Hz was done at 0.4 s. Figure 18 shows the input balanced grid voltage with a deviation in the frequency from 60 to 65 Hz. Figure 19 shows the phase of the OCF-FS-PLL. In Figure 20, the d-component for the OCF-FS-PLL, the DSOGI-PLL, the OCF-SRF-PLL, and the SRF-PLL can be seen. Additioonally, Figure 21 shows the transient state in response to a step in the frequency from 60 to 65 Hz for all of them. A point to be noted is that the OCF-SRF-PLL requires two cascading blocks in the case of frequency adaptability, designated as AOCF-PLL, as presented in [21]. In the OCF-FS-PLL, there is no need.
Again, the test showed that OCF-FS-PLL has better dynamics than DSOGI-PLL, as can be seen in Table 1.

4. Conclusions

In this paper, a new Finite Position Set Predictive Control PLL has been proposed, which enjoys the One-cycle Fourier (OCF) filter to extract the grid positive sequence. This proposal employs the model predictive control fundamentals, in which a finite set of angles using the discrete angular position of the voltage of the grid. Hence, the optimal angular position is chosen by means of a minimized cost function.
In this context, the presented results permits endorsing the performance of the proposal. Additionally, the proposal (OCF-FS-PLL) has better performance when compared with another solution, such as SRF-PLL, DSOGI-PLL, and OFC-SRF-PLL, for the tests under unbalanced voltage in two phases, voltage balanced sag under the presence of 5th harmonic, voltage distorted by harmonics components as 5th, 7th, 11th, 13th, 17th, and 19th and balanced grid voltage with a frequency deviation from 60 to 65 Hz. However, the algorithmic rule can have a high computational burden with the increase of the number of interactions. Additionally, the proposal when the voltages are distorted by the interhamonics elements is a challenge for future works.
Using this work, three improvements could be observed in the implementation of PLL. As a first, it was shown that the OCF filter used in the OCF-FS-PLL has a better noise immunity in the presence of harmonics. The second improvement was the best response in the cases of frequency deviations in the electrical grid when compared with OCF-SRF-PLL. It is also noteworthy here that the OCF-SRF-PLL requires two cascading blocks in the case of frequency adaptability, while the OCF-FS-PLL does not. Additionally, as a third, the implemented Finite Set (FS) algorithm in the PLL in this work has the advantage of not using PI controllers, which needs to gain adjustments for each operation point.

Author Contributions

Conceptualization, A.J.S.F. and F.L.; methodology, A.J.S.F., R.J., F.L., D.A.F., J.A. and F.F.C.; software, A.J.S.F., R.J., F.L., D.A.F., J.A. and F.F.C.; validation, A.J.S.F., F.L., D.A.F., J.A. and F.F.C.; formal analysis, R.J., A.J.S.F., F.L., D.A.F., J.A. and F.F.C.; investigation, F.L.; resources, A.J.S.F., F.L., D.A.F., J.A. and F.F.C.; data curation, A.J.S.F., R.J., F.L., D.A.F., J.A. and F.F.C.; writing—original draft preparation, F.L. and R.J.; writing—review and editing, A.J.S.F., R.J., F.L., D.A.F., J.A. and F.F.C.; visualization, A.J.S.F. and R.J.; supervision, A.J.S.F.; project administration, A.J.S.F.; funding acquisition, A.J.S.F. and D.A.F. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding by CNPQ and FAPESP.

Acknowledgments

The authors acknowledge the Brazilian Counsel of Technological and Scientific Development (CNPq) processes 437435/2018-0 and 405757/2018-2 and the São Paulo State Research Support Foundation (FAPESP) by the financial and material support provided by both institutions.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Positive sequence extraction algorithm.
Figure 1. Positive sequence extraction algorithm.
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Figure 2. Block diagram of the proposed One-cycle Fourier-Finite Set-Phase-Locked Loop (OCF-FS-PLL).
Figure 2. Block diagram of the proposed One-cycle Fourier-Finite Set-Phase-Locked Loop (OCF-FS-PLL).
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Figure 3. Flowchart of the proposed OCF-FS-PLL.
Figure 3. Flowchart of the proposed OCF-FS-PLL.
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Figure 4. Experimental setup.
Figure 4. Experimental setup.
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Figure 5. Block diagram—connections between components.
Figure 5. Block diagram—connections between components.
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Figure 6. Unbalanced grid voltage sag in two phases.
Figure 6. Unbalanced grid voltage sag in two phases.
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Figure 7. Grid position during unbalanced grid voltage sag in two phases.
Figure 7. Grid position during unbalanced grid voltage sag in two phases.
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Figure 8. The v g , d positive sequence component during unbalanced grid voltage sag in two phases.
Figure 8. The v g , d positive sequence component during unbalanced grid voltage sag in two phases.
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Figure 9. Grid frequency during unbalanced grid voltage sag in 2 phases.
Figure 9. Grid frequency during unbalanced grid voltage sag in 2 phases.
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Figure 10. Balanced grid voltage sag under the presence of the 5th harmonic.
Figure 10. Balanced grid voltage sag under the presence of the 5th harmonic.
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Figure 11. Grid position during voltage sag under the presence of the 5th harmonic.
Figure 11. Grid position during voltage sag under the presence of the 5th harmonic.
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Figure 12. The v g , d positive sequence component during voltage sag under the presence of the 5th harmonic.
Figure 12. The v g , d positive sequence component during voltage sag under the presence of the 5th harmonic.
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Figure 13. Grid frequency during voltage sag under the presence of the 5th harmonic.
Figure 13. Grid frequency during voltage sag under the presence of the 5th harmonic.
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Figure 14. Balanced grid voltage distorted by 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
Figure 14. Balanced grid voltage distorted by 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
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Figure 15. Grid position during voltage sag under the presence of 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
Figure 15. Grid position during voltage sag under the presence of 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
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Figure 16. The v g , d positive sequence component during voltage sag under the presence of 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
Figure 16. The v g , d positive sequence component during voltage sag under the presence of 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
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Figure 17. Grid frequency during voltage sag under the presence 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
Figure 17. Grid frequency during voltage sag under the presence 5th, 7th, 11th, 13th, 17th, and 19th harmonics components.
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Figure 18. Balanced grid voltage with frequency change.
Figure 18. Balanced grid voltage with frequency change.
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Figure 19. The grid position during grid voltage with frequency change.
Figure 19. The grid position during grid voltage with frequency change.
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Figure 20. The v g , d of the positive sequence component during grid voltage with frequency change.
Figure 20. The v g , d of the positive sequence component during grid voltage with frequency change.
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Figure 21. The frequency of the grid voltage with frequency change.
Figure 21. The frequency of the grid voltage with frequency change.
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Table 1. Response of the OCF-FS-PLL and dual second order generalized integrator-PLL (DSOGI-PLL).
Table 1. Response of the OCF-FS-PLL and dual second order generalized integrator-PLL (DSOGI-PLL).
Parameters M p [%] t s [ms]
(freq.)
osc.
[Hz]
t s [ms]
( V d )
Δ V d
[p.u.]
Need PI
Controller
Unlanced voltage sag
OCF-FS-PLL13.06-±0.3120.7370.0122No
SRF-PLL15.81-±8.742.4040.3731Yes
DSOGI-PLL2.08-±0.9116.4770.0122Yes
Balanced voltage sag
with 5th harmonic
OCF-FS-PLL14.79-±0.2422.6390.0092No
SRF-PLL0.34-±0.890.0010.1230Yes
DSOGI-PLL0.44-±2.2717.1720.0349Yes
Balanced voltage
with 5th, 7th, 11th, 13th, 17th and 19th harmonics
OCF-FS-PLL--±0.022-0.0086No
SRF-PLL--±1.561-0.0781Yes
DSOGI-PLL--±4.711-0.0114Yes
Frequency deviation
OCF-FS-PLL1.2129.312±0.02-0.0003No
SRF-PLL0.3213.955±0.04-0.0021Yes
DSOGI-PLL0.0926.894±0.04-0.0012Yes
Table 2. Filtering performance of the OCF-FS-PLL and DSOGI-PLL under 5th harmonic.
Table 2. Filtering performance of the OCF-FS-PLL and DSOGI-PLL under 5th harmonic.
SignalTHD [%]
Input voltage14.04
DSOGI-PLL output voltage2.95
OCF-FS-PLL output voltage0.42
Table 3. Filtering performance of the OCF-FS-PLL and DSOGI-PLL under 5th, 7th, 11th, 13th, 17th, and 19th harmonics.
Table 3. Filtering performance of the OCF-FS-PLL and DSOGI-PLL under 5th, 7th, 11th, 13th, 17th, and 19th harmonics.
SignalTHD [%]
Input voltage4.44
DSOGI-PLL output voltage1.02
OCF-FS-PLL output voltage0.05
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Lino, F.; Assis, J.; Fernandes, D.A.; Jacomini, R.; Costa, F.F.; Sguarezi Filho, A.J. One-Cycle Fourier Finite Position Set PLL. Energies 2021, 14, 1824. https://doi.org/10.3390/en14071824

AMA Style

Lino F, Assis J, Fernandes DA, Jacomini R, Costa FF, Sguarezi Filho AJ. One-Cycle Fourier Finite Position Set PLL. Energies. 2021; 14(7):1824. https://doi.org/10.3390/en14071824

Chicago/Turabian Style

Lino, Fernando, Jefferson Assis, Darlan A. Fernandes, Rogerio Jacomini, Fabiano F. Costa, and Alfeu J. Sguarezi Filho. 2021. "One-Cycle Fourier Finite Position Set PLL" Energies 14, no. 7: 1824. https://doi.org/10.3390/en14071824

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