# Multivariable Deadbeat Control of Power Electronics Converters with Fast Dynamic Response and Fixed Switching Frequency

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## Abstract

**:**

## 1. Introduction

## 2. System Modelling

#### 2.1. Continuous Static Reference Frame Model

_{dc}is the capacitor at the dc side. Furthermore, the power converter voltage related to the switches’ states is:

**s**

^{abc}represent the converter switching functions

#### 2.2. Discrete Static Reference Frame Model

## 3. Predictive Control Strategy

#### 3.1. Power Converter Voltage

**v**

_{o}^{abc}, as the control actuating variable, it can be generated as a function of the desired future value of the currents. Together, the source currents

**i**

_{s}^{abc}and voltages

**v**

_{s}^{abc}provide the total power consumption, which in turn sets the power factor and the amount of active power drained by the load.

**i**

_{s}^{αβ}(k + 1), the parameters of the filter, and the sampling time T

_{s}:

**i**

_{s}^{αβ}(k + 1) is the power converter current reference,

**v**

_{s}^{αβ}(k) the supply voltage, and

**v**

_{o}^{αβ}(k) the converter injected voltage; Rs and Ls are the filter parameters. However, due to processing delays, the voltage

**v**

_{o}^{αβ}cannot be calculated and applied at the same time k. Therefore, time delay compensation is mandatory. Subsequently, the voltage in Equation (9) is to be expressed as:

**i**

_{s}^{αβ}(k + 1),

**v**

_{s}^{αβ}(k + 1) can be estimated by using the following procedure.

_{s}, thus the estimation of the source voltage is found to be

#### 3.2. Current References as a Function of the Power Reference

**i**

_{s}^{abc}and the voltages

**v**

_{s}^{abc}. In fact, the power consumed by the topology is given by:

**v**

_{s}^{abc}(k + 2) can be found by assuming the frequency and amplitude as constant, as was mentioned in Equation (11), to find:

#### 3.3. Power Reference Calculation

- -
- dc load power consumption: This contribution represents what the power converter is supplying to the dc loads through the current i
_{L}^{dc}. The related dc power is computed as:

- -
- ac inductive filter losses: The filter included on the ac side has natural losses, associated to R
_{s}, due to the non-ideality of the inductance, and can be calculated as:

- -
- Power supplied to the dc capacitor: The dc link capacitor C
_{dc}is charged/discharged in order to maintain the dc voltage to its reference. Therefore, this power is regulated by the dc voltage control. The energy on the dc capacitor at time t is given by:

^{dc}(k + 2) is required. An estimation of this voltage at k + 1 can be found solving Equation (8) as:

^{dc}(k + 2) cannot be estimated from Equation (28) because this voltage would be based on the unknown switching states

**s**

^{αβ}at time (k + 1), i.e.,

**s**

^{αβ}(k + 1). Thus, the estimation of the voltage v

^{dc}(k + 2) is obtained by interpolation as:

_{L}

^{dc}is considered as a disturbance and changes as a function of the load requirements, the estimation turns into a difficult task considering this as an uncertain future value. Therefore,

_{L}

^{dc}, will influence the control as a delay of two steps at most, with:

_{s}is close to zero. The prediction

**i**

_{s}^{αβ}(k + 1) can therefore be found by using Equation (13) and the current

**i**

_{s}^{αβ}(k + 2) can be found similarly as performed for the dc link voltage at time (k + 2) in Equation (29), where the interpolation can now define p

_{RL}(k + 2) to be:

^{ref}is the angle between the voltage and the current (capacitive or inductive) and may be defined by the power factor (pf) as:

## 4. Multivariable Fast-Dynamic Deadbeat Control

**v**

_{o}^{abc}due to the finite value of the dc link voltage v

^{dc}.

_{s}, which can be tens of microseconds. This operation may cause an excessive increase in the power demanded by the control, which can be beyond the rated values of the converter, and therefore, generate an inflated power reference, only due to the presence of noise.

_{Cdc}shall be introduced to reduce the noise effect on the power reference, altering Equation (34) to be:

_{m}> 1 represents the times in which the response is delayed; to speed up computations in the controller, this term is transformed into k

_{Cdc}as follows:

_{max}represents the maximum rated power the converter.

## 5. Simulation and Experimental Results

#### 5.1. Simulative Results

#### 5.2. Response under Model Uncertainties

_{s}are reduced to 50% from their original value, i.e., L

_{s}changes from 4.75 to 2.375 mH, whilst the controller still considers L

_{s}= 4.75 mH. The results show the control has good performance, despite the high noise presented due to the reduced inductance not being capable of properly mitigating the switching effects.

_{s}to 9.5 mH (twice the original value), whilst the control always considers L

_{s}= 4.75 mH. The noise in this case is low because the filter is enlarged. The results show the control can cope with variation of this type and keep stability and reference tracking.

_{s}of 50% and 200% from the original value, respectively. In both cases, the controller considers the original resistance value of R

_{s}= 0.4 Ω. In both cases, the effectiveness of the proposed control strategy even under parametric uncertainty is demonstrated, keeping the rapidness of the dc link voltage and regulating the current in order to keep the phase shift between the voltage and current close to zero. In addition, in all cases, there is no overshoot on the dc link voltage response, being one of the most distinguished advantages of the proposal.

_{s}inductor implies a reduction in noise in the current but also makes the control slower; therefore, the inductor can be selected by a procedure related to the allowed current ripple, the nominal current, and the switching frequency as reported in [42]. On the other hand, the capacitor affects the dc voltage dynamic, where larger capacitors help to maintain the voltage under disturbances as voltage sags/swells or changes on the current drained i

_{L}

^{dc}[43,44]. In Figure 5, there are results including different parameters in order to test the power converter control under different inductances and capacitors values, where, in this case, the control has the correct parameters into the algorithm. Figure 5 (1) shows the results where the inductance increases its values to 200% with respect to the nominal value listed in Table 1, where the noise in the current shows a moderate reduction but the power control shows a slower dynamic. In Figure 5 (2), the inductances are reduced to 50% with respect to the nominal value and the noise is higher but not as high as the noise shown in Figure 4 (1), because the controller has the correct parameter in the algorithm and therefore, the prediction error is reduced. When the capacitor is increased (Figure 5 (3)) or decreased (Figure 5 (4)), the dc voltage dynamic changes notoriously; therefore, this greatly increases its rapidness for the low C

_{dc}value. However, the higher the value of the capacitor, the more effective rejection to disturbances achieved. Thus, there is an equilibrium that does not allow the capacitor to be reduced; in fact, if some imbalance appears, then the capacitor should be large enough to reduce the second order harmonic in the v

_{dc}which causes a third harmonic in the ac currents. Another interesting case is the H-Bridge topology, which is noted to include a second order voltage and which is mostly reduced by enlarging the dc capacitor [45].

#### 5.3. Experimental Tests

**i**

_{s}^{abc}is always maintained within certain boundaries that ensure not to exceed the maximum power, yet the power reference is reached in the shortest time, related to the current time response, i.e., about 100µs without over-modulation. In effect, the theoretical development says the voltage reference can be attained in three sample times; however, due to the amount of power required for this action, the time is enlarged to avoid damage to the power converter components. Therefore, the dc link voltage is reached in the shortest possible transient time to avoid exceeding the power converter limits.

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 3.**Simulated Results, (

**a**) dc voltage and reference, (

**b**) v

_{s}

^{α}voltage and i

_{s}

^{α}current, (

**c**)

**i**

_{s}^{αβ}currents, (

**d**) active p

_{s}and reactive q

_{s}power; (

**1**) p

_{s}

_{max}= 5 kW, (

**2**) p

_{s}

_{max}= 10 kW.

**Figure 4.**Model uncertainties, (

**a**) dc voltage and reference, (

**b**) v

_{s}

^{α}voltage and i

_{s}

^{α}current, (

**c**)

**i**

_{s}^{αβ}currents, (

**d**) active p

_{s}and reactive q

_{s}power, with (

**1**) inductances decrease to 50%, (

**2**) inductances increase to 200%, (

**3**) resistances decrease to 50%, (

**4**) resistances increase to 200%.

**Figure 5.**Different parameters, (

**a**) dc voltage and reference, (

**b**) v

_{s}

^{α}voltage and i

_{s}

^{α}current, (

**c**)

**i**

_{s}^{αβ}currents, (

**d**) active p

_{s}and reactive q

_{s}power, (

**e**) load current i

_{L}

^{dc}, with (

**1**) inductances increase to 200%, (

**2**) inductances decrease to 50%, (

**3**) capacitor increases to 200%, (

**4**) capacitor decreases to 50%.

**Figure 7.**Experimental Results, (

**a**) dc voltage step up with unitary power factor, (

**b**) dc voltage step up with power factor of 0.7(inductive), (

**c**) change on the power factor, (

**d**) load step up from 0 (A) to 4.7 (A).

Parameters | Value |
---|---|

v_{s} (grid nominal voltage value) | 230 V, rms |

v^{dc} (dc link nominal voltage) | 700 V |

R_{s} (filter resistance) | 0.4 Ω |

L_{s} (filter inductance) | 4.75 mH |

C_{dc} (dc link capacitor) | 2.2 mF |

f_{s} (grid frequency) | 50 Hz |

T_{s} (controller sampling time) | 50 µs |

f_{sw} (switching frequency) | 20 kHz |

T_{m} (controller parameter) | 25 p.u. |

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## Share and Cite

**MDPI and ACS Style**

Rohten, J.A.; Dewar, D.N.; Zanchetta, P.; Formentini, A.; Muñoz, J.A.; Baier, C.R.; Silva, J.J. Multivariable Deadbeat Control of Power Electronics Converters with Fast Dynamic Response and Fixed Switching Frequency. *Energies* **2021**, *14*, 313.
https://doi.org/10.3390/en14020313

**AMA Style**

Rohten JA, Dewar DN, Zanchetta P, Formentini A, Muñoz JA, Baier CR, Silva JJ. Multivariable Deadbeat Control of Power Electronics Converters with Fast Dynamic Response and Fixed Switching Frequency. *Energies*. 2021; 14(2):313.
https://doi.org/10.3390/en14020313

**Chicago/Turabian Style**

Rohten, Jaime A., David N. Dewar, Pericle Zanchetta, Andrea Formentini, Javier A. Muñoz, Carlos R. Baier, and José J. Silva. 2021. "Multivariable Deadbeat Control of Power Electronics Converters with Fast Dynamic Response and Fixed Switching Frequency" *Energies* 14, no. 2: 313.
https://doi.org/10.3390/en14020313