# Closed-Form Formulas for Automated Design of SiC-Based Phase-Shifted Full Bridge Converters in Charger Applications

^{*}

## Abstract

**:**

## 1. Introduction

_{abc}and the dc-link voltage V

_{dc}is simple, the same is not the case with regard to the PSFB part of the charger. The output voltage V

_{o}has an intricate dependence on eight design parameters: V

_{dc}, load resistance R

_{o}, phase-shift ratio φ, switching frequency f

_{s}, transformer turns ratio n, magnetizing inductance L

_{m}, series inductance L

_{l}, and output inductance L

_{o}; however, the literature provides no closed-form formulas that encompass all of these dependencies. So far, one approach to this problem has been to design the converter based on some very approximate calculations and then to let the voltage controller set φ to obtain the desired value of V

_{o}. However, the problem is that for many combinations of the design parameters there is simply no value of φ that leads to a particular required V

_{o}value at the given output power level (P

_{o}). Additionally, if the converter does work at the required voltage and power conditions, it is certain to be overdesigned, which implies unnecessarily high losses, dimensions, and costs. Another, more prevalent method is to conduct simulations at the required V

_{dc}, V

_{o}, and P

_{o}values [10]. This is a valid but not scalable solution, i.e., it cannot be efficiently automated for multi-objective optimization of the design.

## 2. Materials and Methods

#### 2.1. Topological Details

_{AC}), six SiC MOSFETs (T

_{1}–T

_{6}), as well as a DC-link capacitor (C

_{dc}). The PSFB consists of a transformer with turns ratio n and magnetizing inductance L

_{m}, two inductors (L

_{l}, L

_{o}), four SiC MOSFETs (T

_{7}–T

_{10}), four SiC diodes (D

_{1}–D

_{4}), and two capacitors (C

_{dc}′, C

_{o}). As depicted in Figure 3b, the AFE controller takes in six measurements (input currents i

_{b}and i

_{c}, input voltages v

_{a}, v

_{b}, and v

_{c}, and the DC-link voltage v

_{dc}) and provides six control signals (s

_{1}–s

_{6}). On the other hand, the PSFB controller requires one measurement (output voltage v

_{o}) and provides four control signals (s

_{7}–s

_{10}). The role of the inductor L

_{l}should be elaborated here: in certain operating conditions, its presence is not necessary. The converter can operate using only the energy accumulated in the magnetic field of the primary-side leakage inductance of the transformer to charge and discharge parasitic output capacitances of the switches [27,28]. However, at light-load high-voltage conditions that magnetic energy might be insufficient [29], and the result may be not only lower efficiency due to lack of zero-voltage switching but also the destruction of the transistors due to entering undesirable off-states, in which DC-link voltage is almost evenly divided between the high-side and the low-side switch.

#### 2.2. Topology Analysis

_{dc}), load resistance (R

_{o}), phase shift ratio (φ), switching frequency (f

_{s}), transformer turns ratio (n), magnetizing inductance (L

_{m}), series inductance (L

_{l}), and output filter inductance (L

_{o}). These parameters can be observed throughout Figure 4.

_{7}–s

_{10}) shown in Figure 4b, and have the total duration of half of the switching period 1/f

_{s}. Note that the remaining three states are not discussed here since inductor-related waveforms in the second half of the switching period are symmetrical to those in the first half. Furthermore, due to its relatively low value in SiC applications (c.a. 100 ns), deadtime is omitted, and additional states resulting from it are not considered.

#### 2.2.1. State I Analysis

_{s}) it can be observed that there is no energy transfer from the DC-link to the load. Magnetic energy accumulated in various inductances is redistributed between these inductances and between them and the load. The exact nature of the energy flow is dictated by how voltage is shared among these inductances. Voltage V

_{o}, which is kept constant by the output capacitor C

_{o}, is divided between the transformer and the output inductor proportionally, as resulting from the inductance values and the turns ratio. It should be noted that, starting from (1), only the eight aforementioned design parameters are used, and, as in the case of (2), the previously defined expressions. Thereby, final expressions will also depend exclusively on the design parameters set. The levels of voltage applied during state I across inductances L

_{m}(V

_{Lm}

_{(I)}), L

_{l}(V

_{Ll}

_{(I)}), and L

_{o}(V

_{Lo}

_{(I)}) can be obtained in the following manner:

_{Lm}and i

_{Lo}decrease, while i

_{Ll}increases. The changes in i

_{Lm}, i

_{Ll}, and i

_{Lo}in this state are defined as Δi

_{Lm}

_{(I)}, Δi

_{Ll}

_{(I)}, and Δi

_{Lo}

_{(I)}, respectively.

#### 2.2.2. State II Analysis

_{s}. Parameter λ is not directly set by the control signals, as in the case of φ, but it rather depends on a couple of parameters, including φ:

_{m}, L

_{l}, and L

_{o}are defined as V

_{Lm}

_{(II)}, V

_{Ll}

_{(II)}, and V

_{Lo}

_{(II)}, respectively.

_{Lm}does not change, i

_{Ll}continues to increase, and i

_{Lo}decreases. In this state, absolute values of change in i

_{Lm}, i

_{Ll}, and i

_{Lo}are defined as Δi

_{Lm}

_{(II)}, Δi

_{Ll}

_{(II)}, and Δi

_{Lo}

_{(II)}, respectively.

#### 2.2.3. State III Analysis

_{s}and the voltage values across inductances L

_{m}, L

_{l}, and L

_{o}are defined as V

_{Lm}

_{(III)}, V

_{Ll}

_{(III)}, and V

_{Lo}

_{(III)}, respectively.

_{Lm}, i

_{Ll}, and i

_{Lo}all increase, as energy from the DC-link is accumulated in magnetic fields. In this state increments of i

_{Lm}, i

_{Ll}, and i

_{Lo}are defined as Δi

_{Lm}

_{(III)}, Δi

_{Ll}

_{(III)}, and Δi

_{Lo}

_{(III)}, respectively.

_{Lo}current must satisfy the following condition:

#### 2.2.4. Derivation Results—Output Voltage Expression

_{m}, it is important to know the instantaneous current values at the beginning of state I (I

_{Lm}

_{(I)}) and at the beginning of state II (I

_{Lm}

_{(II)}). These values can be obtained based on the total increment of the magnetizing inductance current (Δi

_{Lm}), calculated using partial increments from (4) and (17).

_{l}, on the other hand, it is instrumental to know the instantaneous values at the beginning of the first four states (I

_{Ll}

_{(I)}, I

_{Ll}

_{(II)}, I

_{Ll}

_{(III)}, I

_{Ll}

_{(IV)}). These parameters can be calculated based on the total current swing of the series-inductance current (Δi

_{Ll}) and the partial increments obtained in (5), (12), and (18):

_{Lo}at the beginning of the first four states (I

_{Lo}

_{(I)}, I

_{Lo}

_{(II)}, I

_{Lo}

_{(III)}, I

_{Lo}

_{(IV)}) are also required. These can be calculated based on the design parameter n, instantaneous current values obtained in (23) and (25), and partial increments from (6) and (13).

_{o}is clearly shown. Especially noteworthy is the influence of f

_{s}and L

_{l}, since setting either of these values too high can greatly limit the available range of V

_{o}. This can be, in turn, partially remedied by increasing n; however, such action would have its own downsides, as will be shown in the following subsection. It should also be kept in mind that aside from the first-order parameters listed in Table 2 and used in (37), there are many second-order parasitic parameters present in any laboratory prototype. Their absence from (37) indicates that the accuracy of the laboratory experiments will be slightly lower than 100%.

#### 2.2.5. Derivation Results—Semiconductor-Loss-Related Parameters

_{1}, r

_{2}, and r

_{3}can be calculated based on design parameter φ and (5), (7), (12), (18), and (25)–(28). The actual rms value of the transistor, I

_{T}

_{7}

_{(rms)}, can be obtained directly from r

_{1}–r

_{3}, while the turn-off instantaneous transistor current value I

_{T}

_{7(off)}is equal to (28).

_{D}

_{1(rms)}) calculation, q

_{1}–q

_{3}, can be obtained based on the design parameter φ and Formulas (6), (7), (19), and (30)–(32), while the average diode current value (I

_{D}

_{1(avg)}) can be calculated using φ, (7), and (30)–(32).

_{T}

_{7(cond)}, can be calculated based on the on-state resistance value of the transistor r

_{T7}obtained from a datasheet and on (41). Switching power loss of a transistor, P

_{T7(sw)}, can be calculated based on the switching frequency and on turn-off energy E

_{off}

_{_T7}(I

_{T}

_{7(off)}; V

_{dc}). It should be noted that using a datasheet, approximating functions should be used to calculate E

_{off_T}

_{7}based on the switching current value (42) and the switching voltage value (V

_{dc}). Such functions depend on the shapes of the characteristics in a datasheet and, in some cases, a first-order approximation can be assumed whereby the turn-off energy is linearly proportional to both the current and the voltage. As for the diode conduction loss, P

_{D}

_{1(cond)}, it can be obtained based on the piecewise linear approximation of forward characteristics from a datasheet, where V

_{D}

_{1(th)}is the threshold voltage and r

_{D1}is the slope of the characteristic beyond the threshold. Often there is no need to manually extract the data from the characteristics as ready formulas are provided in the datasheet. Finally, total semiconductor losses P

_{loss}

_{(tot)}can be calculated by multiplying all the losses of single switches by the number of each type of switch—4.

_{o}= 650 V at V

_{dc}= 800 V and P

_{o}= 10 kW one cannot use n lower than around 0.85, since at this point the required value of φ reaches 0% and it cannot decrease any further. On the other hand, one cannot use n higher than approximately 1.0, since above that value the circuit leaves the CCM. Operation in Discontinuous Conduction Mode (DCM) would lead to high output capacitor current stress and increased electromagnetic interference (EMI). This figure shows that the transformer turns ratio has the greatest impact on the total switching and conduction semiconductor losses; therefore, n should be kept as small as possible. On the other hand, too small values of L

_{m}, L

_{l}, and L

_{o}as well as of f

_{s}should be avoided to limit these losses.

#### 2.3. Control Scheme for Grid-Connected Operation

_{dc}) control loop, both PI-based. As for the PSFB, PI-based control of the output voltage (v

_{o}) is implemented. A Phase-Shift Modulation (PSM) block is applied to delay control signals of the second phase-leg (s

_{9}, s

_{10}) with relation to the first phase-leg signals (s

_{7}, s

_{8}) by keeping the value of φ between 0 and 0.5 (see Figure 4b).

_{a}, v

_{b}, v

_{c}, v

_{dc}) and current (i

_{b}, i

_{c}) values. A doubled sampling frequency of 120 kHz was used to decrease control loop delay. As a result, the delay between the measurements and the control loop response equal to 1.5 times the control period was obtained. Three ADC channels were used to reduce measurement latency so that the total of six signals could be converted to digital form during two ADC conversion cycles. Furthermore, each measurement channel features analogue low-pass filters with a cut-off frequency of around 300 kHz.

## 3. Results

#### 3.1. Laboratory Setup

#### 3.2. Laboratory Tests

#### Steady-State Operation

_{dc}and output voltage v

_{o}are kept constant with the exception of some acceptable amount of ripple.

_{dc}read from these screenshots, as well as from screenshots for all other operating points, V

_{o}values were calculated with the Formula (37) and compared with V

_{o}values obtained from the power analyzer. Results were juxtaposed in the following figures. Figure 13 shows two modes in which the steady-state experiments were conducted: fixed output voltage mode and maximum output voltage mode. In the first one, the output voltage was fixed at a particular value, which meant that the device was operated with closed-loop voltage control, and the value of φ was varied at levels above zero. In the second mode, the PSFB was operated in the open loop with phase shift ratio φ equal to zero to obtain the highest possible value of output voltage V

_{o}(see Figure 5c). It should be noted that the dots in Figure 13 correspond to the results obtained from the laboratory experiments, while the lines are values calculated using (37). Due to the parasitic resistances of the laboratory setup, the fitting cannot be ideal; however, the results predicted by the model are very close to the measured ones.

_{dc}and P

_{o}values, the higher is V

_{o}, the lower are the losses. This conclusion is in line with the analytical results shown in Figure 8. On the other hand, the efficiency of the AFE in these two modes remains unchanged.

#### 3.3. The Design Procedure

_{o}by substituting R

_{o}with V

_{o}

^{2}/P

_{o}:

_{dc}, output voltage V

_{o}, output power P

_{o}, and maximum allowable ripple factor RF

_{max}of the output inductor current. The thermal part, on the other hand, provides the requirements regarding the operating ambient temperature T

_{a}, and maximum allowable junction temperatures of the transistors (T

_{jT(max)}) and the diodes (T

_{jD(max)}).

_{s}, turns ratio n, magnetizing inductance L

_{m}, series inductance L

_{l}, and output inductance L

_{o}can be therefore provided in array forms with several values of each parameter in its particular array. The same is the case with the heatsink and the semiconductor database. As a result, the entire procedure is repeated as many times as there are unique combinations of each value of f

_{s}, n, L

_{m}, L

_{l}, L

_{o}, and each model of the heatsink, transistor, and diode. Throughout each iteration, first, φ is calculated using (55) and it is checked whether its value lies between 0 and 0.5. If it does not, then this iteration is stopped, and the next set of design parameters is loaded, restarting from (55). If φ is located in the range (0; 0.5), the phase shift ratio is used for further calculations using Formulas (1)–(19), after which the value of RF is obtained based on (20) and compared with RF

_{max}from the application requirements. If RF is higher than RF

_{max}, the iteration is cancelled, and the next parameter set is selected. If RF is low enough, calculations (21)–(32) and (38)–(47) are conducted and the following values are obtained: I

_{T}

_{7(rms)}, I

_{T}

_{7(off)}, I

_{D}

_{1(rms)}, I

_{D}

_{1(avg)}, but also V

_{Lm}

_{(I)}and V

_{Lm}

_{(III)}. Using values of voltages V

_{Lm}

_{(I)}, V

_{Lm}

_{(III)}, and also n, the diode database is restricted to only those diodes with a high enough breakdown voltage value. Formulas for this can be observed in the diode waveforms in Figure 6b. Similar exclusion of the lower-voltage transistors is conducted based on the value of V

_{dc}. For the remaining diodes, the following values are imported from the database: threshold voltage V

_{D}

_{1(th)}, dynamic resistance r

_{D1}, and junction-case thermal resistance R

_{th,j-c(D)}. For the remaining transistors, the following values are obtained: on-state resistance r

_{T7}, switch-off energy E

_{off}

_{_T7}(calculated using V

_{dc}and I

_{T}

_{7(off)}), and junction-case thermal resistance R

_{th,j-c(T)}. Afterwards, calculations using Formulas (48)–(51) are conducted to obtain losses in each transistor and diode, as well as the total losses. Using the thermal specification from the application requirements, a component from the heatsink database, and the results obtained so far, calculations (52) and (53) are realised. If any of the maximum junction temperatures are exceeded (T

_{jT}higher than T

_{jT(max)}or T

_{jD}higher than T

_{jD(max)}), the iteration stops and the next set of design parameters is considered, starting from (56). If the calculated temperatures are low enough, this particular design set is added to a viable design set and placed on a characteristic, such as these shown in Figure 17. After all defined sets are analyzed and qualified as either viable or not viable, the characteristics are completed and a design is selected according to the desired priority, e.g., lowest semiconductor losses, smallest volume, or lowest cost. Such results are provided in Table 5, where the application requirements used are provided in the table caption and the results of the automatic selection are provided in the table body. For each power level, three optimization directions were taken, and the appropriate fields contain underlined values to show this. For example, for the 20-kW PSFB with the lowest cost in mind, one should opt for C3M0032120J1 SiC transistors, STPSC20H12C SiC diodes, and LA V 6 150 12 heatsink. In that case, the recommended series inductance L

_{l}is 25 μH. This is almost the maximum inductance value that will allow obtaining V

_{o}= 650 V for the given conditions, while minimizing the total losses (see Figure 8d). Of course, a more developed semiconductor and heatsink database could provide results that are even better than these. By comparing the results from Table 5 and Figure 17 it can be seen that the optimal designs are placed in the lower left corners of the characteristics.

## 4. Discussion

_{o}, as referred to in this work, becomes the DC-link voltage, and parameter V

_{dc}becomes the output voltage of the photovoltaic array. Proper definition of the transformer turns ratio should also be assumed, as shown in Figure 1b. In future work, magnetic design procedure could be incorporated into this method, including losses in those components. This would enable prediction of total volume of the converter in the same automated fashion. Nevertheless, the main point is that without an accurate and verified formula such as (37), this sort of optimization of converters based on PSFB topology would not be possible.

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A

_{dc}, and nine other parameters that are defined here: m, p, c, d, e, h, g, b, and z. As will be shown in the formulas below, all these parameters consist only of the remaining design parameters: R

_{o}, φ, f

_{s}, n, L

_{m}, L

_{l}, and L

_{o}. As a result, the expression (37) is shown to consist exclusively of the main set of design parameters. First, let us define two auxiliary parameters: k

_{1}and k

_{2}.

_{1}–m

_{5}can be obtained, which leads to a simple calculation of m.

_{1}–p

_{4}, p, is calculated in a straightforward manner.

_{1}–c

_{3}, the design parameters, and (A1)–(A2).

_{1}and d

_{2}, the design parameters, and (A1)–(A2).

_{1}–h

_{3}, the design parameters, and (A1)–(A2).

_{1}and g

_{2}is required.

_{1}–z

_{3}.

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**Figure 1.**Sample applications of the AFE + PSFB isolated grid-connected AC–DC converter: (

**a**) EV charger; (

**b**) PV Inverter.

**Figure 3.**Schemes: (

**a**) detailed, showing components; (

**b**) generalized, with control and measurement signals.

**Figure 5.**Output voltage calculation as a function of design parameters. Blue lines show the results according to Formula (37), PLECS simulation results for various parameters are in red, while results for selected parameters are symbolized by stars. The design parameters are: (

**a**) V

_{dc}; (

**b**) R

_{o}; (

**c**) φ; (

**d**) f

_{s}; (

**e**) n; (

**f**) L

_{m}; (

**g**) L

_{l}; (

**h**) L

_{o}.

**Figure 6.**Analysis of PSFB operation continued: (

**a**) independent states IV and V; (

**b**) vital semiconductor waveforms.

**Figure 7.**Semiconductor current parameters—Formulas (41), (42), (46), (47) shown as lines vs. PLECS simulation results shown as symbols. Varied design parameter: (

**a**) V

_{dc}; (

**b**) R

_{o}; (

**c**) φ; (

**d**) f

_{s}; (

**e**) n; (

**f**) L

_{m}; (

**g**) L

_{l}; (

**h**) L

_{o}.

**Figure 8.**P

_{loss}

_{(tot)}(green) and φ (purple) at constant input and output parameters with V

_{dc}= 800 V, V

_{o}= 650 V / 690 V, P

_{o}= 10 kW. Varied design parameters are: (

**a**) f

_{s}; (

**b**) n; (

**c**) L

_{m}; (

**d**) L

_{l}; (

**e**) L

_{o}.

**Figure 10.**Laboratory setup: (

**a**) connection scheme; (

**b**) AFE (left side) with PSFB (right side); (

**c**) entire experimental setup.

**Figure 11.**Waveforms of the converter with voltage of phase a (v

_{a}) in black, current of phase a (i

_{a}) in light blue, DC-link voltage (v

_{dc}) in red, and output voltage (v

_{o}) in green at V

_{dc}= 800 V, P

_{o}= 10 kW and: (

**a**) V

_{o}= 650 V; (

**b**) V

_{o}= 690 V.

**Figure 12.**Power analyzer measurements of the converter at V

_{dc}= 800 V, P

_{o}= 10 kW and: (

**a**) V

_{o}= 650 V; (

**b**) V

_{o}= 690 V.

**Figure 13.**Output voltage as a function of output power in both examined modes—the fixed and the maximum output voltage mode. The symbols represent the experimental results, and the lines are obtained using Formula (37).

**Figure 14.**Relative error of Formula (37) in both examined modes: (

**a**) fixed output voltage; (

**b**) maximum output voltage.

**Figure 15.**Efficiency characteristics of both stages in both modes: (

**a**) PSFB in fixed output voltage mode; (

**b**) PSFB in maximum output voltage mode; (

**c**) AFE in fixed output voltage mode; (

**d**) AFE in maximum output voltage mode.

**Figure 17.**Sets of automatically generated designs using the developed analytical model and databases of various types of transistors, diodes, and heatsinks. The application requirements are V

_{dc}= 800 V, V

_{o}= 650 V, RF

_{max}= 1, T

_{a}= 25 °C, T

_{jT(max)}= 150 °C, T

_{jD(max)}= 150 °C, P

_{o}= 10 kW: (

**a**) losses vs. volume; (

**b**) cost vs. volume; (

**c**) cost vs. losses vs. volume; and P

_{o}= 20 kW: (

**d**) losses vs. volume; (

**e**) cost vs. volume; (

**f**) cost vs. losses vs. volume.

Parameter | Symbol | Value |
---|---|---|

Input voltage | V_{abc} | 3 × 400 V, 50 Hz |

DC-link voltage | V_{dc} | 800 V |

Output voltage | V_{o} | 650 V |

Output power | P_{o} | 20 kW |

Parameter | Symbol | Value |
---|---|---|

DC-link voltage | V_{dc} | 800 V |

Load resistance | R_{o} | 21.125 Ω |

Phase shift ratio | φ | 1.43% |

Switching frequency | f_{s} | 25 kHz |

Turns ratio | n | 0.9 |

Magnetizing inductance | L_{m} | 792 μH |

Series inductance | L_{l} | 14.15 μH |

Output inductance | L_{o} | 60 μH |

AFE | PSFB | |
---|---|---|

Controller | TMS320F28379D DSP | 10CL025 FPGA |

Control frequency | 60 kHz | 25 kHz |

Deadtime | 100 ns | 165 ns |

ADC sampling | 12 bit, 120 kS/s | 12 bit, 250 kS/s |

Resources used | CPU + CLA | ~20k LE |

**Table 4.**Selected components of the AC–DC–DC charger prototype operating at V

_{abc}= 3 × 400 V, V

_{dc}= 600 V–800 V, P

_{o}= 5 kW–10 kW, f

_{s}= 25 kHz, f

_{s}

_{(AFE)}= 60 kHz.

Component | Parameter | Value | Model |
---|---|---|---|

PSFB transformer | n | 0.9 | Payton T10000AC-9-10 |

L_{m} | 792 μH | ||

PSFB series inductor | L_{l} | 14.15 μH (incl. transf. leak.) | Custom-made |

PSFB output inductor | L_{o} | 60 μH | Custom-made |

AFE input inductors | L_{AC} | 210 μH | Custom-made |

AFE transistors | T_{1}–T_{6} | - | C3M0021120K |

PSFB transistor | T_{7}–T_{8} | - | 2 × SCTH100N120G2-AG |

PSFB diodes | D_{1}–D_{4} | - | 2 × STPSC20H12CWL |

**Table 5.**Results of operation of the automated component selection tool for PSFB. The following specification requirements are assumed: V

_{dc}= 800 V, V

_{o}= 650 V, RF

_{max}= 1, T

_{a}= 25 °C, T

_{jT(max)}= 150 °C, T

_{jD(max)}= 150 °C, P

_{o}= 10 kW / 20 kW.

P_{o} | Volume [dm^{3}] | Cost | P_{loss(tot)} [W] | T_{7}–T_{10} | D_{1}–D_{4} | Heatsink | f_{s} [kHz] | n | L_{m} [mH] | L_{l} [μH] | L_{o} [μH] |
---|---|---|---|---|---|---|---|---|---|---|---|

10 kW | 0.375 | $115 | 169 | C3M0120100K | STPSC20H12C | LAM 5 150 12 | 20 | 0.9 | 1.5 | 36 | 130 |

0.375 | $466 | 76 | CAB011M12FM3 | C4D40120D | LAM 5 150 12 | 20 | 0.9 | 1.5 | 36 | 130 | |

0.125 | $183 | 92 | C3M0032120J1 | C4D15120H | LAM 5 50 12 | 20 | 0.9 | 1.5 | 36 | 130 | |

20 kW | 0.688 | $193 | 382 | C3M0032120J1 | STPSC20H12C | LA V 6 150 12 | 20 | 0.9 | 1.5 | 25 | 130 |

0.688 | $495 | 211 | CAB011M12FM3 | C4D40120D | LA V 6 150 12 | 20 | 0.9 | 1.5 | 25 | 130 | |

0.459 | $252 | 299 | C3M0032120J1 | C4D15120H | LA 6 100 12 | 20 | 0.9 | 1.5 | 25 | 130 |

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## Share and Cite

**MDPI and ACS Style**

Wolski, K.; Grzejszczak, P.; Szymczak, M.; Barlik, R.
Closed-Form Formulas for Automated Design of SiC-Based Phase-Shifted Full Bridge Converters in Charger Applications. *Energies* **2021**, *14*, 5380.
https://doi.org/10.3390/en14175380

**AMA Style**

Wolski K, Grzejszczak P, Szymczak M, Barlik R.
Closed-Form Formulas for Automated Design of SiC-Based Phase-Shifted Full Bridge Converters in Charger Applications. *Energies*. 2021; 14(17):5380.
https://doi.org/10.3390/en14175380

**Chicago/Turabian Style**

Wolski, Kornel, Piotr Grzejszczak, Marek Szymczak, and Roman Barlik.
2021. "Closed-Form Formulas for Automated Design of SiC-Based Phase-Shifted Full Bridge Converters in Charger Applications" *Energies* 14, no. 17: 5380.
https://doi.org/10.3390/en14175380