Asymmetric Multilevel Inverter Topology and Its Fault Management Strategy for High-Reliability Applications

Abstract

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

1. Introduction

The increased adoption of power electronics in all areas in the electrical power domain has made various feasible innovations such as electric vehicles [1,2], HVDC transmission systems, large-scale transformation towards renewable energy resources [3]. With the DC–AC conversion playing a significant role, the development of multilevel inverters (MLIs) is an essential process. Succeeding the conventional two-level and three-level inverter topologies, MLIs possess the advantages of better power quality, efficient conversion, reduced thermal management, smaller filter size as well as in-built redundancy and voltage boosting features [4,5]. The classical MLI topologies are the Neutral Point Clamped (NPC), the Flying Capacitor (FC), and the Cascaded H-bridge (CHB) topologies. Since their inception, a vast diversity of newer structures has been proposed to eliminate the disadvantages of classical topologies. They include reduced device count, lower per-unit total standing voltage, and greater efficiency converters. Recent developments in MLI design are also focused on EMI, volume, weight and cooling, and packaging requirements [6].

Implementing a large number of power semiconductor switches leads to an increased susceptibility towards fault and makes monitoring and diagnosis more complex [7]. This can be unacceptable in safety-critical applications such as onboard power systems. Isolated sites with heavy economic penalties for downtime and maintenance or repair such as an offshore wind farm also demand high reliability [8,9,10]. Power converters are frequently operated in high-stress environments and less than optimal cooling management. One survey on electrical drive systems concluded that 47% of 484 failures were caused by semiconductor components [11]. Another survey concluded that 37% of unexpected maintenance routines and 59% of maintenance expenditures are single-handedly caused by inverters in a 5-year operation period of a 3.5 MW PV system. These figures present the need for the reliable and fault-tolerant design of MLIs [12].

Switch faults can manifest either as an open-circuit fault or a short-circuit fault. Open-circuit faults occur through various mechanisms such as bond-wire lift-off, gate driver failure, or internal connection rapture due to thermal or mechanical shocks [13]. This work investigates the same. Researchers in this regard have made significant efforts. Reducing electrical or thermal stress can decrease failure probability. Including redundant states in the topology can make the post-fault operation possible. An early effort is made in [14] on an FC topology, compromising with device count and having capacitor imbalance issues, thus increasing the cost and complexity of the structure. Adding extra legs to individual modules for modular multilevel converter (MMC) topologies is investigated in [15], with similar consequences of increased switch count and complexity. Switches in parallel and an extra capacitor have been added in structure [16] for fault handling capability. It adds to the circuit size, and the power loss of the converter increases. The use of a high number of DC sources for producing higher levels is also a disadvantage. A hybrid MLI with reduced device count is proposed in [17], eliminating some of the drawbacks. However, the low-level post-fault operation leads to poor power quality, unsuitable for the majority of applications. Z-source inverter topology has been discussed with fault tolerant feature in [18].

Likewise, a large number of switches in an MLI further leads to significant challenges in fault detection. Researchers have devised various techniques for fault detection. A work proposed in [19] uses voltage vectors of the converter. Similarly, detection works using switching frequency component magnitude [20], voltage pattern mass center [21], a sliding mode observer for comparison between the actual state and simulated state [22], and bridge voltage mean [23] can be noted. Fault detection using output voltage mean can also be observed in [24,25]. The advent of artificial intelligence (AI) with powerful and low-cost microcontrollers has made the application of AI techniques ubiquitous in power electronics [26]. Correspondingly, AI techniques have seen significant use in fault detection [27,28,29]. Although fault detection in CHB-MLIs has been investigated in multiple works [24,29,30,31,32], few works have focused on reduced device count topologies.

On account of the above, this paper proposes a reduced device count asymmetric multilevel inverter topology capable of producing 11 levels under healthy operation with fault tolerance across any switch undergoing an open-circuit fault, including across multiple switches simultaneously in some cases. The proposed fault-tolerant inverter is suitable for applications with high reliability demands. One application can be in renewable energy systems in remote or rural areas, where maintenance or repair can be significantly resource-intensive or delayed. The reduced peak level or power quality can still be useful as a temporary measure until repair. Another application where fault tolerance is crucial is vehicles onboard power electronics, where in the case of a fault, reduced power is still useful to function for a long enough duration to get the vehicle to a safe location. Post-fault modulation reconfiguration and use of redundant switches is used to handle switch open-circuit faults in this work. The healthy, under fault and post-fault conditions are examined and validated through simulation results. Moreover, a fault detection strategy based on artificial intelligence techniques is also presented, which can localize a fault under varying load and modulation index conditions. After fault mitigation, continued operation with an acceptable quality waveform on the output can be performed.

2. Proposed Structure

The proposed 11-level topology is depicted in Figure 1. Observably, the structure comprises six unidirectional switches and three bidirectional switches, requiring 12 IGBT components. A pair of bidirectional switches S₈ and S₉ are redundant, with these switches being used exclusively under faulty states. The structure utilizes three DC sources with per unit magnitudes of 0.5, 1, and 1, respectively. The structure can generate an 11-level output voltage waveform, with five levels each of positive and negative polarity, respectively, and a zero level. The switching strategy under healthy operation is described in

Table 1. Switching states for the proposed topology.

S1	S2	S3	S4	S5	S6	S7	V0
1	0	1	0	1	0	0	0
1	0	1	0	0	1	0	V1
1	0	0	0	1	0	1	V2
1	0	0	0	0	1	1	V1 + V2
1	0	0	1	1	0	0	2V2
1	0	0	1	0	1	0	V1 + 2V2
0	1	0	1	0	1	0	0
0	1	0	1	1	0	0	−V1
0	1	0	0	0	1	1	−V2
0	1	0	0	1	0	1	−(V1 + V2)
0	1	1	0	0	1	0	−2V2
0	1	1	0	1	0	0	−(V1 + 2V2)

, and the corresponding conduction diagram is presented in Figure 2. The ratio of the magnitude of the dc sources is as V₂ = V_dc and V₁ = 0.5V_dc. The total standing voltage (TSV) of the structure is 20V_dc, with the per-unit TSV having a magnitude of 20/2.5 = 8V_dc.

3. Fault-Tolerant Strategy

The modulation scheme must be reconfigured after an open-circuit fault is detected on any of the switches to sustain operation with acceptable output power quality and THD. The strategy for faults across individual switches is given in

Table 2. Fault management strategy.

Faulty Switches	Levels Preserved Post-Fault	Peak Levels Remaining
S1 or S2	±V2, ± 2V2, zero	±2V2
S3 or S4	±V2, ±(V1 + V2), zero	±(V2 + V1)
S5 or S6	±V2, ± 2V2, zero	±2V2
S7	±V1, ±2V2, ±(V1 + 2V2), zero	± (V1 + 2V2)

. The open-circuit fault can result in a reduced output power rating due to the loss of the peak level ±5V_dc in particular cases.

The blocking voltages of the switches are given as

$${\mathrm{S}}_1={\mathrm{S}}_2=2.5{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$$

(1)

$${\mathrm{S}}_3={\mathrm{S}}_4=2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$$

(2)

$${\mathrm{S}}_5={\mathrm{S}}_6=0.5{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$$

(3)

$${\mathrm{S}}_7=2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$$

(4)

$${\mathrm{S}}_8={\mathrm{S}}_9=3{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$$

(5)

The total TSV (total standing voltage) of the structure calculated as the sum of individual maximum blocking voltages is obtained as 18V_dc, with the per-unit TSV having a magnitude of 18/2.5 = 7.2V_dc. The switch voltage stresses do not increase post-fault and remain at their healthy condition or lower values.

Modulation Strategy

Implementing a low-frequency modulation technique effectively reduces voltage transients, snubber requirements, switching losses and has a positive effect on the reliability of the inverter [33]. Selective harmonic elimination (SHE-PWM) and nearest level control (NLC-PWM) are two techniques based on low frequency modulation. SHE is better at reducing the filter size by mitigating the lower order harmonics, but it requires solving complex transcendental equations which is computationally intensive. Moreover, the closed-loop implementation of NLC-PWM is simpler. This work uses NLC-PWM in light of the above issues. The switching angles θ_i [34,35] are calculated using:

$${\theta }_i=M_a{sin}^{-1}\left(\frac{2i-1}{N-1}\right)$$

(6)

where MI stands for the modulation index with i = 1,2, …(N − 1)/2 (N = number of levels). The modulation index MI is equal to

$$M_{a }= \frac{V_{ref}}{V_0}$$

(7)

Post-fault, modulation is reconfigured to generate new switching angles to maintain the output power quality with reduced or inconsecutive levels.

• Fault in S₁ or S₂ or S₅ or S₆

The generation of levels ±V₁, ± (V₁ + V₂), ± (2V₂ + V₁) cannot be sustained following a fault that occurs in this situation. The levels ±V₂ and ±2V₂ are produced post-fault. The respective conduction diagram under R-L load is shown in Figure 3. The load power rating is reduced as a result of the loss of the peak level. Modulation reconfiguration can give a satisfactory output voltage THD.

2.

Fault in S₃ or S₄

The levels ±V₁, ±2V₂, and ± (2V₂ + V₁) are lost in this case. The conduction diagram following this fault is given in Figure 4. Indeed, the fault leads to a similar reduction in load power rating.

3.

Fault IN S₇

Following a fault in S₇, the levels ±V₁, ±2V₂ cannot be further produced. However, a fault in this location does not affect the load power rating, as the peak level ±(2V₂ + V₁) is preserved. The conduction diagram for this scenario is illustrated in Figure 5.

4. Reliability Assessment

A reliability assessment is instrumental in evaluating the robustness of a circuit towards environmental stresses and gradual degradation. It is instrumental in predicting the expected lifespan of the inverter.

4.1. Component Failure Rate Evaluation

The failure rates of various components are influenced by numerous factors, such as voltage stress, thermal behavior, environment, as described in MIL-HDBK-217F [36]. The failure rate of a semiconductor switch is derived as:

$${\mathsf{\lambda }}_{\mathrm{s}}{=\mathsf{\lambda }}_{\mathrm{b}}{\times \mathsf{\pi }}_{\mathrm{T}}{\times \mathsf{\pi }}_{\mathrm{A}}{\times \mathsf{\pi }}_{\mathrm{R}}{\times \mathsf{\pi }}_{\mathrm{S}}{\times \mathsf{\pi }}_{\mathrm{Q}}{\times \mathsf{\pi }}_{\mathrm{E}}$$

(8)

where the base failure rate λ_b is given as 0.00074. The thermal parameter π_T is given by:

$${\mathsf{\pi }}_{\mathrm{T}}=\exp (-2114(\frac{1}{T_J+273}-\frac{1}{298}))$$

(9)

where T_J is the junction temperature of the device. The application factor π_A corresponds to switching and is considered as 0.7. The power rating factor π_R is given as

$${\mathsf{\pi }}_{\mathrm{R}}={P_r}^{\left(0.37\right)}$$

(10)

where P_r is the power rating of the switch. The voltage stress factor π_S is given using

$${\mathsf{\pi }}_{\mathrm{R}}=0.45 \times \exp \left(3.1\times V_S\right)$$

(11)

where V_S = V_CE (applied collector to emitter voltage)/V_CEO (rated collector to emitter voltage with base open). The quality factor π_Q is taken as unity for JANTX specifications. The environment factor (π_E) is considered as benign ground environment with a value of unity.

1.

Thermal Power Loss

The non-ideal behavior of switches is manifested in the form of their conduction losses and switching losses. It, in turn, elevates the junction temperature of the device, resulting in decreased reliability and efficiency. The total conduction loss in an IGBT diode module in a fundamental period can be evaluated using Equation (12).

$${\mathrm{P}}_{\mathrm{c} }={\displaystyle \sum }_{\mathrm{k}=1}^{{\mathrm{N}}_{\mathrm{sw}}}\frac{1}{2\mathsf{\pi }}{{\displaystyle \int }}_0^{2\mathsf{\pi }}\left({\mathrm{V}}_{\mathrm{sw}}\mathrm{i}\left(\mathrm{t}\right){+\mathrm{R}}_{\mathrm{s}}{\mathrm{i}}^{\mathsf{\beta }}\left(\mathrm{t}\right)\right)\mathrm{dt}+{\displaystyle \sum }_{\mathrm{k}=1}^{{\mathrm{N}}_{\mathrm{D}}}\frac{1}{2\mathsf{\pi }}{{\displaystyle \int }}_0^{2\mathsf{\pi }}{(\mathrm{V}}_{\mathrm{D}}\mathrm{i}\left(\mathrm{t}\right){+\mathrm{R}}_{\mathrm{D}}{\mathrm{i}}^2\left(\mathrm{t}\right))\mathrm{dt}$$

(12)

In the preceding expression, V_sw represents the ON-state switch voltage drop, R_s stands for the ON-state switch resistance; similar terms are denoted for the diode D. The module current is given by i(t). Further, the switching losses in the module can be computed by the following equations:

$${\mathrm{P}}_{\mathrm{s} }=\left[{\displaystyle \sum }_{\mathrm{k}=1}^{\mathrm{Ns}}{(\mathrm{N}}_{{\mathrm{ON}}_{\mathrm{k}}}{\mathrm{E}}_{{\mathrm{ON}}_{\mathrm{k}}}{+\mathrm{N}}_{{\mathrm{OFF}}_{\mathrm{k}}}{\mathrm{E}}_{{\mathrm{OFF}}_{\mathrm{k}}}) \right]\times \mathrm{f}$$

(13)

Here, ${\mathrm{N}}_{{\mathrm{ON}}_{\mathrm{k}}}$ and ${\mathrm{E}}_{{\mathrm{ON}}_{\mathrm{k}}}$ are taken as the number of transitions to OFF states and the associated energy loss, respectively, for the kth device, with the second term for ON transitions. The fundamental frequency is being denoted by f. The total thermal losses as an algebraic sum of the average conduction and switching losses is given by:

$${\mathrm{P}}_{\mathrm{loss} }{=\mathrm{P}}_{\mathrm{c}}{+\mathrm{P}}_{\mathrm{s}}$$

(14)

The Foster thermal model was compiled in the PLECS environment. Figure 6 and Figure 7, respectively, denote the thermal description of the IGBT module IKW20N60H3 implemented. Heat sinks with reduced thermal resistances are not added. To simulate a worst-case scenario, the junction-to-ambient thermal resistance of the IGBT module itself is implemented for analysis. Following the thermal model, the ${\mathsf{\pi }}_{\mathrm{R}}$ and ${\mathsf{\pi }}_{\mathrm{T}}$ values are obtained.

4.2. Reliability Evaluation

The different failure rate parameters, and hence the failure rates of the various switches, are computed and are described in

Table 3. Device failure rate parameters.

Switches	Junction Temp. (°C)	ΠT	Power Loss (W)	ΠR	Vs	ΠS	λs
S1/S2	248.73	20.82	5.33	1.85	0.41	0.21	λ1 = 0.00421
S3/S4	190.852	12.63	3. 90	1.65	0.33	0.16	λ2 = 0.00172
S5/S6	230	18.01	4.90	1.80	0.08	0.11	λ3 = 0.00184
S7	119.272	5.50	3.39	1.57	0.16	0.11	λ4 = 0.000492

. The reliability function of the inverter under any switch open-circuit faults is evaluated using the following result:

$$\begin{gathered} \mathrm{R}(\mathrm{t}){=(\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}}{)}^2{{(\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }4\mathrm{t}})}^2+2({1-\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}}){{(\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }4})}^2+2(1{-\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}}){{(\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }4\mathrm{t}})}^2+ \\ 2({1-\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}}){{(\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }4\mathrm{t}})}^2+(1-{\mathrm{e}}^{-\mathsf{\lambda }4\mathrm{t}}{)(\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}}{)}^2{{(\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}})}^2 \end{gathered}$$

(15)

The first term in the expression is for the healthy operation of the topology. The second term is for the case of post-fault in either of S1/S2. The third term of the equation represents conditions after a fault in S₃/S₄. Similarly, the third term of the equation represents a fault in one of S₅/S₆. The equation’s fourth term represents a fault in S₇. In a situation where there is no fault management, the reliability of the inverter is substantially suppressed, as predictable by Equation (16).

$$\mathrm{R}(\mathrm{t}){=(\mathrm{e}}^{-\mathsf{\lambda }1\mathrm{t}}{)}^2{{(\mathrm{e}}^{-\mathsf{\lambda }2\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }3\mathrm{t}})}^2{{(\mathrm{e}}^{-\mathsf{\lambda }4\mathrm{t}})}^2$$

(16)

The distinction of reliability between fault management and its lack thereof can be visualized in Figure 8.

5. Comparative Analysis

In this section, the proposed topology is assessed competitively concerning fault-tolerant MLIs mentioned the in recent literature. Multiple parameters for assessment include the number of DC sources, power semiconductor switches, and levels generated. The comparison can be visualized using Table 4. The proposed topology shows advantages in terms of per-unit level device utilization and component requirements with the additional benefit of improved reliability. The literature works compared with the proposed topology include [16,17,18,37,38,39,40,41]. While the DC source requirement in [18,39] are same as the proposed topology, still they can produce only seven level output voltage. The topologies presented in [17,38,40,41] utilizes two DC sources, but they can only produce a maximum level of 5, 5, 7, and 9 respctively. Moreover, although the switch requirement in [17,37,38,39,40] is less compared to proposed topology, the ouptut voltage levels generated are also quite a bit lower. Comparison with a CHB topology with DC sources ±V_dc, ±2V_dc, ±2V_dc is also included. The CHB topology exhibits only partial fault tolerance in terms of post-fault peak level availability and reduced performance in case of faults in multiple switches while requiring 12 active IGBTs compared to 8, as in the case of the proposed topology. Consider a three-CHB with DC sources ±Vdc, ±2V_dc, ±2V_dc. The proposed topology can continue to produce a five-level output of 0, ±2V_dc, ±4V_dc in the event of both S₁-S₂, both S₅-S₆, and even all four S₁, S₂, S₅, and S₆ simultaneous failure by employing the redundant switches S₈ and S₉, while the loss of four switches will catastrophically affect the performance of the CHB inverter. Moreover, only eight IGBTs are active in the proposed topology during healthy conditions, and the other four are redundant, which results in higher reliability than the three-CHB inverter comprising 12 active IGBTs.

Table 4. Comparative assessment.

Topology	No. of Dc Sources	No. of Capacitors	No. of Power Diodes	No. of Switches	Fault Tolerant/Reliable	No. of Levels
Binary CHB (1-2-2)	3	0	0	12	YES (partial)	11
[16]	4	0	0	20	YES	5
[17]	2	0	2	8	YES	5
[37]	1	2	2	8	YES	5
[38]	2	0	0	8	YES	5
[18]	3	0	0	12	YES	7
[39]	3	0	0	10	YES	7
[40]	2	2	0	9	YES	7
[41]	2	1	0	12	YES	9
Proposed	3	0	0	12	YES	11

Table 4. Comparative assessment.

Topology	No. of Dc Sources	No. of Capacitors	No. of Power Diodes	No. of Switches	Fault Tolerant/Reliable	No. of Levels
Binary CHB (1-2-2)	3	0	0	12	YES (partial)	11
[16]	4	0	0	20	YES	5
[17]	2	0	2	8	YES	5
[37]	1	2	2	8	YES	5
[38]	2	0	0	8	YES	5
[18]	3	0	0	12	YES	7
[39]	3	0	0	10	YES	7
[40]	2	2	0	9	YES	7
[41]	2	1	0	12	YES	9
Proposed	3	0	0	12	YES	11

6. Fault Detection

The proposed fault detection technique involves the acquisition of the mean load voltage and Root Mean Square (RMS) load voltage supplied by the MLI. The detection problem is a Multiclass Classification problem in machine learning, with fault location as the output and mean and RMS voltages as inputs. Various supervised learning classification algorithms have been developed, namely expert systems, linear regression, artificial neural networks (ANNs), a support vector machine (SVM), k-nearest neighbour (KNN), fuzzy logic, and decision trees (DTs). This work implements a decision tree model for the classification problem. DTs are one of the most versatile and popular models which can perform both classification and regression. A decision tree is in the structure of a tree, where each feature is represented as a node. A decision rule is represented as a branch (link), and each leaf classifies the output. The structure of a DT is depicted in Figure 9. The basic principle involves asking a series of true/false questions or decisions. Data are further categorized across every step. Each branch corresponds to a result of the test. Each leaf node assigns a classification of the output. DTs often mimic the human thinking flow, making them simple to understand and they help one in interpreting the implications of the data. The three steps performed are dataset preparation, training, and testing.

Assuming training vectors $x_i\in R^n,i=1,\dots l$ with a label vector $y\in R^l$, the functioning of a decision tree involves recursively partitioning the features such that identically labelled or similar target outputs are aggregated together. Consider the data composed of N_m samples at node m and symbolised by Q_m. A split $\theta =(j,t_m)$ with j and t_m as the feature and partition, respectively, partitions the data into the subsets $Q_m^{left}(\theta$) and $Q_m^{right}(\theta$).

$$Q_m^{left}\left(\theta \right)=\left\{\left(\mathrm{x},\mathrm{y}\right)\right|x_j\le t_m\}$$

(17)

$$Q_m^{right}\left(\theta \right)=Q_m/Q_m^{left}\left(\theta \right)$$

(18)

The obtained candidate split is verified by its quality using a loss function H(),

$$G\left(Q_m,\theta \right)=\frac{N_m^{left}}{N_m}H(Q_m^{left}\left(\theta \right))+\frac{N_m^{right}}{N_m}H(Q_m^{right}\left(\theta \right))$$

(19)

The impurity minimisation is performed by the following parameter:

$${\theta }^{*}=argmi{n}_{\theta }G\left(Q_{m,\theta }\right)$$

(20)

Recursion is performed for the subsets $Q_m^{left}\left({\theta }^{*}\right)$ and $Q_m^{right}\left({\theta }^{*}\right)$ until the maximum allowable depth is achieved that is $N_m<mi{n}_{samples}$ or $N_m=1$. For a classification application implementing 0…(K − 1) outputs for node m, assume that the proportions of class k outputs in node m given by

$$p_{mk}=1/N_m{\displaystyle \sum }_{y\in Q_m}I\left(y=k\right)$$

(21)

Then, the loss function corresponding to the Gini classification index is given by

$$H\left(Q_m\right){\displaystyle \sum }_k{p}_{km}\left(1-p_{mk}\right)$$

(22)

6.1. Dataset Preparation

The mean and RMS values are acquired and are used as input to the model. Multiple inputs are obtained by varying the DC source voltages by 0%, ±1%, ±2%, ±5%, and ±10% to account for variations in load and dynamic behavior. Moreover, the above procedure is repeated for modulation indexes of 1, 0.9, 0.8, 0.7, 0.6, and 0.5. Distinct values across these parameters are obtained for fault in all seven switches and healthy operation. This gives a total of 432 input datasets, of which 75% are used for training the model. Selected sample datasets are displayed in

Table 5. Sample dataset features.

Mean Load Voltage	RMS Load Voltage	Fault in Switch
−45.20	79.29	1
66.56	116.11	2
6.014	122.00	3
−4.72	87.69	4
16.65	108.49	5
−13.75	99.34	6
−0.00014	137.92	7
−3 $\times$ 10−6	−3 $\times$ 10−6	0 (NO Fault)

for S₃ fault conditions. A plot of the total dataset obtained is shown in Figure 10. Classification 1 to 7 is used for respective faults in switches, with ‘0′ for no fault.

6.2. Training

The training was implemented on a Colab^TM computational environment using the Python Scikit-learn library. Gini index classification was used as a metric. The importance of the features can be visualized in Figure 11. Observably, the mean voltage is a more important feature than the RMS values. The obtained decision tree structure is shown in Figure 12. The tree has 39 nodes and 38 branches with eight leaf nodes determining the fault location as the output.

6.3. Testing and Results

After training, testing was carried out to verify the performance of the prediction model. The Confusion matrix obtained post-training is given as:

$$\left[\begin{array}{cccccccc}13& 0& 0& 0& 0& 0& 0& 0\\ 0& 11& 0& 0& 0& 0& 0& 0\\ 0& 0& 12& 0& 0& 0& 0& 0\\ 0& 0& 1& 8& 0& 0& 0& 0\\ 0& 0& 0& 0& 16& 0& 0& 0\\ 0& 0& 0& 0& 0& 15& 0& 0\\ 0& 0& 0& 0& 0& 0& 16& 0\\ 0& 0& 0& 0& 0& 0& 0& 15\end{array}\right]$$

(23)

The diagonal values are the correct predictions, and the non-diagonal elements are false positives and false negatives. As a result, the testing accuracy as a ratio of the number of correct predictions and total predictions was approximately 98.14%. An error of 1.86% is within satisfactory ranges for load and modulation index variation. Thus, the model can predict open-circuit fault locations with acceptable accuracy and low computational and hardware requirements.

The trained classification model was implemented in the MATLAB-Simulink environment for fault detection on the inverter model. The obtained simulation results are given in Figure 13. The simulation results indicate that the fault is detected within one fundamental period.

The method can also be expanded for multiple switch faults. The advantages of the given method include the requirement of only two measured signals, mean and RMS voltage, from the inverter, thus requiring minimal additional sensor and signal processing hardware requirements. Thus, the proposed method can work with minimal cost and complexity.

7. Results and Discussion

7.1. Simulation Results

The operation of the proposed topology was verified in the MATLAB-Simulink^TM R2016b environment on an Intel^® Core^TM i5-3210M 2.50 GHz platform. The simulation parameters are listed in

Table 6. Simulation and reliability model parameters.

IGBT-diode module	IGB20N60H3
Dc source voltages V1, V2	50 V, 100 V
Load	20 Ω, 40 mH
Power	960 W
Modulation	NLC
Fundamental Frequency	50 Hz
Heat sink added	NO
Initial temperature and ambient	298 K

. Results under both normal and faulty operation are presented with the execution of the NLC-PWM modulation control. The load voltage and load current waveform and their respective harmonic profiles are given in Figure 14. The load voltage, load current, and the switch current waveforms in the scenario of S₁/S₂ or S₅/S₆ fault are shown in Figure 15. Similarly, the corresponding waveforms for faults in S₃/S₄ and S₇ are shown in Figure 16 and Figure 17, respectively.

7.2. Experimental Verification

The operation of the proposed topology was verified through a hardware prototype depicted in Figure 18 using NLC (nearest level control) at 50 Hz fundamental frequency with

Table 7. Experimental parameters.

IGBT-diode module	IGB20N60H3
Dc source voltages V1, V2	10 V, 20 V
Load	20 Ω, 50 mH
Power	125 W
Modulation	NLC
Fundamental Frequency	50 Hz
Controller	TMS320F28335
Gate Drivers	TLP250H

parameters. IGBTs IGB20N60H3 were used as switches. TMS320F28335 was used as the controller while TLP250H gate drivers were implemented. The output waveforms were displayed in a Yokogawa DL1640 oscilloscope. A total input DC source voltage of 50 V with V₁ = 10 V and V₂ = 20 V was fed to the module. An EN50160 power analyzer was used to determine the harmonic distortion in the load voltage waveforms. A load of 20 Ω + 50 mH was connected at the output. The output waveforms for S₁ open-circuit fault for modulation indexes MI = 1 and MI = 0.7 are given in Figure 19. Similarly, the output waveforms for S₃ fault and S₇ fault are given in Figure 20 and Figure 21, respectively. The fault-tolerant operation was successful, even with the variation of MI. Moreover, the waveform distortion arising from the open-circuit fault was corrected in one fundamental period. The harmonic spectrum of load voltages for healthy conditions, S₁ post- fault, S₃ post-fault, and S₇ post-fault, are given in Figure 22. Observably, the THD is higher post-fault but is at acceptable values and can be supplied to critical loads with low filter requirements.

8. Conclusions

In this paper, an asymmetric multilevel inverter topology is introduced. The fault tolerance of the proposed topology against switch open-circuit faults due to gating failure is verified through simulation results. Reliability analysis of the topology is presented to illustrate the advantage of fault tolerance. The topology is compared against previous works in terms of device count and other parameters to demonstrate its superiority. Additionally, a fault detection strategy using the supervised machine learning technique decision trees is put forth. The fault localization model inputs the load mean voltage and its RMS as diagnostic variables and outputs the fault location. The testing results demonstrate that the classification model successfully detects the fault location with an accuracy of 0.981481. Therefore, the fault detection strategy can be expanded to a real-time system in the future with low computational requirements and minimal additional hardware.