Realization of a Generalized Switched-Capacitor Multilevel Inverter Topology with Less Switch Requirement

Abstract

Conventional multilevel inverter topologies like neutral point clamped (NPC), flying capacitor (FC), and cascade H bridge (CHB) are employed in the industry but require a large number of switches and passive and active components for the generation of a higher number of voltage levels. Consequently, the cost and complexity of the inverter increases. In this work, the basic unit of a switched capacitor topology was generalized utilizing a cascaded H-bridge structure for realizing a switched-capacitor multilevel inverter (SCMLI). The proposed generalized MLI can generate a significant number of output voltage levels with a lower number of components. The operation of symmetric and asymmetric configurations was shown with 13 and 31 level output voltage generation, respectively. Self-capacitor voltage balancing and boosting capability are the key features of the proposed SCMLI structure. The nearest level control modulation scheme was employed for controlling and regulating the output voltage. Based on the longest discharging time, the optimum value of capacitance was also calculated. A generalized formula for the generation of higher voltage levels was also derived. The proposed model was simulated in the MATLAB^®/Simulink 2016a environment. Simulation results were validated with the hardware implementation.

1. Introduction

Conversion of power from DC to AC or AC to DC is a key technology involved in the generation, transmission, distribution, and utilization of electrical energy. With the advent of fast and high rating power electronics devices, digital controllers, and sensors the power converter industry is seeing a revolution. Inverters form the backbone of drives and grid integration applications. They can be classified based on the nature of the output waveform, such as square wave inverter, quasi square wave inverter, two-level pulse width modulated inverters, and multilevel inverter [1,2]. Although the realization of conventional two-level inverters is simple, it has many shortcomings. High total harmonic distortion (THD) with the requirement of higher blocking voltage rating devices and the better design of filters for improving the power quality restrict their application to a small power range. To overcome the shortcomings of the conventional two-level inverter, a multilevel inverter was proposed [3,4,5]. Multilevel inverters are composed of semiconductor switches and DC power supplies/capacitive voltage sources. A multiple-step voltage waveform with variable and controllable frequency, phase, and amplitude are obtained by suitable connection and control of the switches using a modulation scheme [6]. Because of the inherent superior harmonic profile and less voltage stress across switches, MLI has replaced a two-level counterpart for high power applications. MLIs find wide usage in motor drive applications [7]. Neutral point clamped (NPC), flying capacitor (FC), and cascade H bridge (CHB) are the conventional MLI topologies. Separate DC voltage sources are required for the generation of multistep voltage in a CHB. CHB has a modular structure and can be more easily extended to achieve higher voltage levels. FC requires a complex control mechanism to ensure that the voltage across the capacitor is maintained constant. Therefore, conventional MLI is not suitable for voltage levels beyond five [8]. A large number of modified/hybrid conventional topologies that were proposed required a large number of power semiconductor switches for the generation of higher voltage levels [9]. Each switch requires a separate driver circuit and heat sink. Consequently, size and complexity increase. To avoid these issues, authors in [10,11,12,13,14] presented reduced device count topologies of MLI. Although a higher number of voltage levels are generated with a smaller number of device counts, they do not possess the voltage boosting capability. This boosting feature is available in the switched capacitor multilevel inverter (SCMLI) in which the capacitor acts as a voltage source, which was introduced by authors of [15] in 1998. They obtained a 31-level output voltage with the help of two sub-circuits. Each sub-circuit contained 15 basic cells. One basic cell consisted of two diodes, two MOSFETs, and one capacitor. The topology requires a complex control algorithm for balancing the capacitor voltage. Authors of [16,17] introduced reduced device count MLI topologies having a capacitor, but the capacitor voltage balancing issue remained. This problem was overcome by adding an auxiliary circuit reported in [18,19]. However, it increased the overall cost and complexity of the system. In [20], authors developed a novel switched capacitor-multilevel inverter known as a Marx inverter. It is capable of synthesizing the different output voltage levels and also maintaining the capacitor voltage at the desired level. Seven level output voltage is obtained with the help of ten switches. By cascading SC cells (consist of switches and capacitors), higher voltage levels can be achieved. In [21] authors proposed a new basic unit having two switches, one diode, and one capacitor. The topology has self-boosting capability without any transformer. Seventeen and twenty-five level output voltage with experimental results were reported. Since the boosting factor of this basic unit is two times of DC supply voltage, therefore for the generation of a higher number of voltage levels, cascading of basic units is needed. However, the cascading will increase the complexity and total standing voltage (TSV) of the circuit. Authors in [22] presented a switched capacitor multilevel inverter; this circuit can generate higher number of voltage levels with fewer switches in asymmetric configuration, but the TSV of the structure is significant. By the simultaneous charging and discharging of capacitors, authors in [23] obtained multilevel output voltage. However, it requires a large number of bidirectional switches and it also increases the TSV of the circuit significantly. In [24], authors introduced a novel structure of the switched-capacitor multilevel inverter. Its basic unit generates nine level output voltage with the help of ten switches, two capacitors, one diode, and one DC supply. The extended structure of this switch capacitor multilevel inverter was also discussed for symmetric and asymmetric DC supply configurations. However, the structure again suffers from a high TSV level for a higher voltage level. Authors in [25] proposed a new basic unit cell where the boosting factor is three times the DC supply voltage with the help of five semiconductor switches, two capacitors, and one diode. The structure promises to be a competitive topology for SCMLI.

In this paper, a generalized topology taking the basic unit of [25] is proposed. The paper is organized into eight sections. In Section 1, the working of the basic unit is explained. Section 2 deals with a symmetric DC supply configuration and its modes of operation. Further, in Section 3, Section 4 and Section 5, an asymmetric DC supply configuration, selection procedure of capacitance, and an extension of the proposed topology are discussed, while Section 6 deals with comparative analysis of the proposed generalized scheme. Section 7 presents simulation and hardware results, and the paper is concluded in Section 8. The nearest level control modulation scheme (NLC), which comes under the fundamental switching frequency scheme [26], is employed for controlling the switches.

2. Basic Unit

The basic unit cell of the switched-capacitor multilevel inverter is shown in Figure 1. It is comprised of one voltage source, one diode, two capacitors, and five IGBT (Insulated-gate bipolar transistor) semiconductor switching devices. A DC voltage supply is connected between capacitor legs L₁ and L₂. Switches ($S_1$, $S_2$) in capacitor leg L₁ and ($S_3, S_4$) in capacitor leg L₂ are complementary to each other. Charging leg CH1 is realized by a power switch along with a power diode. This leg starts conducting when capacitor $C_1$ or $C_2$ is charging.

Table 1. Switching states and capacitor mode.

S1	S2	S3	S4	SCHI	C1	C2	Level
OFF	ON	OFF	ON	OFF	NC	NC	V
OFF	ON	ON	OFF	ON	C	D	2V
ON	OFF	OFF	ON	ON	D	C	2V
ON	OFF	ON	OFF	OFF	D	D	3V

shows the switching scheme of the basic unit; 1 stands for the switch-on condition, and 0 stands for the switch-off condition. D, C, and NC stand for discharging, charging, and not connected states of capacitors, respectively.

The basic unit acts as a boost converter that can generate V, 2V, and 3V voltage levels, which is shown with the help of Figure 2. The output voltage is taken between points A and N. The conducting path for each level generation is indicated by red color. For obtaining +V voltage between the point A and N, switch S₂ and S₄ are in the on condition, and capacitors C₁ and C₂ both are not connected, i.e., both the capacitors are neither in the charging nor in the discharging state. Figure 2 shows an equivalent circuit diagram of this voltage level generation. There are two ways for generating the +2V voltage level at the output between A and N, as shown in Table 1.

As shown in Figure 2b, it is necessary that capacitor C₂ is charged up to DC source voltage. Therefore, by closing the switches S₂ and S₃, capacitor C₂ discharges and is connected in series with the supply voltage to produce a 2 V voltage level. Simultaneously, capacitors C₁ is charged up to supply voltage V by providing a path from S₂, SCH₁, and S₃. Further, as shown in Figure 2c, by switching ON of S₁ and S₄, capacitor C₁ discharges and is connected in series with the supply voltage. At the same time, with the help of switch SCH₁, S₁, S₄, and the power diode, capacitor C₂ charges up to the supply voltage. It is to be noted that the charging leg comes into the picture when either capacitor C₁ or C₂ is in the charging state. For the sake of better understanding, charging states of capacitors are represented by a blue color. For generating +3 V at the output switch, pair S₁, S₃ is in the ON condition, and both the capacitors discharge and are connected in series with the supply voltage, as shown in Figure 2d.

3. Symmetric Configuration

3.1. Circuit Diagram

Figure 3 shows the circuit diagram of 13 level SCMLI. The switching table of this configuration is given by

Table 2. Switching states of the proposed symmetrical 13 level SCMLI.

S1	S3	SCH1	T1	T3	S5	S7	SCH2	T5	T7	Level	C1	C2	C3	C4
0	0	0	1	1	0	0	0	1	1	0V	NC	NC	NC	NC
0	0	0	1	0	0	0	0	0	0	V	NC	NC	NC	NC
0	0	0	1	0	0	0	0	1	0	2V	NC	NC	NC	NC
0	1	1	1	0	0	0	0	1	0	3V	C	D	NC	NC
1	0	1	1	0	0	1	1	1	0	4V	D	C	C	D
1	1	0	1	0	1	0	1	1	0	5V	NC	NC	D	C
1	1	0	1	0	1	1	0	1	0	6V	D	D	D	D
0	0	0	0	1	0	0	0	1	1	−V	NC	NC	NC	NC
0	0	0	0	1	0	0	0	0	1	−2V	NC	NC	NC	NC
0	1	1	0	1	0	0	0	0	1	−3V	C	D	NC	NC
1	0	1	0	1	0	1	1	0	1	−4V	D	C	C	D
1	1	0	0	1	1	0	1	0	1	−5V	NC	NC	D	C
1	1	0	0	1	1	1	0	0	1	−6V	D	D	D	D

. It consists of two H-bridges and two basic units. For each basic unit, a DC voltage supply of equal rating is used. The two H-bridges are cascaded with the load. IGBT acts as a switch for this circuit. Each capacitor of the basic unit is charged up to the DC supply voltage. Since each basic unit generates three voltage levels, therefore 13 level output voltage can be achieved by this configuration.

3.2. Modes of Operation

There are 13 modes of operation related to this configuration arrangement. The positive modes (including 0V) are described here with reference to Figure 4.

• Mode 0

As shown in Figure 4a, the amplitude of the output voltage across the load is zero. It can be achieved by switching ON T₁, T₃, T₅, and T₇. Switches S₂, S₄, S₆, and S₈ are also ON, but these switches do not play any role in generating the zero voltage level at the output

• Mode 1

In this mode, the amplitude of the output voltage across the load is equal to V. This voltage level is produced by switching ON the transistors S₂, S₄, T₂, T₄, S₆, S₈, T₆, and T₈, as shown in Figure 4b

• Mode 2

In this mode, the voltage developed across the output is 2V. Here, each basic unit (upper and the lower) generate V voltage levels. This is shown in Figure 4c. Switches S₂, S₄, S₆, S₈, T₁, T₄, T₅, and T₈ are ON for the generation of this voltage level

• Mode 3

In this mode, the voltage developed across the output is 3V.

The upper basic unit generates a 2V voltage level, while the lower basic unit produces the V voltage level. This is to be obtained by switching on the transistor S₂, S₃, S₆, S₈, T₁, T₄, T₅, and T₈. Capacitor C₁ is in charge up to the V voltage level, which is indicated by blue color. Figure 4d shows the circuit arrangement for the generation of this voltage level.

• Mode 4

In this mode, the voltage developed across the output is 4V. Both the basic units generate 2V. Capacitor C₂ and C₃ are charging while C₁ and C₂ are discharging. Switches S₁, S₄, S₆, S₇, T₁, T₄, T₅, and T₈ are ON for this sinewave. Figure 4e shows the conduction for the generation of this voltage level.

• Mode 5

In this mode, the voltage developed across the output is 5V. The contribution of the upper and lower unit is 3V and 2V, respectively. Capacitors C₁, C₂, and C₃ are in the discharging state, while capacitor C₄ is in the charge state up to the DC source voltage because it comes in parallel with DC supply voltage. Switches S₁, S₃, S₅, S₈, T₁, T₄, T₅, and T₈ are ON for this mode, as shown in Figure 4f.

• Mode 6

In this mode, the voltage developed across the output is 6V. All the capacitors are discharged and connected in series with DC source voltage and the load. Both the units generate 3V, and the output is the summation of these two voltage levels. Switches S₁, S₃, S₅, S₇, T₁, T₄, T₅, and T₈ are ON for this mode, as shown in Figure 4g.

4. Asymmetric Configuration

In the asymmetric configuration, the voltage of the DC supply in the lower basic unit is four times higher than the upper basic unit, for maximum level generation. The upper basic unit generates V, 2V, and 3V voltage levels, while the lower basic unit generates 4V, 8V, and 12V voltage levels. Maximum voltage stress across each switch in the upper basic unit and H bridge is V and 3V volt, while for the lower basic unit, it is 4V and 12V. Therefore, in the lower basic unit, higher ratings of switches are required.

4.1. Modes of Operation

There are 31 voltage levels, out of which only positive voltage levels are shown in Figure 5. For the generation of V, 2V, and 3V, only switches of the upper basic unit play a role.

Table 3. Switching for the generation of 31 voltage level.

Modes	Conducting Switches	Capacitor States				Upper Basic Unit	Lower Basic Unit	Voltage LeVel
		C1	C2	C3	C4
1	S2,S4,S6,S8,T1,T3,T5,T7	NC	NC	NC	NC	0V	0V	0V
2	S2,S4,S6,S8,T1,T4,T6,T8	NC	NC	NC	NC	V	0V	V
3	S2,S3,S6,S8,SCH1,T1,T4,T6,T8	C	D	NC	NC	2V	0V	2V
4	S1,S3,S6,S8,T1,T4,T6,T8	D	D	NC	NC	3V	0V	3V
5	S2,S4,S6,S8,T1,T3,T5,T8	NC	NC	NC	NC	0V	4V	4V
6	S2,S4,S6,S8,T1,T4,T5,T8	NC	NC	NC	NC	V	4V	5V
7	S1,S4,S6,S8,SCH1,T1,T4,T5,T8	D	C	NC	NC	2V	4V	6V
8	S1,S3,S6,S8,T1,T4,T5,T8	D	D	NC	NC	3V	4V	7V
9	S2,S4,S6,S7,SCH2,T1,T3,T5,T8	NC	NC	C	D	0V	8V	8V
10	S2,S4,S5,S8,SCH2,T1,T4,T5,T8	NC	NC	D	C	V	8V	9V
11	S2,S3,S6,S7,SCH1,SCH2,T1,T4,T5,T8	C	D	C	D	2V	8V	10V
12	S1,S3,S5,S8,SCH2,T1,T4,T5,T8	D	D	D	C	3V	8V	11V
13	S2,S4,S5,S7,T1,T3,T5,T8	NC	NC	D	D	0V	12V	12V
14	S2,S4,S5,S7,T1,T4,T5,T8	NC	NC	D	D	V	12V	13V
15	S1,S4,S5,S7,SCH1,T1,T4,T5,T8	D	C	D	D	2V	12V	14V
16	S1,S3,S5,S7, T1,T4,T5,T8	D	D	D	D	3V	12V	15V
17	S2,S4,S6,S8,T2,T3,T5,T7	NC	NC	NC	NC	V	0V	−V
18	S2,S3,S6,S8,SCH1,T2,T3,T5,T7	C	NC	NC	NC	2V	0V	−2V
19	S1,S3,S6,S8,T2,T3,T5,T7	D	D	NC	NC	3V	0V	−3V
20	S2,S4,S6,S8,T2,T4,T6,T7	NC	NC	NC	NC	0V	4V	−4V
21	S2,S4,S6,S8,T2,T3,T6,T7	NC	NC	NC	NC	V	4V	−5V
22	S1,S4,S6,S8,SCH1,T2,T3,T6,T7	D	C	NC	NC	2V	4V	−6V
23	S1,S3,S6,S8,T2,T3,T6,T7	D	D	NC	NC	3V	4V	−7V
24	S2,S4,S6,S7,SCH2,T2,T4,T6,T7	NC	NC	C	D	0V	8V	−8V
25	S2,S4,S5,S8,SCH2,T2,T3,T6,T7	NC	NC	D	C	V	8V	−9V
26	S2,S3,S6,S7,SCH1,SCH2,T2,T3,T6,T7	C	D	C	D	2V	8V	−10V
27	S1,S3,S5,S8,SCH2,T2,T3,T6,T7	D	D	D	C	3V	8V	−11V
28	S2,S4,S5,S7,T2,T4,T6,T7	NC	NC	D	D	0V	12V	−12V
29	S2,S4,S5,S7,T2,T3,T6,T7	NC	NC	D	D	V	12V	−13V
30	S1,S4,S5,S7,SCH1,T2,T3,T6,T7	D	C	D	D	2V	12V	−14V
31	S1,S3,S5,S7,T2,T3,T6,T7	D	D	D	D	3V	12V	−15V

gives information about the generation of the voltage level and conducting states of switches and capacitors for all positive modes. For the generation of a negative voltage level (−V, −2V, etc.) the same switches are ON in both upper and lower basic units, just like the generation of V, 2V, while complementary switches of H bridges are ON. In both symmetric as well as asymmetric configurations, basic units behave as a level generator, while the cascaded H bridge acts as a polarity generator.

4.2. Calculation of Capacitance

This section giVes the procedure for the selection of a suitable Value of capacitance. It is done by eValuating the longest discharging time (LDT) of each capacitor. Based on the switching state, which is shown in Table 3, the longest discharging time for different capacitors is shown in Figure 6.

It is to be noted that during the LDT, the capacitor discharges the maximum amount. The amount of discharging charge depends upon the load current and LDT duration. From Figure 6, it can be concluded that the discharging duration of capacitor C₃ is larger as compared to other capacitors. Mathematically, the amount of discharging of the switched capacitor C₃ can be expressed by the following equation:

$$Q_{C_3}=2\times {{\displaystyle \int }}_{t_{11}}^{\frac{T}{4}}{i}_o\left(t\right)dt$$

(1)

Similarly, for C₁, C₂, and C₄,

$$Q_{C_1}=2\times {{\displaystyle \int }}_{t_{14}}^{\raisebox{1ex}{$T$}\!\left/ \!\raisebox{-1ex}{$4$}\right.}{i}_0\left(t\right)dt$$

(2)

$$Q_{C_2}=2\times {{\displaystyle \int }}_{t_{15}}^{\raisebox{1ex}{$T$}\!\left/ \!\raisebox{-1ex}{$4$}\right.}{i}_0\left(t\right)dt$$

(3)

$$Q_{C_4}=2\times {{\displaystyle \int }}_{t_{12}}^{\raisebox{1ex}{$T$}\!\left/ \!\raisebox{-1ex}{$4$}\right.}{i}_0\left(t\right)dt$$

(4)

Now the optimum Value of capacitance is expressed by

$$C_{opt}\ge \frac{Q_{C_1}or{Q}_{C_2}or Q_{C_3}or Q_{C_4}}{\rho \times V_{dc}}$$

(5)

where $\rho$ signifies the ripple in capacitor Voltage from the maximum allowable capacitor Voltage and where Q denotes electric charges.

Now for a resistiVe load condition, the load current during the longest discharging time (LDT) can be expressed by the following equation:

$$i_0\left(t\right)=\frac{11V_{dc}}{R_L} \mathrm{for} t_{11}\le t\le t_{12}$$

(6)

For the fundamental switching frequency scheme, the time $t_{11}$can be calculated using the following steps:

Let $\Delta t$ be a small Value. By adding and subtracting this small Value of $\Delta t$ in $t_{11}$ with these two Value, the following are obtained:

$$V_m\sin \mathsf{\omega }\left(t_{11}-\Delta t\right)=10$$

(7)

$$V_m\sin \mathsf{\omega }\left(t_{11}+\Delta t\right)=11$$

(8)

Adding Equations (7) and (8) and after manipulating by trigonometric identities, we get

$$2V_m\sin \left(\omega t_{11}\right)=21$$

(9)

Since the maximum Value of the sine waVe is 1, therefore,

$$t_{11}=\frac{{\sin }^{-1}\left(\raisebox{1ex}{$21$}\!\left/ \!\raisebox{-1ex}{$30$}\right.\right)}{2\pi f}$$

(10)

Using Equations (1), (5), (6) and (10), the optimum Value of capacitance for the resistiVe load can be expressed by the following equation:

$$C_{opt}\ge \frac{17.55}{2\pi \times f\times \rho \times R_L}$$

(11)

Referring to Equation (11), the optimum Value of the capacitor is inVersely proportional to the load resistance, output frequency, and the percentage of Voltage Ripple. The corresponding Figure 7 shows the Variation of capacitor Value with load resistance for different percentage of Voltage Ripple ($\rho$).

For a resistive-inductiVe load condition, the load current during LDT can be expressed by the following equation:

$$i_0\left(t\right)=I_{0max}\sin \left(2\pi f-\phi \right)$$

(12)

The optimum Value of capacitance for C₃ can be calculated by solVing Equation (13) using Equations (1), (10), and (12).

$$C_{3,\left(opt\right)}\ge \frac{2I_{0max}}{\omega \rho V_{dc}}\left[\cos \left(0.7753-\phi \right)-\sin \phi \right]$$

(13)

Figure 8 is obtained for $I_{0max}=3A,V_{dc}=72V,$and $f=50$Hz, which shows the Variation of optimal capacitance for different Values of phase angle (between R and L) $\phi$ and the percentage of Voltage Ripple$\rho$.

Similarly,

$$C_{1,\left(opt\right)}\ge \frac{2I_{0max}}{\omega \rho V_{dc}}\left[\cos \left(1.1197-\phi \right)-\sin \phi \right]$$

(14)

$$C_{2,\left(opt\right)}\ge \frac{2I_{0max}}{\omega \rho V_{dc}}\left[\cos \left(1.3116-\phi \right)-\sin \phi \right]$$

(15)

$$C_{4,\left(opt\right)}\ge \frac{2I_{0max}}{\omega \rho V_{dc}}\left[\cos \left(0.8758-\phi \right)-\sin \phi \right]$$

(16)

5. Extension of Proposed Scheme

For the generation of the higher number of Voltage leVels with reduce deVice count and for improVing the harmonic profile of multileVel inVerter extension of MLI, a topology is carried out in this section. It is done by adding capacitor legs in each side of the DC source; these legs are called charging legs. Figure 9 shows the structure of the proposed scheme for symmetric configuration up to the m = 4 stage or charging leg. The proposed topology is also applicable to asymmetric configuration. It is to be mentioned that the selection of the DC Voltage source in the lower basic unit cell is dependent on the Voltage leVels generated by the upper basic unit. For example, when charging leg m = 2, the basic unit acts as a Voltage source which generates a 3V Voltage leVel; therefore, with the turning on of switches (S_10,2), (S₁₁,₂), and (S_CH3,2), capacitor C_5,2 is charged up to the 3V Voltage leVel. Similarly, capacitor C_6,2 is charged up to the 3V Voltage leVel by proViding a current flow path by switching on (S_9,2), (S_11,2), and (S_CH3,2). When both the capacitors are connected in series with the DC source, nine Voltage leVels are obtained across the output. Hence the boosting factor of the basic unit is increasing in the order of 3^m. The lower basic unit obtains the same Voltage leVel (9V). Therefore, the Voltage rating of the DC Voltage source of a lower basic unit cell is 10 times larger than the upper unit cell of the Voltage source in case of asymmetric configurations. By connecting the extensiVe structure of an upper basic unit to the point (a2 and a’,2) and a lower unit to (b2 and b’,2), 37 leVel (symmetric) and 199 leVel (asymmetric) output Voltage is obtained across the load. For m = 3, 109 of output Voltage leVel can be obtained by symmetrical configuration. This is possible by connecting the upper basic to the point (a,3 and a’,3) and lower unit to (b,3 and b’,3).

The following equations giVe a generalized formula for both symmetric and asymmetric configuration in terms of charging legs or stages (m). SeVeral diodes, switches, capacitors, and Voltage sources are the same for both the configurations.

Number of leVel (N_L) = (4.3^m + 1) (for symmetric configuration)

= (3^m + (3^m + 1)3^m) × 2 + 1(asymmetric configuration)

(17)

Number of diodes (N_D) = 2m

(18)

Number of switches (N_S = 10m + 8

(19)

Number of gate driVers (N_G) = 10m + 8

(20)

Number of capacitors (N_C) = 4m

(21)

The current rating of the switches in a multileVel inVerter is equal to the rated load current. HoweVer, this is not true for the Voltage rating of switches; it affects the total cost of the inVerter. Therefore, for eValuating the multileVel inVerter topology from the Viewpoint of blocked Voltage by power switches and the total cost of the system, standing Voltage criteria are defined, which are equal to the sum of all blocked Voltages by power switches in a conVerter. In the symmetric configuration, the total standing Voltage of the basic unit and H bridge is 5V and 12V, respectiVely. This topology consists of two H bridges and basic units. Hence the total standing Voltage of this topology is 34 and 5.66 (in terms of per unit). The following formula giVes the generalized formula for TSV:

$$\mathrm{TSV}=2.\left(5\right){{\displaystyle \sum }}_{m=1}^n{3}^{m-1}+ 3^m.\left(8\right)$$

(22)

$$\mathrm{TSV} \left(\mathrm{pu}\right)=\frac{TSV}{{4.3}^m/2})$$

(23)

Similarly, for asymmetric configuration, the generalized formula of TSV is giVen by the following equation:

$$5.{{\displaystyle \sum }}_{m=1}^n{3}^{m-1}+5.\left(3^m+1\right){\displaystyle \sum }_{m=1}^n{3}^{m-1}+{4.3}^m+{4.3}^m\left(3^m+1\right)$$

(24)

$$\mathrm{TSV} \left(\mathrm{pu}\right)= \frac{TSV}{ \left(3^m+3^m\left(3^m+1\right)\right)}$$

(25)

With the help of Equation (17), the relation between circuit components and the number of leVels can be achieVed.

Since

$$N_L=4 \left(3^m\right)+1,$$

$$\frac{N_L-1}{4}=3^m$$

Taking log on both sides,

$$m={\log }_3\left(\frac{N_L-1}{4}\right)$$

Now the no. of capacitors, diodes, and switches can be written as

$$N_c=4 {\log }_3\left(\frac{N_L-1}{4}\right)$$

(26)

$$N_D=2 {\log }_3\left(\frac{N_L-1}{4}\right)$$

(27)

$$N_S=8+10 {\log }_3\left(\frac{N_L-1}{4}\right)$$

(28)

Similarly, the relation between circuit components and the number of leVels for asymmetric configuration are giVen by the following equations:

$${\mathrm{N}}_{\mathrm{C}}=4 {\log }_3\left[-1+\sqrt{\frac{N_L+1}{2}}\right]$$

(29)

$${\mathrm{N}}_{\mathrm{D}}=2 {\log }_3\left[-1+\sqrt{\frac{N_L+1}{2}}\right]$$

(30)

$$N_S=8+10 {\log }_3\left[-1+\sqrt{\frac{N_L+1}{2}}\right]$$

(31)

6. Comparison of Proposed with Other Existing SCMLI Topology

Table 4. Comparison of proposed topology with other symmetric SCMLI.

SCMLI Presented In	NL	Ndc	NS	NC	TSV
[27]	13	3	18	3	5
[28] (m = 1)	17	4	20	4	5
(m = 2)	33	4	32	8	6
[29]	13	2	14	4	5.3
[24]	17	2	18	4	5
[25]	13	2	16	4	5.6
Proposed (m = 1)	13	2	18	4	5.66
(m = 2)	37	2	28	8	5.66

shows the comparison of some existing SCMLIs and proposed topology in terms of deVice counts. The proposed topology was better as compared to topology proposed by the authors in [4,5] concerning the number of DC sources. Although authors [6] obtained seVenteen leVels by using 18 switches, they required some bidirectional switches. The topology presented in [7] is comparable with the proposed topology in terms of capacitors, diodes, and TSV for the generation of 13 leVels of the output Voltage, and 37 leVels (when m = 2) of the output Voltage were obtained by extending the structure of the proposed scheme. It exhibited better results in terms of deVice count and TSV as compared to the topology (m = 2) presented in [5]. From

Table 5. Comparison of proposed with other asymmetric SCMLI.

SCMLI Presented In	NL	Ndc	NS	NC	TSV
[28]	49	2	16	4	6.25
[29]	31	2	14	4	5.33
[24]	49	2	18	4	6
[25]	31	2	16	4	5.67
Proposed (m = 1)	31	2	18	4	5.66
(m = 2)	199	2	28	8	5.66

, it can be concluded that the proposed structure with asymmetric DC sources was not significantly beneficial as compared to suggested topologies for producing lower output Voltage leVels. HoweVer, it required a smaller number of deVices for the generation of higher Voltage leVels. A generalized formula for finding the number of switches and capacitors with the number of leVels is shown in

Table 6. Comparison with other extended. Structure of SCMLI.

Topologies	NL	NS	NC
CHB	2m + 1	4m	0
[30]	6m + 1	10m	3m
[31]	4m + 1	6m	2m
[32]	2m + 1	5m − 1	m − 1
[33]	2m + 3	m + 5	m
[28]	4m − 1	6m − 2	2m − 1
Proposed symmetric	4(3m) + 1	10m + 8	4m
Proposed asymmetric	2(3m + (3m + 1)3m) + 1	10m + 8	4m

. Here m represents the stage. All the topologies discussed in table are modular in structure. Therefore, extension of these topologies is possible for achieVing a higher number of Voltage leVel. Figure 10 shows the relation between the number of leVels and stages; it can be concluded that the proposed topology (both symmetric and asymmetric) is better than the others. Additionally, fewer capacitors and switches are required for the generation of higher Voltage leVels, as can be seen in Figure 11 and Figure 12. Therefore, the proposed topology is far better than other topologies for the generation of higher Voltage leVels with a smaller number of deVice counts.

7. Simulation and Hardware Results

The proposed topology (symmetric as well as asymmetric configuration) was simulated and hardware results were also presented. For the simulation, MATLAB 2016 was used. A TMS320F28335 digital signal processor was used for the generation of switching pulses for IGBT switches. The driVer circuit was deVeloped using TLP 250.

Table 7. Parameters used in simulation and hardware.

Parameters/Components	Attributes
Two DC Voltage supply	12 V each for symmetric, 7.5 and 30 V for asymmetric configuration
Fundamental frequency	50 Hz
Switching frequency	50 Hz
Four electrolytic capacitors	4700 µf, 50 V
Two power diode	10 A
Eighteen IGBT Switches	1200 V, 25 A
Load	250 Ω

shows the parameters used in both simulations as well as in hardware. Figure 13a–h shows the gating signals of switches of the 13 leVel switched capacitor multileVel inVerter. Since switches (T₂,T₄,T₆,T₈,S₂,S₄,S₆,S₈) are complementary switches to switches (T₁,T₃,T₅,T₇,S₁,S₃,S_5,S₇), therefore, states of these switches were always opposite to the corresponding complementary switches. Figure 14i, j shows the output Voltage and current of the 13 leVel inVerter for the resistiVe load condition. To represent the output current on the same graph, the amplitude of the current was multiplied by a hundred times of the actual Value of current. The peak Values of Voltage and current were 72 Volts and 0.288 A, respectiVely. Figure 14k–n shows the Voltage across capacitor C₁ to C₄. The maximum Voltage across each capacitor was 12 Volts, and the Variation in the capacitor Voltage (ripple Voltage) with respect to time was less than 10% obserVed in simulation results. The Voltage stress across each switch of the basic unit was V Volts and across each switch of cascaded H-bridge was 3V Volts. Figure 14o,p shows the Voltages across switches S₁ and T₁.

Some of the switching pulses (simulation and hardware) of 31 leVel switch capacitor multileVel inVerters are depicted in Figure 15a–d. The peak amplitude of output Voltage of 112.5 Volts was obserVed in simulations, and almost similar results were obtained in hardware, as shown in Figure 15e,f. Voltage stress across capacitor C₁ was more as compared to C₂ and C₃. The simulated capacitor Voltages are shown in Figure 15g, and the experimental result is shown in Figure 15h. Figure 16 indicates the THD in the output Voltage for both symmetric (13 leVels) and asymmetric (31 leVels) SCMLI, namely 6.36% and 2.36% THD in output Voltage in 31 leVels and 31 leVels SCMLI, respectiVely. This THD Value is satisfied with the IEEE-519 2014 THD leVel standard.

8. Conclusions

In this paper, a boost switched-capacitor multileVel inVerter is proposed, which is the combination of a switched-capacitor cell and a cascaded H-bridge module. The capacitor in the switched capacitor cell behaVes as a DC source, and when they are connected in series with the DC source Voltage, the maximum output Voltage leVel is obtained. Using the nearest leVel modulation scheme, 13 leVels of symmetric and 31 leVels of asymmetric or output Voltage were achieVed. Determination of the rating of capacitance in terms of the longest discharging time for R and R-L load were also deriVed. MoreoVer, for achieVing a higher number of Voltage leVels, an extended structure of the proposed scheme was presented. The required number of deVice counts in terms of the number of stages for the higher number of Voltage generation was also deriVed. A comparatiVe analysis with other switched capacitor multileVel inVerters was also presented. Output Voltage THD was also analyzed and it satisfied the IEEE 519-1992 THD standard. Finally, the effectiVeness of the proposed scheme’s seVeral simulation and hardware results was presented.