A Modified High Voltage Gain Quasi-Impedance Source Coupled Inductor Multilevel Inverter for Photovoltaic Application

Abstract

The quasi-impedance source inverters/quasi-Z source inverters (Q-ZSIs) have shown improvement to overwhelmed shortcomings of regular voltage-source inverters (VSIs) and current-source inverters (CSIs) in terms of efficiency and buck-boost type operations. The Q-ZSIs encapsulated several significant merits against conventional ZSIs, i.e., realized buck/boost, inversion and power conditioning in a single power stage with improved reliability. The conventional inverters have two major problems; voltage harmonics and boosting capability, which make it impossible to prefer for renewable generation and general-purpose applications such as drive acceleration. This work has proposed a Q-ZSI with five-level six switches coupled inverter. The proposed Q-ZSI has the merits of operation, reduced passive components, higher voltage boosting capability and high efficiency. The modified space vector pulse width modulation (PWM) developed to achieve the desired control on the impedance network and inverter switching states. The proposed PWM integrates the boosting and regular inverter switching state within one sampling period. The PWM has merits such as reduction of coupled inductor size, total harmonic reduction with enhancing of the fundamental voltage profile. In comparison with other multilevel inverters (MLI), it utilizes only half of the power switch and a lower modulation index to attain higher voltage gain. The proposed inverter dealt with photovoltaic (PV) system for the stand-alone load. The proposed boost inverter topology, operating performance and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for the stand-alone and grid-connected system.

1. Introduction

Photovoltaic (PV) energy, extracted through solar cells is a mandatory power generation technology to meet out the global power demand [1]. The most prominent merits in PV generation are reduction of fossil fuel usage, less impact on the environment and reduction in power generation cost [2,3]. The large-scale deviation occurs in the floating power generations that abide by climatic conditions. Unfortunately, the main drawback of the PV array panels is a wide range of drop-in voltage. However, the power electronics devices overcome the voltage drops and floating power generation [4]. The power electronics converter and inverter combinations make PV power transfer an efficient process. The traditional power electronics inverters; voltage-source inverter (VSI), and current-source inverter (CSI) defeats options in the PV power generation with the addition of DC-DC converters. This two-stage power conversion needs more semiconductor switches and passive components; hence they may cause the abrupt disturbance on voltage profile [5]. To prevail over the demerits of traditional inverters, single-stage power conversion is introduce named as Z (impedance) source inverter (ZSI). Impedance networks offer an effective power transformation between the source (input) and an extensive range of loads with high efficiency. However, the ZSI lags in the performance like producing discontinuous nature in the input current; inductors do not withstand high current, and voltage stress on the capacitors [6]. The quasi-Z source has been expected to inherit the merits of the ZSI with reduced passive components, continuous input current, constant DC rail voltage for the inverter, and so on. Before embarking on the investigation of the Z source inverter, it is helpful to look into its evolution. Impedance source topology-based researches have proliferated, from the time it was proposed by Peng et al. in 2003; the variety of alterations and novel Z-source topologies has matured exponentially [7]. In the advancement of ZSI, it finds variety of applications such as; variable-speed electrical drives [8,9], uninterruptible power supply [10], in distributed power generations (such as photovoltaic (PV), fuel cell, and wind, etc.), energy storage system (such as battery and supercapacitor), and electric vehicles [11,12,13]. An earned mark of the Z-source inverter has lost its capability in the form of the input and output voltage ratio profile, switching stress and utilization of higher modulation. These lagging structure needs to be remarked with a quasi (Q)-Z source. The development in the Q-Z source with coupled inductor achieves most compromising effect towards upright of power quality, lower switching dv/dt, better electromagnetic influence, and negligible switching losses [14].

Owing to the advantages and challenges, power electronics researchers have given much interest in impedance-source topology development. The first Z-source was proposed during 2003 (Peng et al.); the variety of alterations, as well as novel topological inventions that have been developed exponentially, are chosen based on the applications and requirements. Concerning power conversion, it is separated into four groups: AC to DC (rectifier), AC to AC (AC voltage regulator), DC to DC (DC chopper), and DC to AC (inverter). This classification is further divided into two-level (conventional VSI) and multi-level DC to AC, AC to AC matrix converters [15] and DC to DC converters in isolated and non-isolated arrangement [16]. Based on the input source (current or voltage), the impedance source topology is further divided into the voltage source and current source Z-source [17]. Besides, considering the impedance components (inductors arrangements), this group can be distributed into coupled inductor (magnetically coupled) or transformer-based [18] and non-transformer (non-magnetically coupled) based [19]. There are selected limitations present in non-magnetically coupled topologies such as lower modulation proportion and lesser, output gain. Therefore, non-transformer topology needs higher boosting inductor and DC-link voltage rating, which may increase the converter switching stress superfluously. Besides, the circuit cost and size for these converters are undesirable. To minimize these concerns, the uses of magnetically coupled inductors or transformers are attractive to increase the operating range and output voltage gain concurrently. The Q-ZSIs proposed in [19,20] offer additional improvement of traditional X shape network topology. Besides the rewards inherited from X shape ZSIs, Q-ZSIs also has its own merits such as continuous current mode operation, reduction of component selection ratings, structured with common DC-rail in the middle of the input and inverter. There are modified Q-ZSI topologies comprehensibly investigated within their improvement to provide continuous input current [21]. Yang et al. propose the current-fed Q-ZSI., including the benefits of the combined buck-boost operation, enhanced reliability, reduced component ratings, as well as single-stage regeneration capability. This topology provides consistency with the input current control and performs better than Q-ZSI.

In the current era, the interests of multilevel inverters (MLIs) have increased than the conventional VSIs, due to their merits [22]. Particularly the development of power semiconductor technology makes it easy to tradeoff the selection of power devices. New MLIs have been recommended in a hybrid approach by involving MOSFETs, IGCTs or GTOs and IGBTs [23,24,25,26,27]. Recently, the interleaved converter topology using coupled-inductors is proposed and extensively applied in low-power claims. These topologies are mostly used to increase the output current with lesser current ripple.

Additionally, the interleaved converter reduces the size of passive components (inductors and capacitors), and the output voltage harmonic profile is considerably increased [28,29,30,31,32,33,34,35,36,37,38,39]. Banaei et al. discussed the switching stress reduction in Z source-based MLI [36]. Alexandre Battiston et al. deliberated the withdrawal of the ripples in the input current with the suitable coupled inductors arrangement [37]. Li et al. proposed the use of the cascading magnetic cells to obtain a high voltage gain [38] and investigated the voltage gain achievement against smaller duty time. Followed by the authors, Lei et al. offered optimized pulse width modulation (PWM) technique with reduction of switching loss, current ripple, low total harmonic distortion (THD) and high boost gain [39]. The space vector PWM is extensively reviewed for impendence sourced VSIs and MLIs [40,41,42,43,44,45,46,47,48,49]. The creation of shoot-through (ST) and placing them in the active switching states, these PWM methods perform better than other carrier-based PWM methods. The ZSI space vector PWM is also studied with two-level MLIs for altering the active and ST switching vector in the space vector diagram for the enhancement of inverter output [44]. However, when connecting a coupled inverter with an impedance network, the PWM methods need to be modified.

Based on this technical background and coupled MLI and control scheme requirements of ZSI, this paper suggests a single-phase MLI coupled inverter topology with five-level output for PV application. This PV tied five-level coupled inverter topology is connecting the modified Q-ZSI with a six-switch coupled inverter, making a single stage DC to AC conversion topology. The proposed Q-ZSI has the merits of operation, namely reduced passive components, voltage boosting capability and high efficiency. The modified space vector PWM is proposed to realize the desired control in impedance network shoot-through and regular inverter switching state to make five-level output. The proposed PWM is integrating the boosting and regular inverter switching state within one sampling period. The PWM has the merits like a reduction of coupled inductor size and triplen harmonic reduction with the enhancement of the fundamental voltage profile.

In comparison with other MLIs, it utilizes only half of the power switch, lower modulation index to obtain high voltage gain. The proposed inverter is simulated and experimentally validated for single phase induction motor load with off-grid fashion. Nevertheless, the proposed inverter topology is a suitable version for both off-grid and on-grid applications.

The paper flow is organized in this way. Section 2 deals with the review of traditional Z-source inverter. The proposed modified Q-impedance converter fed coupled inductor multilevel inverter is explained in Section 3. The modified Space Vector PWM concept and control methods of the proposed inverter are shown in Section 4, Section 5, Section 6 and Section 7 explain the simulation and experimentation, respectively. The conclusion is given in Section 8.

2. Review of Traditional Z-source Inverter

2.1. Review of X-Z Source Topology

Figure 1 illustrates the general impedance-source configuration with the impedance-source network for VSI. The basic Z-source network structure is generalized as a necessary X shaped two-port network using two L and C (linear energy storage elements) (Peng et al. 2003). Perhaps designing different Z-source network configurations to expand the converter performance, non-linear elements (switches, diodes, or/and combination of both) is added in the shape two-port network (Peng et al. 2003).

According to Figure 2, the impedance-source network has two modes of work. During the mode-1, inverter switch is short-circuited to provide the charging loop for an inductor with input DC source. This state is called the ‘shoot-through (ST) state’. The second mode is the active mode, where energy stored in the inductors is supplied the load via inverter active mode switching. To connect this ST state with regular inverter active switch, there are a variety of modulation methods available. The modulation methods are distributing the ST states equally based on the modulation index of the inverter (M_a). The upper limit of the modulation index is 1-D_S. For the maximum boost modulation method, the modulation index is operated in extensive range (M_a ≥ 1); however, the state involves larger (high rating), passive (L and C) elements [8], and correspondingly distributing the active states, the M_a has its maximum M_a ≤ 1–D_S [14]. Therefore, V_C1 = V_C2 = V_PL. During this time, high-frequency generation in the active states causes higher frequency ripples, as shown in Figure 2a. According to the characteristics of Z-source inverter boost mode operation, the performance of inductor and capacitor components and DC-link voltage estimation related to input voltage function are shown in Figure 2b. From the characteristics curve, it is understood that the inverter matches the maximum DC-link voltage with the least input voltage. The inductor curve has a challenging dependency with ST time, and the quick capacitance value raise with the decreasing input voltage is essential. Hence, it is noted that passive elements (inductor and capacitor) are carefully chosen based on the input source voltage and power profile. The voltage rating capacitors are required since the voltage across the capacitors is always greater than the input voltage. Similarly, starting current and voltage surge happens because of the enormous inrush input current. Due to the resonance conditions, these surges are not avoidable, and the absence of bidirectional and soft-start capability limits the application for conventional Z-source topology.

To get improvement in the conventional ZSIs, Q-ZSIs are significantly improved to make use of single-stage power conversions. Considering the circuit operations and boosting, characterizes Q-ZSIs as having similar belongings with conventional ZSIs. Figure 3 illustrates the boost-mode characteristics of ZSIs. The Q-ZSIs differ from the conventional X shape-ZSIs by providing continuous input current through lower capacitor C₂ [10]. Regardless of the control strategy of Q-ZSIs, during ST states, the duty ratio is limited concerning inductor rating directly. Hence, there is a possibility of continuous conduction with reduced input inductor current ripples. Besides, Q-ZSI provides the cross conduction switching states to provide the boosting by mutual sharing of inverter switching (top and bottom), which improves the inverter reliability [11]. The Q-ZSI has advantages of reduced component (L and C) ratings, lower switching stress, and continuous current mode operation. The standard ground-sharing option in the Q-ZSI is an additional feature, which is high indeed for PV modules [19]. Even though Q-ZSI has several advantages over conventional X-shape ZSI; it has low DC-link utilization in constant boost operation. To overcome this weakness, Q-ZSIs modified with additional passive components have been proposed [19,20].

2.2. Different Advanced Z-Source Topologies

Due to the advantages and challenges, power electronics researchers have given much interest in impedance-source topology development. These topologies are categorized into two ways; 1. Transformer based and 2. Without transformer (non-magnetically coupled). Figure 4a–f shows the basic different impedance source topologies.

Selected limitations are present in non-magnetically coupled topologies such as low modulation ratio and lesser input-to-output gain. Therefore, this topology needs higher DC-link voltage, which may increase the semiconductors stress needlessly. Besides, the circuit cost and size for these converters are undesirable. Even though the magnetically coupled converters are attractive for their boosting performance, due to the higher DC ripple, the inverter suffers from high harmonics. The disadvantages of magnetically coupled topologies are; (1) raising the shoot-through and magnetizing current while switching; (2) the tightly coupled transformer leads to low leakage impedance; and (3) the need for the snubber circuit is mandatory when the coupling is not fulfilled. Hence, non-magnetic type converters are not highly preferred for PV fed applications [6]. Considering the non-magnetic type converters group, X-shape and Q- impedance converters offer low passive components rating, less duty cycle conversion ratio, and direct conversion. However, it has the poor performance to maintain the input current, reverse blocking capability for the switch, buck-boost operation, absence of bidirectional conversion and direct current control ability. Hence, the paper proposes a coupled inverter connected modified Q-impedance converter to provide single conversion mode power flow operation with multi-level output.

3. Proposed Modified Q- Impedance Converter Fed Coupled Inductor Multilevel Inverter.

The traditional Z source inverters can only allow unidirectional power conversion flow with boosting operation. Nevertheless, the proposed topology is different from the conventional Z source inverter or Q-ZSI family to exchange the diode for bi-directional power flow; the proposed Q-ZSI achieve the boosting capability with single-stage conversion associated with the inverter switching scheme as shown in Figure 5. The first suggestion of a proposed modified Q-impedance network is to obtain the continuous input current is controlled possibility. It consists of the three operating states; (1) active state, (2) shoot-through state, and (3) open-zero states. When related to the conventional X-Z/Q-Z topology, the proposed structure streams the minimum DC voltage on capacitor C₂ as well as deliver continuous input current [11,19]. Acknowledging straightforwardness in the control strategy for the proposed quasi-Z-source MLI functions with two operating modes; (1) shoot-through (ST) and, (2) non-shoot-through (NST). In ST mode, among all inverter phase leg, only one leg is conducting for providing ST. In NST mode, all the three leg switches in the inverter are forming the switching states to make a level in MLI. Hence, the inverter is working similar to a standard inverter. The current Z-source inverter switching states are premeditated with two zero states, and six active states. Figure 6 shows the Proposed modified Q-impedance network. The proposed inverter possesses the two open-zero, six active, and one shoot-through states.

State-1: Figure 7a shows the active states of the inverter. This mode assumes inductors, L₁ and L₂ and capacitors, C₁ and C₂ with chosen identical values as V_C1 = V_C2 = V_C, V_L1 = V_L2 = V_L to maintain a symmetrical output nature. The Kirchhoff’s voltage law is applied in Figure 7a,

$$V_{C1}+V_{L1}=V_{C2}+V_{L2}=V_{PV}+V_{Ls}=V_{ab}$$

(1)

Considering the steady-state average voltage of the inductors in one switching event must be zero. $V_{L1}=V_{L2}=V_{Ls}=V_L=\frac{1}{T}{{\displaystyle \int }}_0^T{V}_L\left(t\right)dt$ = 0. From Equation (1), the steady-state voltage average of inductors is zero at one single switching period. Hence,

$$V_{C1}=V_{C2}=V_C=V_{PV}$$

(2)

State-2: In this shoot-through state, when any inverter leg is shorted, the PV array voltage is zero, and the diode is off. Thus, the inverter output voltage is zero due to short circuit as shown in Figure 7b, from the equivalent circuit of Figure 7b the KCL equation is given below,

$$V_{C1}=V_{C2}=V_C=V_{PV}=0$$

(3)

State-3: This is considered to be an open-zero state, where the inverter is switching legs act as an open circuit, and therefore the added capacitor voltages (V_C1 and V_C2) appear across the V_ab. Now, the inductor (L₁ and L₂) currents flow through diode D₁ to charge the capacitors (C₁ and C₂) as exposed in Figure 7c.

From the circuit operation of the proposed inverter, the total switching period is classified as T_A (active state switching time), T_sh (shoot-through state switching time), and T_op (open-zero state switching time) within one switching cycle, T_A+T_sh+T_op =1. Considering any of the three inductors voltage, V_L in different states; state-1: V_L= V_in-V_out, state-2: V_L= V_in, state-3: V_L= V_in−2V_C.

Since, $V_L=\frac{1}{T}{{\displaystyle \int }}_0^T{V}_L\left(t\right)dt$ = 0

$$V_L=T_A\left(V_{in}-V_{out}\right)+T_{sh}{V}_{in}-T_{op}{V}_{in}=0$$

(4)

$$V_{boost}=\frac{\left(T_A+T_{sh}-T_{op}\right)}{T_A}{V}_{PV}$$

(5)

From T_A+T_sh = 1 − T_op

Hence,

$$V_{boost}=\frac{\left(1-2T_{op}\right)}{T_A}{V}_{PV}$$

(6)

The converter DC output voltage boosting (V_boost) has two control degrees of choice (T_A and T_sh). Figure 8a shows the graphical understanding between V_boost and input voltage (V_PV) concerning duty cycle D_A. Here, the operation is split into two modes as (1) Mode-1: without open-zero states, and (2) Mode-2: towards short-zero states to open-zero states.

In mode 1 the T_op = 0 output voltage depends on the parameter T_A = 1 − (T_op+T_sh). The entire range of the operation depends on the T_A active state switching time. The controlling of the parameter T_A decides the boosting capability of the MLI.

In Mode-2, the converter is in shoot-through states, where T_op = 1 − T_A. Hence the converter provides minimum voltage gain with a specified duty ratio of T_A. When converter operation moves from shoot-through states to the open-zero states, the output gain would be situated in the middle of the Mode-1 and Mode-2. The marked red area in Figure 8a shows the mode shift of the converter. Therefore, the converter voltage output can be adjusted to the desired values with two control degrees of freedom T_op and T_A. Figure 8b shows the radar graph of energy storage capability on C, L, diode voltage stress and switch voltage stress in boost mode for conventional QZ and proposed QZ. It shows the proposed QZ have better energy storage capability and lesser diode and switching voltage stress than conventional QZ.

4. Modes of Operation of Coupled Inductor MLI

The proposed coupled inductor MLI contains a structure having six switches in three legs (u, v and w). The leg v and leg w are connected with identical turns coupled inductor (L_M1 and L_M2). The ST operation is done through any leg. If the leg u is used for ST, then the switch S₁ and S₂ are turned ON simultaneously. Since the ST is allowed in any of the MLI legs, the switching reliability is significantly improved. During the Non-ST (active state), the MLI is functioning with either one upper switch and two-lower switches/two-upper switches, and one-lower switch. Hence, during the active state, the inverter is operating with eight modes of operation to produce five-level voltages (−V_dc,−V_dc/2, 0, V_dc/2, and V_dc).

During the regular inverter operating conditions, the boosted voltage is appearing across the inverter and provides pure DC current. For the period of the ST time, the inductor is maintaining its voltage precisely equal to capacitor voltage V_C and hence current increases through the inductors leniently and limits the inductor current ripples. The eight modes of operation and their corresponding equivalent circuits of the proposed coupled inductor connected MLI is illustrated in Figure 9.

It is a single-phase circuit with two legs associated with coupled circuits. The quasi fed MLI provides V_pv + V_S as input voltage to the coupled inductors (L_M1 and L_M2). The mutual inductance (M) of the coupled inductors provides the five-level voltage output with a reduction of the switching devices. The level making of the inverter is done through the L_M1 and L_M2 with the identical sum. The inductor L_M1 = L_M2 = L is connected between leg v and w. The voltage equation can be expressed as,

$$L\frac{d{i}_v}{dt}-M\frac{d{i}_w}{dt}=V_{in}-V_{bn}$$

(7)

$$L\frac{d{i}_w}{dt}-M\frac{d{i}_v}{dt}=V_{wn}-V_{bn}$$

(8)

where, V_in = input voltage, V_bn = load voltage, and V_wn = w leg voltage

Applying current law of Kirchhoff’s’, the leg current can be written as,

$$i_u+i_v+i_w=0$$

(9)

Hence,

$$V_{bn}=\frac{V_{vn}+V_{wn}+\left(L-M\right)\frac{d{i}_u}{dt}}{2}$$

(10)

The inverter leakage inductance L_M1 and L_M2 are designed approximately equal to the mutual inductance value; hence leakage inductance equals mutual inductance (L = M). Therefore, the voltage equation on V_bn can be written as,

$$V_{bn}=\frac{V_{vn}+V_{wn}}{2}$$

(11)

The voltage output of the inverter can be delivered as,

$$V_{ab}=V_{an}-V_{bn}=V_{an}-\left(\frac{V_{vn}+V_{wn}}{2}\right)$$

(12)

$$V_{ab}=\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=0$$

(13)

The different modes of operation of active inverter switching for level making are explained as follows;

Mode-1: During Mode-1, the inverter switches S₁, S₄, and S₆ are turned ON, and S₂, S₃, and S₅ are turned OFF (see Figure 10). Hence, from Equation (12) the load voltage is derived as, $V_{ab}=\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=V_{dc.}$

Mode-2: During Mode-2, the inverter switches S₁, S₄, and S₅ are turned ON, and S₂, S₃, and S₆ are turned OFF (see Figure 11). Hence, the inverter produces half of the V_dc (Vs = inverter input voltage). From Equation (12) the load voltage is derived as, $V_{ab}=\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=\frac{V_{dc}}{2}.$

Mode-3: During the Mode-3, the inverter switches S₁, S₃, and S₆ are turned ON, and S₂, S₄, and S₅ are turned OFF (see Figure 12). Hence, the inverter produces half of the V_dc. From Equation (12) the load voltage is derived as, $V_{ab}=\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=\frac{V_{dc}}{2}.$

Mode-4: During Mode-4 the inverter switches S₁, S₃, and S₅ (all upper switch) is turned ON, and S₂, S₄, and S₆ (all lower switch) are turn OFF showing in Figure 13. Hence, the inverter produces zero output voltage. From Equation (12) the load voltage is derived as, $V_{ab}=\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=0$.

Mode-5: During Mode-5 the inverter switches S₂, S₄, and S₆ (all lower switch) are turned ON, and S₁, S₃, and S₃ (all upper switch) are turned OFF as shown in Figure 14. Hence, the inverter produces zero output voltage. From Equation (12) the load voltage is derived as, $V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=0$.

Mode-6: During Mode-6, the inverter switches S₂, S₄, and S₅ are turned ON, and S₁, S₃, and S₆ are turned OFF (see Figure 15). Hence, the inverter produces half of the V_dc. From Equation (12) the load voltage is derived as, $V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=-\frac{V_{dc}}{2}.$

Mode-7: During Mode-7, the inverter switches S₂, S₃, and S₆ are turned ON, and S₁, S₄, and S₅ are turned OFF (see Figure 16). Hence, the inverter produces half of the V_dc. From the Equation.12 the load voltage is derived as, $V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=-\frac{V_{dc}}{2}.$

Mode-8: During Mode-8, the inverter switches S₂, S₃, and S₅ are turned ON, and S₁, S₄, and S₆ are turned OFF (see Figure 17). Hence, the inverter produces full of the V_dc in negative. From Equation (12) the load voltage is derived as, $V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=-V_{dc}.$

Table 1. Switching table for the proposed topology.

Mode	Conducting Switches	Output
1	S1, S4, S6	$V_{ab}=\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=V_{dc}$
2	S1, S4, S5	$V_{ab}=\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=\frac{V_{dc}}{2}$
3	S1, S3, S6	$V_{ab}=\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=\frac{V_{dc}}{2}$
4	S1, S3, S5	$V_{ab}=\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=0$
5	S2, S4, S6	$V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=0$
6	S2, S4, S5	$V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(-\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=-\frac{V_{dc}}{2}$
7	S2, S3, S6	$V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}-\frac{V_{ab}}{2}\right)}{2}=-\frac{V_{dc}}{2}$
8	S2, S3, S5	$V_{ab}=-\frac{V_{ab}}{2}-\frac{\left(+\frac{V_{ab}}{2}+\frac{V_{ab}}{2}\right)}{2}=-V_{dc}$

shows the consolidation of the eight modes of operations of the inverter. Of these eight modes, six modes are producing the voltage in different forms between +V_dc to −V_dc. The Mode-4 and Mode-5 are producing the zero voltages, and hence, any one of the modes can be used for zero voltage. Figure 18 illustrates the all mode operation output voltage structure for proposed MLI.

5. Modified Space Vector PWM

The Space Vector PWM is a continuous switching PWM technique, which explicitly selects the active and zero states placed within the carrier period [30]. While designing for the boost converter circuitry, the vector-based algorithm possesses the additional switching states which must be imposed to acquire a higher voltage gain in the traditional impedance source inverters. It may lead to impact the switches in the form of stress or failure of a switch [8]. While looking into the traditional strategy, the upper and lower switch combination must be short as the voltage gain may impose distortion on voltage. The proposed space vectors consist of normalized state operation, which generates the voltage gain by operating u, v, w legs upper or lower switches, as shown in Figure 10. The condition ST is incorporated with the regular zero vector operation. The projected control algorithm realizes the least number of switching operations to improve the efficiency of an inverter over one switching cycle, as indicated in Figure 18. The operation time for each period and every switching cycle of the dead time for short-zero as well as open-zero states, should be pre-calculated. The six modes (Mode-1 to Mode-6) of switching states are aligned with active vector and Mode-4, and Mode-5 are placed in zero vector.

In a three-phase balanced system, the voltage equation of Space Vector PWM is predefined as,

$$V_{ref}{T}_s=V_1{T}_1+V_2{T}_2+V_0\frac{T_0}{2}$$

(14)

Here, V_ref is a reference vector (target vector), From Figure 19b in the sector-1, vector V_ref can be synthesized as,

$$V_{ref}=V_1\frac{T_1}{T_s}+V_2\frac{T_2}{T_s}+V_0\frac{T_0}{2T_s}$$

(15)

The V₁ and V₂ are the adjustment operating vectors at T₁ and T₂. The T_s is a switching period, and T₀ is zero vector time. The pulse period of the active vector is calculated from the below equation when operating in a given switching period T_s.

$$T_1=\frac{2}{\sqrt{3}}+\left|V\right|\sin \left(\frac{2\pi }{3}-\theta \right)T_s$$

(16)

$$T_2=\frac{2}{\sqrt{3}}\left|V\right|\sin \left(\theta -\frac{\pi }{3}\right)T_s$$

(17)

Hence, the zero-vector time:

$$T_0=T_s-T_1-T_2=\left(1-\frac{2}{\sqrt{3}}\left|V\right|\sin \left(\theta \right)T_s\right)$$

(18)

The proposed Space Vector PWM strategy is selecting the voltage vector switching sequence, according to V_ref. The V_ref is the reference vector of output V_ab. Hence, the output voltage of the inverter is selected by using switch S₁. According to Table 1, when S1 is turned ON, the inverter output voltage V_ab is either in positive voltage or zero. Hence the relation is framed between S₁ and V_ab, for the smooth implementation.

When S₁ is turned ON, the V_ab ≥ 0 and S₁ is low, consequently V_ab ≤ 0. Nevertheless, the other switching states should be appropriately combined with S₁ to make the desired voltage level of the inverter. In order to select the stable switching states, the dwell time (T_d) of the switch is calculated in every switching frequency T_s sampling period. The dwell time concerning inverter DC-link voltage V_in is defined as:

$$T_d=\frac{\left|V_{ref}\right|-k{V}_{in}}{V_{in}}$$

(19)

Here, the V_ref is related to the sampling period T_s. The ST duty ratio for inverter must be predefined for every switching cycle by adding the ST time within the T_S. Figure 19a shows the dwell time control of inverter, and it is related to T_S (= 1/f_S), and V_in.

To locate the selected switching vector for the V_ref, a new method of vector identification is proposed. The strategy is to locate the V_ref value and to find out the different switching states in the space vector diagram (SVD) hexagon (see Figure 20). Hence the control strategy is designed in two steps: (1) locate the real and imaginary equivalent of V_ref, and (2) find out the control vector within the sector.

Figure 19b represents the proposed control strategy in which, from the V_ref slope, the real and imaginary equivalent of V_x and V_y are determined and compared with the targeted switching vector V₁ and V₁’. Here, when the condition is V_y < a V_x + b, then V₁ is selected. Else V₁’ is selected. Once this targeting vector is selected, the T_d is calculated and then active switching time, ST time and zero switching time is calculated according to the inverter output voltage requirement. Figure 20 represents the overall SVD for the proposed control strategy. Here, the entire active targeted vector is placed inside the SVD sector until the hexagonal boundary. The zero vectors [1, 1, 1] and [0, 0, 0] are placed at the origin. The control switching vector is directly related to the inverter modulation index (m_a), where V_in and V_ref are related to the inverter output. The maximum inverter control in the linear modulation range is allowed only until $\frac{2}{\sqrt{3}}$ V_in [23]. The switching pulse patent of the proposed PWM is prearranged in Figure 21. Once the active and zero states are done, the ST state patent is included in the switching sampling period. The ST state is calculated based on the V_PV value. Figure 22 represents the inverter switching pulse. The zero-state sharing ST state and ST time is calculated directly from the following equations:

$$T_{sh}=\frac{\left(\left|V_{ab}\right|-B{V}_{PV}\right)}{V_{PV}}$$

(20)

$$B=\frac{\left|V_{ab}\right|}{V_{PV}}$$

(21)

where B is a boosting factor.

6. Simulation Result

The PV powered Q-impedance network connected coupled inductor multilevel inverter and its control switching schemes strategy is designed in MATLAB/Simulink software simulation platform (Figure 23). The inverter is powered by 500 Watts peak power PV. The PV module is arranged to get 100 to 120 V to meet the 330 V DC-link voltage of the inverter. The insulation level of the PV array is 1000 W/m² for 10 s, 800 W/m² from 10 s to 30 s. The temperature of the PV array is 400°C for 10 s and 300 °C from 10 s onwards. The variation in PV array power input can be overcome by the Perturb and Observe the MPPT algorithm to obtain the constant DC voltage from the PV array.

Table 2. Simulation Parameters.

Input PV Voltage, VPV	100 V–120 V
Impedance Network Inductor Ls = L2 = L3	2 mH
Impedance network inductor capacitors C1 = C2	200 µF
Switching frequency, fs	10 KHz
Inverter coupled inductor LM1 = LM2	5 mH
Mutual inductance	2.4 mH
Load resistance and inductance	10Ω, 5 mH
LC filter: inductance and capacitor	2.5 mH,50 µF

shows the simulation parameter for the proposed inverter. The inverter performance is investigated with and without LC filters.

In order to validate the inverter performance simulation is carried out when the PV input power is kept at 500 W and the input PV voltage, V_PV is maintained at 120 V. The impedance network duty ratio (T_A and T_ST) is maintained at 20% to 25% to preserve the inverter input (DC-link) voltage 250 to 350 V. The inverter operation is investigated with their modulation index range m_a = 0 to 0.866. The simulation study is carried out for different impedance network duty ratio T_ST and inverter modulation index range m_a. Initially, the inverter is operated with a maximum modulation index of 0.886 with the ST switching time T_ST of 25%. Figure 24 shows the PWM pulse of inverter switches S₁ and S_6. The ST time between switch S₁ and S₂ is represented in Figure 25, in which the 25% switching time is used for ST event, and hence impedance network can boost input PV voltage nearly 290% and achieved 349 V in the output side of the impedance network (DC-link voltage of inverter). During the operation, the voltage of impedance network capacitors V_C1 and V_C2 shows uniform charging and discharging profile (see Figure 26) along with the uniform inductors current profile ( see Figure 27). Hence, during the ST period, the impedance network can draw the constant current and provide a regulated boost DC-link voltage to the MLI. Figure 28 and Figure 29 illustrates the captured the inverter input DC-link voltage and multi-level output voltage across the load (V_ab) respectively. From the results, it can be seen that the 120 V input PV voltage is boosted to 349 V. The inverter load voltage V_ab is observed as 247.3 V (RMS). The corresponding V_ab voltage THD spectrum is shown in Figure 30 (without filter). Here the inverter voltage THD is observed as 14.15%, which is higher due to the participation of passive elements in the impedance network. Hence the LC filter is connected across the load, and harmonics spectrum is captured (see Figure 31 and Figure 32). The output voltage THD perceived is very less as 2.81%. The inverter load current waveform and its corresponding current THD spectrum are captured and shown in Figure 33a,b. As expected, the current THD is very less (1.7%).

Next, the simulation study is extended to T_ST = 20% with 0.866 m_a. In this operating condition, the impedance network has boosted the input PV voltage to nearly 230% and maintaining the inverter DC-link voltage at 280 V. The observed DC-link voltage and impedance network capacitor voltages are shown in Figure 34 and Figure 35. While operating the inverter with a modulation index value of m_a = 0.866, the inverter has produced the output voltage of 197.23 V, as shown in Figure 36. The inverter output voltage THD is shown in Figure 37. Using LC filter in the inverter output terminal similar to 25% T_ST performance, the voltage THD for T_ST = 20% is maintained lesser value as 2.71%. Correspondingly the current THD is observed as 1.70%. In order to validate the higher ST switching time, the simulation is extended to T_ST = 30% with different modulation indices. During this operating condition, the impedance network passive elements are utilized fully and hence the voltage THD triumphs to a higher value. Figure 38 and Figure 39 illustrates the inverter output voltage and its corresponding voltage THD (without LC filter) for m_a = 0.6. Though the inverter voltage is preserved as 292V nearly, the voltage THD is poor.

Table 3. Detailed simulation results for different duty ratio without an LC filter at m_a = 0.86 and 0.6.

DST	Vin	Vo = VDC-link	Vab for ma = 0.86	% THD Vab for ma = 0.86	Vab for ma = 0.60	% THD Vab for ma = 0.60
0	120	120	86.4 V	13.6%	59.3 V	12.6%
10%	120	177	125.6 V	13.9%	88.5 V	13.8%
15%	120	210	149.2 V	14.06%	99.1 V	13.8%
20%	120	280	197.4 V	14.11%	135.3 V	13.54%
25%	120	349	247.3 V	14.15%	166.7 V	14.06%
30%	120	410	291.7 V	19.55%	201.6 V	17.32%

and

Table 4. Detailed simulation results for different duty ratio with an LC filter at m_a = 0.86 and 0.6.

DST	Vin	Vo = VDC-link	Vab for ma =0.86	% THD Vab for ma =0.86	Vab for ma =0.60	% THD Vab for ma =0.60
0	120	120	85.1 V	2.69%	57.2 V	2.61%
10%	120	177	123.9 V	2.71%	86.9 V	2.68%
15%	120	210	147.1 V	2.72%	97.4 V	2.72%
20%	120	280	195.9 V	2.77%	133.9 V	2.74%
25%	120	349	241.2 V	2.81%	164.9 V	2.79%
30%	120	410	291.7 V	3.83%	200.1 V	3.68%

illustrates inverter voltage and its THD performances for m_a = 0.86 and m_a = 0.6 through different duty ratio from 10% to 30% without and with an LC filter, respectively.

From the tabulated results, it could be seen that DC-link voltage has a linear variation with D_ST. However, the THD of the inverter voltage increases when increasing the D_ST. For any value less than or equivalent to D_ST 25% in any modulation index, the inverter provides a wide range of voltage variation with better voltage and current THD performance.

7. Experimental Result

The proposed PV powered Q-impedance fed coupled inductor multilevel inverter experimental setup was built using six MOSFETs IRF640. The switching signals were associated with the MLI through gate driver TLP250. The switching frequency, f_s of the inverter is fixed 10 kHz for the 50 Hz inverter output. The 500 W PV module is arranged to get 100 to 120 V to meet 330 V DC-link voltage to the MLI. The RL load (resistance = 10 Ω and inductance = 5 mH) and LC filter (inductance and capacitor values of 2.5 mH, and 50 µF respectively) are used in the inverter output terminal.

Figure 40 shows the experimental setup photograph. The impedance network and other parameters used for the inverter are the same as the simulation model given in Table 2. The control switching scheme strategy is designed in PIC16F778A microcontroller, and the collaborative results are shown in keyset two channels digital signal oscilloscope (DSO).

The experimentation is carried out for the 500W constant PV power for 100 V and 5 amps current. The impedance network duty ratio is maintained at 25% with the aim of inverter constant DC-link voltage 300V. The inverter operation is investigated with its modulation index range m_a = 0 to 0.866. Initially, the inverter is operated with maximum m_a = 0.886, and the results are captured. Figure 41 shows the PWM pulse of inverter switches S₁ and S_2. The ST time between switch S₁ and S₂ is represented, in which the 25% switching time is used for ST event, and hence impedance network can generate 300% boosting to maintain the DC-link voltage. Figure 42a shows the current waveform of impedance network inductor L₁ and L₂. Figure 42b displays the voltage waveform of impedance network capacitors C₁ and C₂. The voltage profile across the impedance network capacitors V_C1 and V_C2 are indicating that variation in the V_C1 and V_C2 are identical. It can be observed that voltages V_C1 and V_C2 are equally charging the voltage since both are connected in series. Hence the proposed impedance network can provide regulated DC-link voltage to the inverter. Figure 43a,b shows the inverter output voltage (without filters) and input voltage waveform at m_a = 0.866. The results show the measured five-level inverter voltage with symmetrical set output voltage 0V, ± 125 V, ± 250 V. The THD value of load voltage is captured using power analyzer and is found to be about 17.1% (shown in Figure 44). The same experimentation is investigated further with filter, and the results are captured. Figure 45a,b shows the filtered output load and load current respectively, where the current and voltage are maintaining their THD lesser as 3.1% and 1.4% respectively (Figure 46a,b).

To understand the inverter input current control, the duty cycle is varied to 25% and 30%, and results are observed. As expected, the inverter is maintaining the input current regulation at 25% D_ST. However, when D_ST is applied to 30%, the impedance network starts losing its input current regulation. Figure 47 illustrates the output voltage of MLI and impedance input current at 25% and 30% D_ST. From the results, it could be seen that the input PV voltage is boosted via the impedance network to achieve the load voltage of 230 V peak to peak. The DC-link voltage is regulated with a minor ripple of 3%, and hence inverter can maintain its half symmetry and THD of the output voltage is perceived as less. The interesting point to notice at this stage is that the inverter can draw constant current since the impedance network input inductor L_S limits the current. The proposed inverter reliability study is conducted for different inverter operating conditions.

Table 5. Switching loss, inverter efficiency, and THD of the proposed inverter for m_a = 0.86 and f_s = 10 kHz concerning D_ST from 10% to 30%.

DST	Switching Loss in Watts	Conduction Loss in Watts	Inverter Efficiency in %	THD in %(without Filter)	THD in %(with Filter)
10%	6.4	15.2	95.68%	13.9%	2.72%
20%	9.4	16.6	94.8%	14.11%	2.77%
30%	15.2	17.3	93.5%	19.55%	3.83%

illustrations the switching loss, inverter efficiency, and THD of the proposed inverter for D_ST 10% to 30% and m_a = 0.86. From the results, it can seem that the efficiency is higher in all duty cycle. During the 10% D_ST, the inverter efficiency is about 95.68%. However, there is a small dip inefficiency at 20% and 30% duty cycle.

The proposed inverter topology, in comparison with other reported topologies for the gain accomplishments, are deliberated in

Table 6. Switching loss, inverter efficiency, and THD of the proposed inverter for m_a = 0.86 and f_s = 10 kHz concerning D_ST from 10% to 30%.

Topology Proposed in	Number of Passive Elements Used		Number of Switches Used	A Coupled Inductor or Transformer Type	Maximum Achievable Voltage Gain in %
	L	C
[39]	2	2	6	Coupled inductor	≤ 2 times
[6]	2	Intergraded winding	8	NA	≤ 2 times
[45]	4	2	2 only for converter	Coupled inductor	≥ 2 times
[46]	4	4	8	NA
[47]	4	4	8	NA	≤ 2 times
[48]	2	2	10	NA	≤ 2 times
Proposed QZ Inverter	3	2	6	Coupled inductor	≥ 2 times

. In terms of passive element usage and maximum achievable voltage gain, the proposed topology is better than topology presented in [45,46,47]. By comparing the proposed topology with inverter proposed in [36], though the proposed inverter used one extra inductor, the voltage gain is high (3 times). Figure 48 illustrates the passive components rating, cost, boosting, and THD comparisons with other similar topologies [31,39,48]. The proposed inverter topology attains fewer passive elements usage, higher voltage gain conversion and better voltage THD than [31,39,48]. Thus, the proposed inverter topology presents its efficiency and suitability for PV standalone and grid-connected systems.

8. Conclusions

The proposed Q-source MLI coupled inverter ZSI is a combination of modified Q-source impedance network with six switches coupled inductor connected single-phase five-level MLI. The quasi-Z source coupled inductors MLI tied photovoltaic system with modified space vector PWM produces a maximum voltage gain of 140%. The suggested topology generates the five-level output voltage with the higher voltage gain (maximum voltage gains of 310%) with exceptionally low voltage and current THD. Besides, the proposed MLI reduces the switching stress on the inverter for all the duty cycles in the switching algorithm, when increasing the duty cycle, the boost factor also increases. The proposed quasi Q-ZSI has the merits of operation such as reliability, reduced passive components, voltage boosting capability and reduction in switching stress. The modified space vector PWM is proposed to integrate the boosting and regular inverter switching state within one sampling period.

In comparison with other MLI, it utilizes only half of the power switch, lower modulation index to acquire high voltage gain. The performance of the proposed boost MLI topology and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for stand-alone and grid-connected PV applications.