1. Introduction
Switched mode power converters are widely used in industrial applications. They can operate in Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), and Critical Conduction Mode (CRM). It is usually hard to optimize the transient response with the CCM operation owing to the inductor current lag. To improve the transient performance, both analog and digital control strategies have been explored in the literature. For example, compared to analog approaches, digital controllers provide advantages of programmability, robustness to noise, a compact size, and flexible control algorithm, etc. In [
1,
2,
3], digital circuits are used to carry out current ramp estimation, which solves the ripple oscillation issue in the well-known
V2 control. In [
4,
5], digital charge balance controllers are proposed to achieve a time-optimal transient response. In terms of non-linear approaches, digital sliding mode controls are preferable strategies for optimizing large signal transients [
6,
7,
8,
9,
10].
For many digital control strategies, a great challenge that limits the bandwidth is the intrinsic delays in computation and analog-to-digital conversion. In order to address this issue, digital predictive and deadbeat techniques calculate state variables ahead of time, allowing earlier action to stabilize the power converter. In [
11], digital predictive current programmed control is proposed with various modes, i.e., peak, valley, and average current modes. With various current sampling rates, predictive average current control can be flexibly realized with different complexities and performances [
12]. Other studies have focused on the sensorless realization of predictive current controls, where conventional current sensors are substituted by current observers [
13,
14]. For example, through current observation, digital dead-beat current controllers can minimize the current error in one control cycle [
15,
16].
For predictive and many other control strategies, the accuracy of the converter model is a determinant issue that affects the control performance. To facilitate digital controller design and analysis, discrete-time models have been intensely studied [
17,
18], and a widely accepted modeling approach is state averaging. Although state averaged discrete-time models can be directly derived through standard Z-transform, the transform error leads to a degraded accuracy [
19]. In [
20], discrete-time models for different converters are derived with a consideration of leading-edge and trailing-edge modulations, and approximate expressions are acquired in the frequency domain. In [
21], a geometric state-averaged model and a centric control strategy are proposed to achieve reliable and predictable large-signal transient responses. In [
22], a geometric tuning method is proposed for a buck converter with digital current mode control under continuous conduction mode. Using phase-plane geometry, the controller gain is tuned to achieve a proximate time optimal transient response of the output voltage. In [
23], a discrete-time hybrid model is derived for a boost converter, and an enumeration-based Model Predictive Control (MPC) strategy improves the transient response in both continuous and discontinuous conduction modes.
Due to the nonlinear nature of switched mode converters, their modeling and control design have always been a great challenge. Accurate converter modeling can benefit high-performance converter design and analysis. However, without a consideration of switching actions and dynamics within a switching cycle, the conventional state-averaging method has a limited accuracy at a high frequency. A recent review on small-signal modeling methods indicates that the conventional averaged models have a low accuracy at high frequencies [
24]. When these models are used for optimization, the degraded accuracy can lead to unreliable controller design and stability analysis, especially when a very fast response speed is required.
In this paper, a State Switched Discrete-time Model (SSDM) is proposed, which achieves a higher accuracy at a high frequency than conventional state averaged models. Instead of averaging the converter states for approximation, the dynamic states within each switching cycle are considered in the modeling process. Based on exact differential equations of switching-ON and switching-OFF durations, the inductor current and output voltage within a cycle are accurately calculated. This improves the modeling accuracy, and the discretized result forms the SSDM. Furthermore, a Digital Predictive Voltage Programmed (DPVP) control law is derived through SSDM. Through voltage prediction, a suitable duty ratio is calculated, which regulates the output voltage to its reference value in the minimum switching cycles. Finally, with additional integral compensation and saturation limits, a practical DPVP control strategy is derived. This strategy exhibits a high stability under deviated inductance, and achieves very fast large-signal transient responses. The effectiveness of the proposed strategy is verified by detailed simulations and experiments.
The paper is organized as follows. In
Section 2, the state equation of SSDM is derived through total differential equations of switching-ON and switching-OFF durations. In
Section 3, the DPVP control law is given, which is designed to regulate the output voltage to its reference value in the minimum switching cycles. Additionally, a practical DPVP control strategy is proposed with an integral compensation and saturation limit for Digital Pulse Width Modulation (DPWM).
Section 4 proves the accuracy of SSDM and the stability under DPVP control by open-loop and closed-loop frequency response analyses. Finally, experimental results are given in
Section 5 to verify the improved transient response and the robustness to inductance variation. A brief conclusion is given in
Section 6.
2. State Switched Discrete-Time Model
In deriving the proposed SSDM, the inductor current and output voltage are calculated during switching-ON and switching-OFF durations, respectively. Under DPWM, the durations are given by
TON =
dT and
TOFF = (1 −
d)
T, where
d is the duty ratio and
T is the switching period. With a consideration of current and voltage transients within a switching cycle, a buck converter scheme and the state variables are given in
Figure 1.
In
Figure 1a,
L is the power inductance,
R is the load resistance,
C is the output capacitance,
vin is the input voltage,
vout is the output voltage, and
iL denotes the inductor current. In each switching cycle (
Figure 1b), the state variables begin with the initial state
, and achieve the transition state
at
t =
TON. They achieve the end-point state
at time
t =
T =
TON +
TOFF.
With a fixed switching cycle, it is obvious that
xe is a function of
:
Since
xe in one switching cycle is
xs of the next switching cycle, i.e.,
, the discrete-time state space model of the converter is given by
Furthermore, the modeling accuracy is determined by the function at the right side of Equations (1) and (2), which will be derived by total differential equations of switching-ON and switching-OFF durations. First, state variables and their derivative values at switching transients are given as constrains to solve the differential equations. Second, differential equations of the inductor current and output voltage are solved for the switching-ON duration, which derive the relationship between xs and xm. Furthermore, differential equations for the switching-OFF duration are solved, which derive the relationship between xm and xe. Finally, the relationship between xs and xe is derived.
2.1. State Variables and Their Derivative Values at Switching Transients
For the buck converter, the state variables and their derivative values at switching transients are given in
Figure 2, where the inductor current and output voltage at
t = 0 are given by
Additionally, first-order derivatives of these parameters are determined by the instant voltage on the inductor and current through the capacitor. Therefore, at
t = 0
+, the derivative values
and
are given by
At
t =
TON, by continuity of the voltage and current signals, it is possible to write
At
t =
TON+, the instant voltage on the inductor and current through the capacitor are
and
, respectively. Therefore, derivatives of the current and voltage are given by
The aforementioned values will be used to solve differential equations of the inductor current and output voltage during switching-ON and switching-OFF, respectively.
2.2. Inductor Current and Output Voltage during Switching-ON
During switching-ON, the equivalent circuit scheme of the buck converter is as given in
Figure 3. Since the voltage on the inductor and current across the capacitor are
and
, respectively, derivatives of the current and voltage are given by Equation (7).
Using circuit laws and Equation (7), differential equations of
and
are given by
These second-order differential equations have the same characteristic roots, which are
Furthermore, explicit values of
and
are solved as
Taking Equations (3) and (4) into Equation (10) yields
Finally, substituting
into Equation (10) gives
, as shown in Equation (12).
This equation reveals the relationship between xs and xm, which is affected by .
2.3. Inductor Current and Output Voltage during Switching-OFF
During switching-OFF, the equivalent circuit scheme of the buck converter is as given in
Figure 4. Since the voltage on the inductor and current across the capacitor are
and
, respectively, derivatives of the current and voltage are given by Equation (13).
Based on Equation (13), differential equations of
and
are given by
Obviously, Equation (14) has the same characteristic roots as Equation (8), and explicit values of
and
are solved as
Taking Equations (5) and (6) into Equation (15) gives
Furthermore, substituting
t =
TON +
TOFF into Equation (15) gives
, as shown in the following:
Combining Equation (12) and Equation (17), the relationship between
xs and
xe is derived as Equation (18):
where
and
are given in Equation (19). Furthermore, the variables in Equation (18) are listed in
Table 1.
Finally, since
is always valid, the state equation of the proposed SSDM is given by
This model achieves a higher accuracy than that of conventional state-averaged models, which will be proved by the simulations in
Section 4. Furthermore, the SSDM is used to derive the DPVP control strategy.
3. Digital Predictive Voltage Programmed Control
The scheme of the buck converter under DPVP control is given in
Figure 5. The DPVP controller needs three Analog to Digital Converters (ADCs) ADCs to sample the input voltage, output voltage, and inductor current. The sampled values are used to calculate
g2(
d) with Equation (20). Furthermore, a look-up-table of
is used to acquire the duty ratio from
g2(
d). Finally, the duty ratio is modulated through DPWM to control the buck converter.
With DPVP control, vout,s should be regulated to vREF in one switching cycle, and the bandwidth of the controller is maximized. The DPVP control law, stability, and saturation issues are analyzed in the following.
3.1. DPVP Control Law
The DPVP controller calculates a suitable
g2(
d) and
d to shape the output voltage. In an ideal condition, the output voltage can be regulated to track its reference in one switching cycle, as shown in
Figure 6a. In the
kth switching cycle,
is valid, and the converter operates at a steady state. In the
k + 1th switching cycle, the reference voltage steps up, which induces a positive voltage error. Furthermore, to eliminate the error, the duty ratio is increased, which ensures
. Finally, the output voltage re-stabilizes in the
k + 2th switching cycle. In this way,
vout,s tracks
vREF in one switching cycle, i.e.,
vout,s =
vREFz−1.
In a practical condition, with a consideration of parasitics, the output voltage tracks its reference value in three switching cycles, as shown in
Figure 6b. The results are exported from a Matlab-Simulink simulation.
The DPVP control law is derived from the SSDM model. Based on Equation (20), the relationship between
and
is given by
Substituting the control object
into Equation (21) gives
Furthermore, an inverse function is used to derive the duty ratio, which regulates to in one switching cycle.
3.2. Stability Analysis and Compensation for a DPVP Controlled Buck Converter
Based on Equation (22), the output voltage can be regulated to
vREF in just one switching cycle. In this way, the control loop bandwidth is maximized. However, as a nonlinear control approach, the DPVP control law lacks integral items. This induces steady state error between
vout,s and
vREF. Besides, an extremely high bandwidth can degrade the robustness to parameter deviations. In order to eliminate the steady state error and improve the stability, an integral compensator
IT/(
z − 1) is used to reduce the bandwidth, which forms the control scheme in
Figure 7a.
Furthermore, the closed-loop equivalent model is given in
Figure 7b, and the closed-loop transfer function from
vREF to
vout,s is given by
Equation (23) has two poles located at
. When
IT varies from 0 to 1, the variations of the poles are as given in
Figure 8. When
IT < 1/4, both poles are real, and the bandwidth is degraded by the lower pole. When
IT ≥ 1/4, the poles become conjugated to the real axis. As
IT increases, the poles move toward the unit cycle, leading to a degraded stability. In order to improve the bandwidth while maintaining the stability,
IT should be near to 0.35 when the damping factor is 0.7 and the closed-loop bandwidth is 0.25
π/
T. The achieved bandwidth is relatively high for DC-DC converters operating in CCM.
3.3. Saturation of DPWM
Switched mode power converters are nonlinear systems, where the large-signal performance is limited by DPWM saturation. With DPVP control, the output of
might be greater than unity or lower than zero, which leads to the saturation of DPWM. The saturation issue limits the physical-achievable slew rate of the output voltage and leads to potential instability. Therefore, the input of the integral compensator is limited to eliminate the DPWM saturation, which derives the practical control scheme in
Figure 9.
Since the achievable duty ratio is between zero and unity, the output voltage of the converter has a limited slew rate. For the buck converter, the output voltage increases along the duty ratio. The variation of the output voltage in one switching cycle reaches its maximum value when
d = 1 and reaches its minimum value when
d = 0. Therefore, the output voltage slew rate is limited by either
d = 1 or
d = 0, as shown in
Figure 10.
Based on Equation (20), the initial voltage of the next switching cycle is given by
Therefore, the variation of
vout,s in one switching cycle is
The magnitude reaches its maximum value when
d = 1 and reaches its minimum value when
d = 0, as shown in Equation (26).
Therefore, the output voltage slew rate is limited between
and
, as shown in the following:
To avoid potential oscillation, this physical saturation should be avoided in the controller design. Since the slew rate is limited by the input of the integral compensator, Equation (28) is applied to the controller.
In this way, physical saturation of DPWM is avoided, which eliminates potential oscillations.
5. Experiments
Experimental results are given to verify the effectiveness of the proposed DPVP controller. The main specifications of the buck converter are shown in
Table 2. The specifications are designed to achieve a typical power rate of 5 W, a current ripple rate of ±0.35, and an output voltage ripple rate below 1%. The input/output voltages are selected for point-of-load applications, USB chargers, and an embedded system power supply, etc.
A photograph of the prototype is given in
Figure 18. An FPGA (Cyclone IV) control board is used to carry out digital control algorithms. The output and input voltages are sampled by ADC (LTC2314-14) modules. A main switch MOSFET (FDS86540) and a diode (NRVTSA4100E) are used as switching components. The output capacitor adopts two 10 µF capacitors (KRM55QR71J106KH01K) connected in parallel. The core material of the inductor is NPH107060, which is adequate for a switching frequency below 200 kHz.
The output voltage was measured under disturbances of load, input voltage, and reference voltage. The results under DPVP control were compared with those of a digital current mode controller with Proportional Integral Derivative (PID) PID compensation in the outer loop. For the digital current mode controller, the PID compensator was optimized through the PID tuner toolbox in Matlab. It was designed with a phase margin of 75 degrees and the cross-over frequency was 30k rad/s. Furthermore, the robustness of the system under DPVP control was verified under deviated inductance.
5.1. Output Voltage Transient Responses
As shown in
Figure 19a, when the load resistance steps from 10 to 5 Ω, the output voltage deviates by −0.6 V and re-stabilizes in 130 μs under digital current mode control with PID compensation. According to the analyses in
Section 4, the closed-loop frequency response of the load transient is near-derivative in a low-frequency range and near-integrative in a high-frequency range. The response approximates a typical second-order system with a nature frequency of 70 k rad/s. Therefore, with a damping factor of 0.7, the output voltage should re-stabilize in 36 μs. As shown in
Figure 19b, the experimental results match with those of the analysis. The output voltage deviates by −0.3 V and re-stabilizes in 40 μs.
As shown in
Figure 20a, when the input voltage steps from 12 to 9.5 V, the output voltage drops by 0.8 V and re-stabilizes in 200 μs under digital current mode control with PID compensation. According to
Figure 16, the frequency response under DPVP control is near-derivative in all frequency ranges and the magnitude is very low. This indicates a strong rejection to input voltage disturbance. As shown in
Figure 20b, the experimental result matches that of the analysis. When the input voltage steps from 12 to 9.5 V, the output voltage deviates by −0.2–0.15 V and re-stabilizes in 60 μs.
When the reference voltage steps from 5 to 6 V, the output voltage tracks it in 150 μs under digital current mode control with PID compensation. According to the analyses in
Section 4, the bandwidth of the closed-loop system is about 65 k rad/s. Therefore, with a damping factor of 0.7, the output voltage should reach the reference value in 38 μs. The experimental result matches that of the analysis, as shown in
Figure 21b. The output voltage reaches the reference voltage in 30 μs, which is five times faster than that of digital current mode control.
5.2. The Robustness to Deviated Inductance
According to the closed-loop analyses in
Section 4, the converter remains stable when
La deviates from 0.9 to 1.6
L. However, high-frequency oscillation might occur when
La is smaller than
L. When
La is larger than
L, although the performance is slightly degraded, the high-frequency oscillation is eliminated. Therefore,
La can be set a little higher than
L to improve the robustness to deviated inductance. In the following, experimental results are given when
La deviates to 1.3 and 1.6
L, respectively.
When the load resistance steps from 5 to 10 Ω, the output voltage transients are as given in
Figure 22. With
La = 1.3
L and
La = 1.6
L, the output voltage suffers from a degraded transient performance. The response time increases to 60 and 70 μs, respectively. When the input voltage steps from 12 to 9.5 V, the output voltage transients are as given in
Figure 23. The transient response time increases to 70 and 90 μs, respectively. When the reference voltage steps from 5 to 6 V, the output voltage transients are as given in
Figure 24. The output reaches the reference voltage and stabilizes in 50 and 100 μs, respectively. Although the transient responses are degraded with a deviated inductance, the output voltage is still stable when
La = 1.6
L. The results indicate a high robustness of DPVP control to inductance deviation.
All results match those of the analyses and simulations, and prove the effectiveness of the proposed DPVP control strategy.
6. Conclusions
This paper proposes a State Switched Discrete-time Model and Digital Predictive Voltage Programmed controller for a buck converter operating in continuous conduction mode. Compared with the conventional state-averaged modeling method, the SSDM considers the variation of states within a switching cycle, and it achieves a higher accuracy at a medium and high frequency. Furthermore, based on SSDM, a DPVP control law is proposed that regulates the output voltage to its reference value in one switching cycle. Finally, with an integral compensation and saturation limit for DPWM, a practical DPVP control strategy exhibits a high stability and achieves very fast transient responses.
The accuracy of SSDM has been proven by simulations, which were compared with the conventional state averaged discrete-time model and the circuit model. The stability and robustness under DPVP control was proven by open-loop and closed-loop frequency analyses. Finally, the effectiveness of the DPVP controller and the robustness to deviated inductance were verified through experiments.