Open Access
This article is

- freely available
- re-usable

*Energies*
**2018**,
*11*(11),
3096;
doi:10.3390/en11113096

Article

Power Factor Corrector with Bridgeless Flyback Converter for DC Loads Applications

Department of Electircal Engineering, Chang Gung University, Tao-Yuan 33302, Taiwan

^{*}

Author to whom correspondence should be addressed.

Received: 30 August 2018 / Accepted: 5 November 2018 / Published: 9 November 2018

## Abstract

**:**

Since power systems with a DC distribution method has many advantages, such as conversion efficiency increase of about 5–10%, cost reducing by about 15–20% and so on, the AC distribution power system will be replaced by a DC distribution one. This paper presents a DC load power system for a DC distribution application. The proposed power system includes two converters: DC/DC converter with battery source and power factor corrector (PFC) with a line source to increase the reliability of the power system when renewable energy or energy storage equipment are adopted. The proposed PFC adopts a bridgeless flyback converter to achieve power factor correction for supplying power to DC loads. When the bridgeless flyback converter is used to achieve PFC, it needs two transformers to process positive and negative half periods, respectively. In order to increase conversion efficiency, the flyback one can add two sets of the active clamp circuit to recover energies stored in leakage inductances of transformers in the converter. Therefore, the proposed bridgeless flyback converter can not only integrate two transformers into a single transformer, but also share a clamp capacitor to achieve energy recovery of leakage inductances and to operate switches with zero-voltage switching (ZVS) at the turn-on transition. With this approach, the proposed converter can increase conversion efficiency and decrease component counts, where it results in a higher conversion efficiency, lower cost, easier design and so on. Finally, a prototype with a universal input voltage source (AC 90–265 V) under output voltage of 48 V and maximum output power of 300 W has been implemented to verify the feasibility of the proposed bridgeless flyback converter. Furthermore, the proposed power system can be operated at different cases among load power P

_{L}, output power P_{DC1}of DC/DC converter and output power P_{DC2}of the proposed PFC for supplying power to DC loads.Keywords:

bridgeless flyback converter; PFC; active clamp circuit; ZVS; DC distribution## 1. Introduction

Since power systems with a DC distribution method has many advantages, such as conversion efficiency increase of about 5–10%, cost reducing by about 15–20% and so on, the AC distribution power system will be replaced by a DC distribution one [1]. Figure 1 shows a block diagram of a power system for DC load applications. The power sources of the power system can adopt utility line, solar arrays, battery or wind turbine, etc. The power system using a power processor is widely applied to the general electrical or electronic equipment. In order to obtain a lighter weight and a smaller volume, a switching-mode converter is regarded as the power processor of the power system. When a power factor corrector (PFC) is used for the AC/DC power system [2,3,4,5,6,7,8,9,10,11,12] to protect the line source from harmonic current pollution, it has to meet the recommended limits of harmonics in supply current by various international power quality standards, such as the International Electrotechnical Commission (IEC) 61000-3-2 [2]. Therefore, the AC/DC converter adopts PFC techniques to increase power factor (PF), in which input voltage waveform can be made to be completely in phase with the input current one, implying approximately unity power factor.

In general, a boost converter, as shown in Figure 2, or buck-boost converter is adopted in the PFC system. In order to reduce the conduction losses of diodes, a bridgeless boost converter is adopted to achieve a higher power factor, as shown in Figure 3. Due to the universal input voltage source (AC 90–265 V), its output voltage is regulated at approximately 400 V. For a power system under a lower level output voltage condition, it needs an extra DC/DC converter as a step-down converter. Therefore, the topology of two stages is used to achieve a lower output voltage, resulting in a higher cost and a lower conversion efficiency. Single stage topology with buck-boost converter has been an alternative solution in various power conversions. In order to further increase the step-down ratio, a bridgeless flyback converter is regarded as the power processor because of its topological advantages, such as simple circuit structure, low cost, and galvanic isolation, as depicted in Figure 4. It is adopted in not only low power isolated single-stage single-phase AC/DC converters which is regarded as the front end of the switching-mode power supply, but also uninterrupted power supplies (UPS), induction heating, electronic ballast, telecom power supplies, light emitting diode drivers [13,14,15], etc.

Since a flyback converter adopts a transformer to be regarded as a stored inductor and an isolated transformer, a leakage inductance exists in the primary side, resulting in a higher voltage stress across switches of the converter when switches are turned off. In order to limit a high voltage stress across switches, a resistor-capacitor-diode (RCD) clamp circuit is used to reduce switch voltage spike. Although the RCD circuit can smooth out the voltage spike, the energy stored in leakage inductance is released to the clamp resistor. As a result, the conversion efficiency of the flyback converter does not increase. For improving conversion efficiency of the one with the RCD clamp circuit, an active clamp circuit is used to replace the RCD clamp circuit, as shown in Figure 5. With this approach, the energy stored in leakage inductance can be recycled and switches in the converter can be operated with zero-voltage switching (ZVS) at the turn-on transition [16,17].

When the PFC adopts a bridgeless flyback converter, it needs to process power in a positive and negative half periods of the line source, resulting in that its component counts almost need twofold of its counterpart circuit [18,19]. Particularly, using more than one magnetic device in the bridgeless flyback converter impacts the advantage, which is the circuit simplicity. In order to further simplify the circuit structure, two transformers in the bridgeless flyback converter is replaced with a three-winding transformer, as illustrated in Figure 6. Furthermore, two active clamp circuits share a capacitor. It will reduce weight, volume and component counts, significantly.

This paper proposes a bridgeless flyback converter, illustrating that the proposed one is without bridge diodes to remove the diode conduction loss and increase conversion efficiency. In addition, the proposed one adopts a three-winding transformer to substitute for two transformers. When the output maximum power of the proposed bridgeless flyback is the same as that of the conventional bridgeless flyback converter, as shown in Figure 5, its maximum input current I

_{i}is also the same as each other, and maximum working flux B_{pk}of the transformer in the proposed converter is also the same as that in the conventional bridgeless flyback converter. Figure 7 shows a B-H curve of the transformer T_{r}in the flyback converter. Since the conventional flyback converter uses a bridge rectifier to rectify input current I_{i}, the rectified input current I_{i}can be obtained by a positive value during a complete switching cycle. Its B-H curve is illustrated in Figure 7a. As a result, the conventional flyback converter can use a set of transformers to implement PFC function. While, the bridgeless flyback converter, as shown in Figure 5, needs two sets of transformers to process energy under the positive half period and the negative half period. Its B-H curve is illustrated in Figure 7b. Due to the proposed bridgeless flyback converter with a three-winding transformer, its B-H curve is the same as the conventional flyback one, as shown in Figure 7a. Therefore, the proposed bridgeless converter can save a set of transformers. It can simplify the circuit structure, significantly. Therefore, the proposed bridgeless flyback converter for the PFC power system can achieve a higher power factor to avoid the line source from harmonic pollution, possesses soft-switching features in which switches are operated in ZVS at turn-on transition to increase conversion efficiency. It is suitable for a low power level application. This paper focuses on design and analysis of the proposed bridgeless flyback converter and power management for DC loads of power system.## 2. Control Algorithm of the Proposed System for DC Load Applications

The proposed bridgeless PFC is applied to a DC load power system. In order to implement a DC load power system, the proposed one and a DC/DC converter with a battery source connected in parallel to supply power for DC loads. Its block diagram is shown in Figure 8. The control algorithm of the proposed power system for DC load applications is described in the following sections.

1. Circuit Topology of the Proposed Power System

The proposed DC load power system consists of a DC/DC converter with a battery source and a bridgeless PFC and single-chip control circuit. The output voltage V

_{DC}_{2}of the bridgeless PFC is close to and is greater than the output voltage V_{DC1}of the DC/DC converter. Therefore, the diode D_{B}is used to block the voltage difference between voltages V_{DC}_{2}and V_{DC1}. The DC load R_{L}is supplied power from the proposed PFC and the DC/DC converter. When the load power P_{L}is less than or equal to P_{DC2}_{(max)}which is the maximum output power of the proposed PFC, the proposed PFC supplies power to load. If P_{L}is greater than P_{DC2}_{(max)}, the proposed PFC and the DC/DC converter supply power to load for achieving a DC load power system.2. Control Algorithm of Each Unit

● DC/DC converter

The DC/DC converter adopts a boost converter with a single-capacitor snubber [20]. It can transfer power from the battery to load. Since its output voltage V

_{DC1}is less than the voltage V_{DC}_{2}, a diode D_{B}is used to protect the DC/DC converter. Therefore, the protection diode with the output diode of boost converter is replaced by the extra diode D_{B}. If the operational state is in the 0 < P_{L}≤ P_{DC2}_{(max)}state, the battery with the DC/DC converter can be operated in the charging mode. It needs an extra charger to charge the battery. When the proposed power system is operated in an abnormal state, the single-chip control circuit sends a shutdown signal S_{D1}under a high level to the pulse width modulation (PWM) control circuit of the DC/DC converter. The DC/DC converter can be operated in the shutdown state to protect the DC/DC one.● The Proposed PFC

The proposed PFC uses a bridgeless flyback converter which is regarded as a power factor corrector for increasing power factor between input voltage and input current of a line source. Its control circuit adopts a PWM IC for PFC control. Figure 9 illustrates conceptual waveforms of voltage V

_{C1}and current I_{D1}. Variation of current I_{D1}follows the sine waveform of input voltage V_{C1}. Figure 9a shows concept waveforms under a complete line period, while Figure 9b depicts those waveforms under a positive half period. From Figure 9b, it can be seen that the proposed flyback converter can be operated in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) under a positive half period. When the proposed one is operated in the A and C areas, inductor current I_{LK}is in the DCM state due to a lower voltage level of input voltage V_{C1}. If input voltage V_{C1}is during the B area interval, the proposed converter is operated in CCM. According to the operational method of the proposed one as mentioned above, input voltage V_{in}and current I_{i}are in phase. Therefore, the proposed flyback converter can increase PF and reduce total harmonic distortion (THD).In Figure 8, when output current I

_{DC}_{2}of the proposed PFC is less than or is equal to the maximum output current I_{DC}_{2}_{(max)}, the output feedback voltage V_{F}is equal V_{DC}_{2}(diode D_{P1}is forward biased). The proposed PFC is operated as the voltage regulator. If I_{DC}_{2}is greater than I_{DC}_{2}_{(max)}, the output current I_{DC}_{2}is regulated at I_{DC}_{2}_{(max)}. That is, the proposed one is operated as the current regulator. The voltage V_{F}is equal to I_{DC}_{2(max)}and the diode D_{P2}is in the forwardly bias state. In addition, when the proposed power system has an abnormal operational condition, the shutdown signal voltage S_{D2}is changed from a low level to a high level. The proposed PFC is shut down to protect the proposed one.3. Single-Chip Control Circuit

The single-chip control circuit includes three units: The battery protection unit, line source protection unit and output protection unit. According to the operational relationships between DC/DC converter and the proposed PFC, the operational cases are divided into four cases, as listed in Table 1. Symbol definition of the proposed power system is listed in Table 2. Their operational conditions are described in the following section.

● Case I: P

_{L}= 0 WWhen P

_{L}= 0 W, the DC/DC converter with battery source and the proposed PFC are operated in the shutdown mode.● Case II: 0 < P

_{L}≤ P_{DC2}_{(max)}When 0 < P

_{L}≤ P_{DC2}_{(max)}, P_{B}= 0 W and P_{DC2}= P_{L}. The DC/DC converter with battery source and the proposed PFC with line source are operated in the working state.● Case III: P

_{DC2}_{(max)}< P_{L}≤ P_{DC2}_{(max)}+ P_{B}_{(max)}When P

_{DC2}_{(max)}< P_{L}≤ P_{DC2}_{(max)}+ P_{B}_{(max)}, P_{DC2}= P_{DC2}_{(max)}and P_{B}= P_{L}− P_{DC2}_{(max)}. The DC/DC converter and the proposed PFC are in the working state.● Case IV: P

_{L}> P_{DC2}_{(max)}+ P_{B}_{(max)}When P

_{L}> P_{DC2}_{(max)}+ P_{B}_{(max)}, the proposed power system is operated in the over-load state. Therefore, the DC/DC converter and the proposed PFC are in the shutdown state.There are three protection units in the proposed power system: Battery protection, line source protection and output protection units. In order to increase protections of the proposed power system, hardware and software methods are adopted to protect the proposed one. Due to the same protection functions between hardware and software methods, the operation of hardware protection circuit is introduced in this paper. Figure 10 shows a block diagram of the single chip control circuit for the hardware protection circuit. In the battery protection unit, when I

_{B}> I_{B}_{(max)}, the discharging current I_{B}is in the over-current state. Voltage V_{B1}is changed from a low level to a high level. Voltage S_{D1}is equal to V_{S1}(=V_{B1}). The DC/DC converter is shut down to protect the battery. If V_{B}< V_{B}_{(min)}, the battery is in the under-voltage state. Voltage single V_{B2}is changed from a low level to a high level, and signal S_{D1}is the same as V_{S1}(=V_{B2}). Therefore, the DC/DC converter is also shut down.In the line source protection unit, when V

_{i}< V_{i}_{(min)}(=AC 90 V), the proposed PFC is shut down by S_{D2}. In this case, the line source is in the under-voltage state, and voltage signal V_{i1}varies from a low level to a high level. Since V_{i1}= V_{S3}= S_{D2}, the proposed PFC is shut down by signal S_{D2}, which is in a high level state. If I_{i}> I_{i}_{(max)}, the signal V_{i2}is equal to V_{S3}(=S_{D2}), and V_{i2}is in a high level state. The proposed PFC is operated in the over-current state and it is shut down by S_{D2}. In the output protection unit, there are two cases to protect the proposed power system. One is that output voltage is in the under-voltage state. The other one is that output current is in the over-current state. When two protection cases occur, the proposed power system is shut down. In the under voltage state, V_{DC}< V_{DC}_{(min)}, voltage V_{D1}= V_{S2}= S_{D1}= V_{S4}= S_{D2}is changed from a low level to a high level to shut down the proposed one. When I_{DC}> I_{DC}_{(set)}, voltage V_{D2}= V_{S2}= S_{D1}= V_{S4}= S_{D2}is varied from a low level to a high level. The proposed one is shut down. Therefore, the proposed power system can use the battery protection unit, line source protection unit and output protection unit to avoid the abnormal operational condition in the proposed power system.## 3. Operational Principle of the Proposed PFC

The proposed bridgeless flyback converter uses a three-winding transformer to achieve operations of the positive and negative half periods of the line source, as depicted in Figure 6. Its equivalent circuit is illustrated in Figure 11a,b, respectively. When the line source enters the positive half period, switches M

_{1}and M_{2}are operated in complementary. During this time interval, switches M_{3}and M_{4}are always turned off, as shown in Figure 11a. The input energy supplied by the line source is transferred to load through windings N_{1}and N_{3}of the transformer. Furthermore, when the proposed converter is operated in the negative half period, switches M_{1}and M_{2}are turned off and switches M_{3}and M_{4}, in turn, are operated in complementary, as depicted in Figure 11b.The operational principle of the proposed flyback converter is divided into two different half periods: Positive and negative half periods. According to operational principle of equivalent circuit shown in Figure 11a,b, operational modes of the proposed one operated in the positive period are similar to those modes in the negative period, except that switches M

_{1}and M_{2}are changed to switches M_{3}and M_{4}. Furthermore, since the period T_{l}of the line source is much greater than T_{s}of switching converter, the input voltage is regarded as a constant value during each switching period T_{s}. Therefore, the operational principle of the proposed bridgeless flyback converter can adopt, that input voltage is a constant DC voltage and the proposed one is operated in the positive half period of the line source, to explain its operational principle. According to the operational principle of the proposed converter, operational modes of the proposed one are divided into seven modes. Each operational mode is shown in Figure 12 over one switching cycle, and its key waveforms are illustrated in Figure 13. Its operational principle is described in the following.- Mode 1 [Figure 12a; t
_{0}≤ t < t_{1}]: Before t_{0}, switch M_{1}is kept in the turn-on state, while M_{2}is in the turn-off state. When t = t_{0}, current I_{DS1}of switch M_{1}reaches to the initial current which is the minimum inductor current I_{L}(0) of the proposed converter operated in continuous conduction mode (CCM). Within this time interval, the inductor current I_{LK}linearly increases and current I_{DS1}is equal to I_{LK}. Since the diode D_{2}is reverse biased, the capacitor C_{o}supplies the load with energy. In this interval, inductance L_{m1}is in the stored energy state. - Mode 2 [Figure 12b; t
_{1}≤ t < t_{2}]: At t = t_{1}, switch M_{1}is turned off and M_{2}is operated in the off state. The energies stored in leakage inductor L_{k}and magnetizing inductor L_{m1}are transferred to capacitors C_{M1}and C_{M2}. Voltage V_{DS1}across switch M_{1}is charged from 0V to (V_{in}+ V_{o}/N) and voltage V_{DS2}across switch M_{2}is charged from (V_{in}+ V_{o}/N) to 0 V. Since the charge time is very small, capacitor C_{M1}is in an approximately linear charging state and C_{M2}is in an approximately linear discharging state. The output capacitor C_{o}maintains output voltage V_{o}at a desired value. - Mode 3 [Figure 12c; t
_{2}≤ t < t_{3}]: When t = t_{2}, switch voltage V_{DS1}is equal to (V_{in}+ V_{o}/N) and V_{DS2}equals to 0 V. Diode D_{2}and D_{M2}starts to forwardly bias. Voltage of secondary winding in transformer T_{r}is clamped to output voltage V_{o}. Within this time interval, inductance L_{k}and capacitor C_{c}are in a resonant manner. Furthermore, magnetizing inductor L_{m1}releases the energy through transformer T_{r}to load. - Mode 4 [Figure 12d; t
_{3}≤ t < t_{4}]: At t_{3}, switch M_{2}is turned on and switch M_{1}is kept in the off state. Since the body diode D_{M2}is forward biased before switch M_{2}is turned on, switch M_{2}is operated with ZVS at turn-on transition. Inductance L_{k}and capacitor C_{c}are kept in the resonant state. The energy stored in L_{m1}is transferred to load by means of transformer T_{r}. - Mode 5 [Figure 12e; t
_{4}≤ t < t_{5}]: When t = t_{4}, switch M_{2}is turned off. A new resonant network is formed between inductance L_{k}and capacitors C_{M1}and C_{M2}. Capacitor C_{M1}is discharged and C_{M2}is charged through inductance L_{k}. As a sequence, switch voltage V_{DS2}changes from 0 V to (V_{in}+ V_{o}/N), while V_{DS1}varies from (V_{in}+ V_{o}/N) to 0 V. Magnetizing inductance L_{m1}is in the released energy state. Diode D_{2}maintains in the forwardly bias state. - Mode 6 [Figure 12f; t
_{5}≤ t < t_{6}]: At t_{5}, switch voltage V_{DS1}is equal to 0 V. Inductance current I_{Lk}equals a negative value. Voltage across inductance L_{k}is equal to (V_{in}+ V_{o}/N). The operational states of magnetizing inductance L_{m1}and diode D_{2}are the same as those states of mode 5. - Mode 7 [Figure 12g; t
_{6}≤ t < t_{7}]: When t = t_{6}, switch M_{1}is turned on. Since body diode D_{M1}is forward biased before t = t_{6}, switch M_{1}is operated with ZVS at turn-on transition. Inductance current I_{Lk}varies from a negative value to the initial current which is the minimum current value of inductance L_{m1}when the proposed converter is operated in CCM. When t = t_{7}, current of magnetizing inductance L_{m1}reaches its minimum value again, a new switching cycle will start.

## 4. Design of the Proposed PFC

Due to the input voltage with a sine wave, the input current I
where I
where P
where V

_{in}is time dependent. A function of peak current of switch M_{1}or M_{2}is, in turn, a function of duty cycle of the converter. Therefore, peak switch current I_{DS1}needs to be determined as a function of which the instantaneous operating point is on the input line period. Neglecting ripple current in the switch, switch current I_{DS1}(ϕ) can be determined by
$${I}_{DS1}(\varphi )=\frac{{I}_{av}(\varphi )}{D(\varphi )},$$

_{av}(ϕ) is the average input line current and D(ϕ) is an instantaneous duty cycle. In (1), one half of the line cycle period is considered to be normalized to the interval [0, π], and ϕ is an arbitrary point on that interval. I_{av}(ϕ) is given by
$${I}_{av}(\varphi )=\frac{\sqrt{2}{P}_{o}}{\eta {V}_{rms}}\mathrm{sin}(\varphi ),$$

_{o}is the output power of the converter, $\eta $ indicates the conversion efficiency and V_{rms}is the input voltage of line source. The instantaneous duty cycle is
$$D(\varphi )=\frac{{V}_{o}}{{V}_{o}+\sqrt{2}N{V}_{rms}\mathrm{sin}(\varphi )},$$

_{o}is the output voltage and N is the turns ratio of transformer T_{r}. As mentioned above, D(ϕ) can vary from D_{min}to 1. In order to achieve systematic design of the proposed bridgeless flyback converter, its design is listed as follows:● switches M

_{1}–M_{2}The turns ratio N of transformer is selected to accommodate a low voltage ratio device for minimum duty cycle of switch to realize reasonable values, when the active clamp circuit in the proposed converter can provide a perfect suppression of the spike voltage across the main switch M
where ${V}_{rms}^{HL}$ is the high line voltage of input source which is equal to AC 265 V and V
And
where ${V}_{rms}^{LL}$ is the low line voltage of the input source which is equal to AC 90 V. In general, the minimum duty cycle ranges are determined between 0.2 and 0.5 under the input source at high line or low line voltage.

_{1}or M_{3}due to leakage inductance of transformer, the maximum off-state voltage V_{DS1(max)}can be determined by
$${V}_{DS1\left(\mathrm{max}\right)}=\sqrt{2}{V}_{rms}^{HL}+{V}_{O}/N,$$

_{o}indicates the output voltage. The ranges of the minimum duty cycle can be given by
$${D}_{\mathrm{min}}^{LL}=\frac{{V}_{O}}{{V}_{O}+\sqrt{2}N{V}_{rms}^{LL}},$$

$${D}_{\mathrm{min}}^{HL}=\frac{{V}_{O}}{{V}_{O}+\sqrt{2}N{V}_{rms}^{HL}},$$

The maximum switch average current ${I}_{DS1(av)}^{\mathrm{max}}$ occurs at the maximum load and the minimum line voltage, when power factor is approximately unity, the maximum switch average current ${I}_{DS1(av)}^{\mathrm{max}}$ is written by
where ${P}_{O}^{FL}$ is output power of the proposed converter operated in the full load condition. Its worst case maximum peak current also occurs under the same operating conditions as above. The peak current ${I}_{DS1(peak)}^{\mathrm{max}}$ can be calculated from
where L

$${I}_{DS1(av)}^{\mathrm{max}}=\frac{\sqrt{2}{P}_{O}^{FL}}{\eta {V}_{rms}^{LL}},$$

$${I}_{DS1(peak)}^{\mathrm{max}}=\frac{\sqrt{2}{P}_{O}^{FL}}{\eta {D}_{\mathrm{min}}^{LL}{V}_{rms}^{LL}}+\frac{\sqrt{2}{V}_{rms}^{LL}{D}_{\mathrm{min}}^{LL}{T}_{S}}{2{L}_{m}},$$

_{m}is the magnetizing inductance of transformer T_{r}and T_{S}is the switching period of switch M_{1}or M_{3}. For this particular design, since voltage stress and peak current of active clamp switch M_{2}or M_{4}are the same as that of switch M_{1}or M_{3}, device selection of switch M_{2}or M_{4}is the same as M_{1}or M_{3.}● Transformer T

_{r}Since input voltage changes from a low line voltage ${V}_{rms}^{LL}$ to a high line voltage ${V}_{rms}^{HL}$, it will affect the minimum duty cycle ${D}_{\mathrm{min}}^{LL}$ and ${D}_{\mathrm{min}}^{HL}$. In order to obtain a reasonable value of ${D}_{\mathrm{min}}^{LL}$ or ${D}_{\mathrm{min}}^{HL}$ for active clamp flyback converter, ${D}_{\mathrm{min}}^{LL}$ or ${D}_{\mathrm{min}}^{HL}$ is designed at between 0.3 and 0.5. According to the reasonable ranges of ${D}_{\mathrm{min}}^{LL}$ or ${D}_{\mathrm{min}}^{HL}$, turns ratio N is determined by
Or

$$N=\frac{(1-{D}_{\mathrm{min}}^{LL}){V}_{O}}{\sqrt{2}{D}_{\mathrm{min}}^{LL}{V}_{rms}^{LL}},$$

$$N=\frac{(1-{D}_{\mathrm{min}}^{HL}){V}_{O}}{\sqrt{2}{D}_{\mathrm{min}}^{HL}{V}_{rms}^{HL}},$$

The input voltage V

_{in}adopts a sine wave. During the positive half period or the negative half period, input voltage V_{in}can vary from 0 V to the maximum value, and then from the maximum value to 0 V. In order to determine magnetizing inductance L_{m1}(=L_{m}) or L_{m2}(=L_{m}), current variation value △I_{Lm}of magnetizing inductance L_{m1}or L_{m2}is determined with the worst case maximum peak switch current as a reference value. Therefore, △I_{Lm}can be written by
$$\Delta {I}_{Lm}=K{I}_{DS1(peak)}^{\mathrm{max}}=K(\frac{\sqrt{2}{P}_{O}^{FL}}{\eta {D}_{\mathrm{min}}^{LL}{V}_{rms}^{LL}}+\frac{\sqrt{2}{D}_{\mathrm{min}}^{LL}{V}_{rms}^{LL}{T}_{S}}{2{L}_{m}}).$$

For this particular design, K is determined at approximately 0.1.

● Clamp Capacitor C

_{C}Since switches M
where L

_{1}–M_{4}are operated with ZVS at turn-on transition and the energy stored in leakage inductance L_{K}can be recycled, it is by means of leakage inductance L_{K}and clamp capacitor C_{C}operated in the resonant manner. A better design of the proposed converter is to select the clamp capacitor C_{C}value so that one half of the resonant period formed by the clamp capacitor C_{C}and leakage inductance L_{K}exceeds the maximum off time of switch M_{1}or M_{3}. Therefore, clamp capacitor C_{C}can be determined by
$${C}_{C}\approx \frac{{(1-{D}_{\mathrm{min}}^{LL})}^{2}{T}_{S}^{2}}{{\pi}^{2}{L}_{K}}\text{}$$

_{K}is equal to 1~5% of magnetizing inductance L_{m1}or L_{m2}.● Output Capacitor C

_{o}The output capacitor C
where ${P}_{o}^{\mathrm{max}}$ (=${P}_{o}^{FL}$) is the maximum output power. Furthermore, the required ripple current rating ${I}_{CO(rms)}^{\mathrm{max}}$ for output capacitor is determined by

_{o}is used to reduce output voltage ripple. Since the input voltage V_{in}of the proposed converter is a half-wave rectification waveform, output voltage V_{o}contains a voltage ripple with 120 Hz. When the maximum peak output voltage △V_{o}is specified, output capacitor C_{o}can be given by
$${C}_{o}=K\frac{{P}_{o}^{\mathrm{max}}}{240\pi {V}_{o}\Delta {V}_{O}},$$

$${I}_{CO(rms)}^{\mathrm{max}}=\frac{{P}_{o}^{\mathrm{max}}}{\sqrt{2}{V}_{O}}.$$

## 5. Measured Results

In order to verify performances of the proposed power system, as shown in Figure 8, a prototype with following specifications was implemented. The proposed power system includes two converters: The DC/DC converter with battery source and the proposed PFC with line source. Their specifications are respectively shown in the following:

- The DC/DC converter with battery sourceInput Voltage V
_{B}: DC 20–26 V (two batteries connected in series),Switching frequency f_{s}: 50 kHz,Output Voltage V_{DC1}: DC 48 V,Maximum output current I_{DC1}_{(max)}: 2.5 A, andMaximum output power P_{DC1}_{(max)}: 120 W, - The proposed PFC with line sourceInput voltage V
_{in}: AC 90–265 V,Switching frequency f_{s}: 50 kHz,Output Voltage V_{DC2}: DC 50 V,Maximum output current I_{DC2}_{(max)}: 6 A,Maximum output power P_{DC2}_{(max)}: 300 W,

According to the previous specifications, the design values of the key components of the proposed power system can be determined. The DC/DC converter with battery source is shown in Figure 14 and the proposed PFC with line source is shown in Figure 6. According to design of the proposed flyback converter, parameter values in the proposed one is listed in Table 3. Semiconductor selection of the proposed one is illustrated in Table 4. Their devices are determined as follows:

- The DC/DC converter with battery sourceSwitches M
_{1}, M_{2}: IRFP250,Diodes D_{1}, D_{2}: SR10100,Inductances L_{1}, L_{2}: 230 μH, andCapacitor C_{DC1}: 1000 μF, - The proposed PFC with line sourceSwitches M
_{1}–M_{4}: IRG4PH50KDPbF,Transformer T_{r}core: EE-55,Diode D_{2}: 40EPF06PbF,Output capacitor C_{O}: 2200 μF/63 VDiodes D_{1}, D_{3}: HFA08TB60,Capacitors C_{1}, C_{2}: 0.1 μF/630 V,Clamp capacitor C_{C}: 0.47 μF,Turns ratio N of transformer T_{r}: 0.5,D^{LL}_{min}: 0.43, andMagnetizing inductances L_{m1}, L_{m2}: 2.72 mH,

Since this paper focuses on design and implementation of the bridgeless flyback converter, measured results of the DC/DC converter with battery source have only shown that output voltage V

_{DC1}and current I_{DC1}under step-load changes and under supplying power to load in parallel connection. Measured output voltage V_{DC1}and current I_{DC1}waveforms under step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1s is shown in Figure 15. From Figure 15, it can be seen that the voltage regulation of output voltage V_{DC1}has been limited within ±1%.For the proposed PFC, since the input voltage V

_{in}of AC 90 V is the worst case for operational states of the proposed one, the experimental results are shown with the input voltage of AC 90 V. Measured waveforms of input voltage V_{in}and current I_{i}is shown in Figure 16 under the line source of AC 90 V. Figure 16a shows those waveforms under 10% of full load condition and Figure 16b illustrates those waveforms under 100% of full load condition. From Figure 16, it can be found that input voltage V_{in}and current I_{i}are approximately in phase. Figure 17a illustrates measured waveforms of voltages V_{C1}, V_{C2}and currents I_{D1}, I_{D3}under 50% of full load condition and the input voltage of 90 V, while Figure 17b shows measured waveforms of voltage V_{C1}and current I_{D1}. From Figure 17, it can be seen that waveforms of currents I_{D1}and I_{D3}follow ones of voltages V_{C1}and V_{C2}variation, respectively. Since duty ratio D varies from 0.204 to 1, and the proposed flyback converter is operated in DCM or CCM. Figure 18 and Figure 19 show measured waveforms of switch voltage V_{DS}and current I_{DS}under input voltage of 90 V. Figure 18 illustrates measured waveforms of switch voltage V_{DS1}and current I_{DS1}, and switch voltage V_{DS2}and current I_{DS2}and current I_{DS2}under 10% of full load condition and the input voltage of 90 V. From Figure 18, it can be found that the proposed flyback converter is operated in DCM. The active clamp capacitor can reduce the voltage spike and recover energy stored in leakage inductor of the transformer. Figure 19 depicts those waveforms under 30% of full load condition and the input voltage of 90 V, from which it can be seen that switches M_{1}and M_{2}are operated in ZVS at turn-on transition. In Figure 18 and Figure 19, voltage V_{DS1}across switch M_{1}has a ring voltage. The ring voltage is generated by leakage inductor of secondary winding of transformer and parasitic capacitor of diode D_{2}when switch M_{1}is turned on. It can be eliminated by snubber circuit applied to diode D_{2}.Measured output voltage V

_{DC2}and current I_{DC2}waveforms under step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1s as shown in Figure 20, from which it can be observed that the voltage regulation of output voltage V_{DC2}has been limited within ±1%. Figure 21 depicts the measured efficiency of the proposed PFC from light load to heavy load under AC 90 V. When load is greater than 40% of full load condition, each efficiency is greater than 86%. For further increase in conversion efficiency of the proposed converter, switches M_{1}–M_{4}can adopt a lower conduction resistance to reduce conduction loss. It also decreases the switching frequency of the switch to reduce switching loss. In order to verify a high PF, the plot of power factor of the proposed one from light load to heavy load illustrated in Figure 22, from which it can be found that power factor of the proposed one can be greater than 0.8 under different input voltages. In particular, when input voltage is at a high line level and load is in the light load, PF has a lower value. Due to a lower output current I_{DC2}, PFC control IC is difficult to control input current I_{i}, resulting in a lower PF. Figure 23 shows the harmonic current from light load to heavy load under different input voltage levels, illustrating that their harmonic current can meet requirements of IEC6100-3-2 class A.According to operational cases of the proposed power system, there are four operational cases for DC load power variations. Figure 24 shows measured waveforms of voltages V

_{DC1}and V_{DC2}, and currents I_{DC1}and I_{DC2}from P_{L}= 0 W to P_{L}= 125 W. Due to P_{DC2}_{(max)}= 300 W, operational case changes of the proposed one can be varied from case I to case II. When load power P_{L}is from 0 W to 325 W, operational case changes are from case I to case III. Those waveforms are shown in Figure 25. If P_{L}variations are from 0 W to 450 W, operational case charges are from case I to case IV. Those waveforms are shown in Figure 26. As mentioned above, the proposed power system can change operational case by the control algorithm of the proposed power system.## 6. Conclusions

This paper proposes a power system for DC load applications. The proposed power system adopts the DC/DC converter with battery source and the proposed PFC to supply power for DC loads of 48 V power system. The proposed PFC uses a bridgeless flyback converter to achieve a high PF. In this paper, operational principle and design of the proposed one have been described in detail. According to the experimental results, switches M

_{1}and M_{2}of the proposed PFC can be operated with ZVS at turn-on transition. Furthermore, the proposed one can also achieve a lower harmonic current, a higher conversion efficiency and a higher PF. Its harmonic current from light load to heavy load under different input voltage levels can meet the requirements of IEC6100-3-2 class A. Therefore, the proposed bridgeless flyback converter has been implemented to apply to the utility line system as a power factor corrector. In addition, the proposed power system for DC loads of 48 V power system also has been implemented to verify its feasibility. It is suitable for a DC distribution of 48 V power system application.## Author Contributions

S.-Y.T. conceptualized the study, wrote the original draft and acquired funding; P.-J.H. and D.-H.W. did experiments and analyzed data.

## Funding

The authors gratefully acknowledge the financial support (MOST 105-2221-E-182-046-MY3) of the Ministry of Science and Technology, Taiwan, R.O.C.

## Conflicts of Interest

The authors declare no conflict of interest.

## References

- Prabhala, V.A.K.; Baddipadiga, B.P.; Ferdowsi, M. DC Distribution Systems—An Overview. In Proceedings of the International Conference on Renewable Energy Research and Applications, Milwaukee, WI, USA, 19–22 October 2014; pp. 307–312. [Google Scholar]
- Choi, H.; Balogh, L. A Cross-Coupled Master-Slave Interleaving Method for Boundary Conduction Mode (BCM) PFC Converters. IEEE Trans. Power Electron.
**2012**, 27, 4202–4211. [Google Scholar] [CrossRef] - Bist, V.; Singh, B. An Adjustable-Speed PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive. IEEE Trans. Ind. Electron.
**2014**, 61, 2665–2677. [Google Scholar] [CrossRef] - Roh, Y.-S.; Moon, Y.-J.; Park, J.; Yoo, C. A Two-Phase Interleaved Power Factor Correction Boost Converter with a Variation-Tolerant Phase Shifting Technique. IEEE Trans. Power Electron.
**2014**, 29, 1032–1040. [Google Scholar] - Zhang, F.; Xu, J. A Novel PCCM Boost PFC Converter with Fast Dynamic Response. IEEE Trans. Power Electron.
**2011**, 58, 4207–4216. [Google Scholar] [CrossRef] - Jang, Y.; Jovanovic, M.M. Interleaved Boost Converter with Intrinsic Voltage-doubler Characteristic for Universal-line PFC Front End. IEEE Trans. Power Electron.
**2007**, 22, 1394–1401. [Google Scholar] [CrossRef] - Xie, X.; Wang, J.; Zhao, C.; Lu, Q.; Liu, S. A Novel Output Current Estimation and Regulation Circuit for Primary Side Controlled High Power Factor Single-stage Flyback LED Driver. IEEE Trans. Power Electron.
**2012**, 27, 4602–4612. [Google Scholar] [CrossRef] - Baek, J.-I.; Kim, J.-K.; Lee, J.-B.; Youn, H.-S.; Moon, G.-W. A Boost PFC Stage Utilized as Half-Bridge Converter for High-Efficiency DC–DC Stage in Power Supply Unit. IEEE Trans. Power Electron.
**2017**, 32, 7449–7457. [Google Scholar] [CrossRef] - Mallik, A.; Khaligh, A. Control of a Three-Phase Boost PFC Converter Using a Single DC-Link Voltage Sensor. IEEE Trans. Power Electron.
**2017**, 32, 6481–6492. [Google Scholar] [CrossRef] - Reddy, U.R.; Narasimharaju, B.L. Single-stage electrolytic capacitor less non-inverting buck-boost PFC based AC–DC ripple free LED driver. IET Power Electron.
**2017**, 10, 38–46. [Google Scholar] [CrossRef] - Alam, M.; Eberle, W.; Gautam, D.S.; Botting, C. A Soft-Switching Bridgeless AC–DC Power Factor Correction Converter. IEEE Trans. Power Electron.
**2017**, 32, 7716–7726. [Google Scholar] [CrossRef] - Alam, M.; Eberle, W.; Gautam, D.S.; Botting, C.; Dohmeier, N.; Musavi, F. A Hybrid Resonant Pulse-Width Modulation Bridgeless AC–DC Power Factor Correction Converter. IEEE Trans. Ind. Appl.
**2017**, 53, 1406–1415. [Google Scholar] [CrossRef] - Lee, S.-W.; Do, H.-L. Single-Stage Bridgeless AC–DC PFC Converter Using a Lossless Passive Snubber and Valley Switching. IEEE Trans. Ind. Electron.
**2016**, 63, 6055–6063. [Google Scholar] [CrossRef] - Wu, X.; Wang, Z.; Zhang, J. Design Considerations for Dual-output Quasi-resonant Flyback LED Driver with Current-sharing Transformer. IEEE Trans. Power Electron.
**2013**, 28, 4820–4830. [Google Scholar] [CrossRef] - Zengin, S.; Deveci, F.; Boztepe, M. Decoupling Capacitor Selection in DCM Flyback PV Microinverters Considering Harmonic Distortion. IEEE Trans. Power Electron.
**2013**, 28, 816–825. [Google Scholar] [CrossRef] - Hsieh, Y.-C.; Chen, M.-R.; Cheng, H.-L. An Interleaved Flyback Converter Featured with Zero-voltage Transition. IEEE Trans. Power Electron.
**2011**, 26, 79–84. [Google Scholar] [CrossRef] - Lo, Y.-K.; Lin, J.-Y. Active-clamping ZVS Flyback Converter Employing Two Transformers. IEEE Trans. Power Electron.
**2007**, 22, 2416–2423. [Google Scholar] [CrossRef] - Baek, J.; Shin, J.; Jang, P.; Cho, B. A Critical Conduction Mode Bridgeless Flyback Converter. In Proceedings of the International Conference on Power Electronics, Jeju, Korea, 30 May–3 June 2011; pp. 487–492. [Google Scholar]
- Chen, X.; Jiang, T.; Huang, X.; Zhang, J. A High Efficiency Bridgeless Flyback PFC Converter for Adapter Application. In Proceedings of the IEEE Applied Power Electronics Conference and Exposition, Long Beach, CA, USA, 17–21 March 2013; pp. 1013–1017. [Google Scholar]
- Chang, H.-H.; Tseng, S.-Y.; Huang, J.G. Interleaving Boost Converters with a Single-Capacitor Turn-Off Snubber. In Proceedings of the IEEE Power Electronic Specialists Conference, Jeju, Korea, 18–22 June 2006; pp. 1–7. [Google Scholar]

**Figure 5.**Schematic diagram of a bridgeless flyback converter with an active clamp circuit for PFC applications.

**Figure 7.**Plot of the B-H curve of transformer T

_{r}(

**a**) in the conventional flyback converter, and (

**b**) in the conventional bridgeless flyback converter for PFC applications.

**Figure 9.**Conceptual waveforms of voltage V

_{C1}and current I

_{D1}: (

**a**) Under a complete line period, and (

**b**) under a positive half period.

**Figure 11.**Schematic diagram of the proposed bridgeless flyback operated in (

**a**) positive, and (

**b**) negative half periods.

**Figure 12.**Equivalent circuit of the proposed bridgeless flyback converter operated in CCM over one switching cycle during the positive half period of the input source.

**Figure 15.**Measured output voltage V

_{DC1}and current I

_{DC1}waveforms of step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1 s.

**Figure 16.**Measured waveforms of input voltage V

_{in}and input current I

_{i}under the line source of AC 90 V: (

**a**) 10% of full load condition, and (

**b**) 100% of full load condition.

**Figure 17.**Measured waveforms of (

**a**) voltages V

_{C1}, V

_{C2}and currents I

_{D1}, I

_{D3}, and (

**b**) voltage V

_{C1}and current I

_{D1}under 50% of full load condition and the input voltage of 90 V.

**Figure 18.**Measured waveforms of (

**a**) switch voltage V

_{DS1}and current I

_{DS1}, and (

**b**) switch voltage V

_{DS2}and current I

_{DS2}and current I

_{DS2}under 10% of full load condition and the input voltage of 90 V.

**Figure 19.**Measured waveforms of (

**a**) switch voltage V

_{DS1}and current I

_{DS1}, and (

**b**) switch voltage V

_{DS2}and current I

_{DS2}and current I

_{DS2}under 30% of full load condition and the input voltage of 90 V.

**Figure 20.**Measured output voltage V

_{DC2}and current I

_{DC2}waveforms of step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1 s.

**Figure 21.**Measured efficiency of the proposed bridgeless flyback converter from light load to heavy load under 90 V.

**Figure 22.**Plot of power factor of the proposed PFC from light load to heavy load under different input voltages.

**Figure 23.**Plots of harmonic current at light load and heavy load (

**a**) under input voltage of 90 V, and (

**b**) under input voltage of 265 V.

**Figure 24.**Operational state charges of the proposed power system from case I to case II under P

_{L}= 125 W.

**Figure 25.**Operational state charges of the proposed power system from case I to case VI under P

_{L}= 325 W.

**Figure 26.**Operational state charges of the proposed power system from case III to case IV under P

_{L}= 450 W.

Cases | Power Distribution | Operational Conditions | ||
---|---|---|---|---|

DC/DC Converter with Battery Source | The Proposed PFC | DC/DC Converter with Battery Source | The Proposed PFC | |

P_{L} = 0 W | P_{B} = 0 W | P_{DC2} = 0 W | shutdown | shutdown |

0 < P_{L} ≤ P_{DC2}_{(max)} | P_{B} = 0 W | P_{DC2} = P_{L} | work | work |

P_{DC2}_{(max)} < P_{L} ≤ P_{DC2}_{(max)} + P_{B}_{(max)} | P_{B} = P_{L} − P_{DC2}_{(max)} | P_{DC2} = P_{DC2}_{(max)} | work | work |

P_{L} > P_{DC2}_{(max)} + P_{B}_{(max)} | P_{B} = 0 W | P_{DC2} = 0 W | shutdown | shutdown |

Symbol | Definition | Expression |
---|---|---|

P_{B} | Output power of the DC/DC converter with battery source | P_{B} = V_{B}I_{B} |

P_{L} | Load power | P_{L} = V_{DC}I_{DC} |

I_{DC2} | Output current of the proposed PFC | I_{DC2} ≤ I_{DC2}_{(max)} |

I_{DC2}_{(max)} | Output maximum current of the proposed PFC | - |

V_{B} | Voltage of battery | V_{B} ≥ V_{B}_{(min)} |

V_{B}_{(min)} | The minimum work voltage of battery | - |

I_{B} | Discharge current of battery | I_{B} ≤ I_{B}_{(max)} |

I_{B}_{(max)} | The maximum discharge current of battery | - |

P_{B}_{(max)} | The maximum output power of battery | P_{B}_{(max)} = V_{B}I_{B}_{(max)} |

V_{i} | Input voltage of the line source | - |

V_{i}_{(min)} | The minimum input voltage of the line source | V_{i}_{(min)} < AC 90 V |

I_{i} | Input current of the line source | I_{i} ≤ I_{i}_{(max)} |

I_{i}_{(max)} | The maximum work current of the line source | - |

V_{DC} | Output voltage of the proposed power system | - |

I_{DC} | Output current of the proposed power system | I_{DC} ≤ I_{DC}_{(max)} |

I_{DC}_{(max)} | Output maximum current of the proposed power system | - |

P_{DC2}_{(max)} | The maximum output power of the proposed PFC | P_{DC}_{2}_{(max)} = V_{DC2}I_{DC2}_{(max)} |

P_{DC2} | Output power of the proposed PFC | P_{DC}_{2} = V_{DC2}I_{DC2} |

Parameter | Design Value | Experimental Value | Design Value by Equation | Conditions |
---|---|---|---|---|

I_{av}(Φ) | 5.55sin(Φ) A | - | (2) | η = 85%, V_{rms} = 90 V, P_{O} = 300 W |

${D}_{\mathrm{min}}^{LL}$ | 0.43 | - | (5) | V_{O} = 48 V, ${V}_{rms}^{LL}$ = 90 V, N = 0.5 |

${D}_{\mathrm{min}}^{HL}$ | 0.204 | - | (6) | V_{O} = 48 V, ${V}_{rms}^{HL}$ = 265 V, N = 0.5 |

${I}_{DS1(av)}^{\mathrm{max}}$ | 5.5 A | - | (7) | η = 85%, ${V}_{rms}^{LL}$ = 90 V, ${P}_{O}^{\mathrm{F}L}$ = 300 W |

${I}_{DS1(peak)}^{\mathrm{max}}$ | 13.1 A | - | (8) | η = 85%, ${V}_{rms}^{LL}$ = 90 V, ${P}_{O}^{FL}$ = 300 W, L_{m} = 2.72 mH, ${D}_{\mathrm{min}}^{LL}$ = 0.43, T_{S} = 20 μs |

C_{C} | 0.41 μF | 0.47 μF | (12) | L_{K} = 32 μH, ${D}_{\mathrm{min}}^{LL}$ = 0.43, T_{S} = 20 μs |

C_{O} | 1730 μF | 2200 μF | (13) | K = 0.1, V_{O} = 48 V, ΔV_{O} = 0.48 V, ${P}_{O}^{\mathrm{max}}$ = 300 W |

Component | Design Maximum Voltage/Current Ratings | Component Selection and Voltage/Average Current/Peak Current |
---|---|---|

M_{1}–M_{4} | 470 V/13.1 A | IRG4PH50KDPbF 1200 V/24 A/90 A |

D_{1}–D_{3} | 375 V/13.1 A | HFA08TB60 600 V/8 A/60 A |

D_{2} | 235 V/19.87 A | 40EPF06PbF 600 V/10 A/40 A |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).