High-Voltage Gain Single-Switch Quadratic Semi-SEPIC Converters for Powering High-Voltage Sensors Suitable for Renewable Energy Systems and Industrial Automation with Low Voltage Stresses

Abstract

This paper presents two new non-isolated DC-DC converters with and without a coupled inductor based on quadratic voltage conversion. Firstly, the coupled inductor-less type is explained in detail. It employs a voltage-boosting cell and a modified SEPIC structure to provide a high voltage boost ability with a lower and practical value for the switching duty cycle. This allows for lower power loss compared to conventional DC-DC converters. Having only one switch in the proposed converter simplifies the control and reduces the required number of control signals. Furthermore, the presented transformer-less structure can help avoid producing huge voltage spikes across the power switch. In traditional quadratic SEPIC converters, the voltage-boosting cell’s capacitor experiences relatively high voltage stress due to the voltage multiplication process. In contrast, the proposed converter offers significantly lower voltage stresses. Hence, it becomes possible to utilize a capacitor with a lower voltage rating, leading to cost savings and improved reliability and availability of suitable components. The first topology can be improved for ultrahigh voltage applications by replacing the middle inductor with a coupled transformer. Consequently, a higher voltage range with a lower switching duty cycle can be attained. Theoretical analysis and mathematical derivations are provided, and the comparison section claims the proposed converter’s ability to minimize voltage stress across the switch and output diode. Finally, experimental results are given to verify the effectiveness of the proposed converters at an output power of 260 W.

1. Introduction

Overexploitation of fossil fuels has led to significant environmental problems. To promote energy conservation and reduce emissions, renewable energy sources like fuel cells and photovoltaic (PV) panels are seen as viable alternatives to reduce reliance on fossil fuels. Step-up converters are commonly used in renewable energy systems to raise the voltage of the power generated by solar panels to a level that can be used by a system’s load or stored in a battery, as shown in Figure 1 [1]. LED lights and medical equipment, such as ultrasound and X-ray machines, achieve precise and stable power supplies using boost converters. Research in power electronics focuses on enhancing DC-DC boost converters with increased voltage gain, efficiency, reliability, and optimal component utilization.

Multistage DC-AC-DC conversion uses more power switches, increasing power losses and degrading efficiency. Non-isolated DC-DC converters address the drawbacks associated with isolated DC-DC converters [2,3,4,5]. These topologies offer several advantages, such as improved efficiency and performance, lower cost, compact size, and ease of control. These circuits either have common ground or separate grounds for the input and output. Common-ground non-isolated DC-DC converters enhance system performance by eliminating leakage current. The traditional non-isolated boost converter is a popular boost converter. With a voltage gain of 2.5–5, it is an attractive option for low-conversion ratio applications due to its simple configuration and reduced number of components. A high step-up converter is required to raise the low voltage output of fuel cells for use in electric vehicles and distributed power systems. Likewise, the switch and diode are subjected to high voltage stresses equivalent to the DC bus or output voltage. Despite these limitations, traditional boost converters remain popular for many applications. Besides the traditional boost converter, the SEPIC-based configurations are mainly utilized to amplify the input voltage of renewable energy sources [6]. Additionally, the SEPIC converter in [6] exhibits lower voltage stress on the switches, a non-inverting output voltage, and a continuous input current, making it suitable for renewable energy and fuel cell applications. However, the adoption of two switches increases the conduction losses. Some SEPIC converters have lower voltage gain in comparison to other known topologies like quadratic boost converters (QBCs) [7]. Furthermore, in [8], an improved SEPIC converter that can achieve a higher voltage gain is suggested. Nonetheless, the semiconductor elements experience higher voltage stresses. For further increase in voltage gain, a coupled inductor-based SEPIC converter is introduced in [9]; this single-switch SEPIC-based topology with a coupled inductor and voltage multiplier has a continuous input current. However, the coupled inductor causes the switch to experience voltage spikes.

QBCs are non-isolated DC-DC converters renowned for providing higher gain than SEPIC converters. The high voltage stress on the switch and the output diode, equivalent to the output voltage, is one of the drawbacks. Minimizing the impacts of these drawbacks has led to the development of many other QBCs [10,11,12,13,14,15,16]. Paper [10] proposes a QBC with a non-pulsating input current and a relatively low inductor current. However, it adopts two power switches, increasing the switching and conduction losses, and thereby lowering efficiency. In [11], an interleaved QBC developed from two conventional QBCs with high voltage gain is proposed. This topology also employs two switches, which increases the conduction losses and the number of passive elements. In [12], a QBC with reduced output voltage ripple and a high power density is suggested. However, the numerous switches make the control cumbersome and reduce efficiency. In [17], a QBC based on stackable switching stages is suggested to obtain a higher gain. However, the switch and the diodes experience a voltage stress equivalent to the output voltage.

Magnetic coupling is also a major technique adopted to achieve higher voltage gain in non-isolated converters [18,19,20,21,22,23]. Nonetheless, there is a voltage overshot on the switches during the turn-off process, requiring higher voltage rating switches and additional clamping circuits to be employed.

The application of the quadratic converter by incorporating switched capacitors is presented in [24]. However, the use of switched capacitors adds extra circuit elements [25]. Also, a cascaded structure can be utilized to achieve a higher step-up voltage gain [26,27,28,29,30]. Nevertheless, these structures require more switches, leading to a complex control scheme, higher switching and conduction losses, and reduced efficiency. In [31], a family of non-isolated transformer-less single-switch dual inductor high-voltage gain boost converters are introduced. However, their voltage gains are lower than those of other topologies like the QBC. With the same voltage gain, [32] uses two semiconductor switches. The additional switch reduces efficiency. In [33,34,35,36,37,38], buck–boost topologies with quadratic features have been proposed. One main challenge of designing buck–boost converters is the complexity of the control circuitry. The converter’s switching frequency and duty cycle must be carefully optimized to ensure efficient operation to avoid issues such as voltage spikes and electromagnetic interference.

Adopting the proposed high-gain DC-DC converter for sensor applications offers significant advantages, particularly in scenarios requiring efficient and stable high-voltage operation. Its transformer-less design minimizes voltage spikes and reduces power losses, ensuring reliable power delivery to sensors. The converter’s ability to achieve a high voltage boost with a practical switching duty cycle enhances its compatibility with low-voltage input sources, making it ideal for powering high-voltage sensors in renewable energy systems, electric vehicles, and industrial automation. Furthermore, the reduced voltage stress on components improves the system’s reliability and cost-effectiveness, while the single-switch configuration simplifies control, making it a practical and efficient choice for advanced sensor integration.

This paper presents a novel non-isolated common-ground single-switch quadratic semi-SEPIC boost converter and its coupled inductor-based counterpart. The proposed converters are designed to operate effectively in the 100-watt to 1.2-kilowatt range, making them suitable for medium-power applications, such as battery charging systems, renewable energy interfaces, and electric vehicle auxiliaries. The proposed converter shown in Figure 2a has a high gain and a continuous input current. The proposed converter uses only one switch. Therefore, it has fewer switching and conduction losses, thereby improving efficiency. The subsequent segments of this paper are organized as follows: Section 2 offers a comprehensive description of the circuit topology of the proposed converter without a coupled inductor, encompassing fundamental principles and operational modes in CCM. In Section 3, DCM analysis is presented. In Section 4, considerations about the design of the converter components are discussed. Magnetic coupling applied to the proposed converter is studied in Section 5. Section 6 provides a comparative analysis of the proposed converter and other topologies. Experimental results are discussed in Section 7, and Section 8 concludes this work.

2. Proposed Quadratic Semi-SEPIC DC-DC Converter

A.

Circuit Topology

The proposed non-isolated quadratic boost DC-DC converter is depicted in Figure 2a. It features one MOSFET switch ($S_1$), three external diodes ($D_1-D_3$), one output diode ($D_o$), three inductors ($L_1-L_3$), three capacitors ($C_1-C_3$), and an output capacitor ($C_o$). $L_1$ is the input inductor, and $C_1$ is a buffer capacitor. While $V_{in }$is the input source DC voltage, $V_o$ is the output voltage across the load, R. $D_3$ and $C_3$ provide enhanced voltage-boosting capability. The incorporation of this arrangement offers several appealing benefits, including continuous input current. The topology boasts an uncomplicated control circuitry, the ability to boost voltage to high levels, a broad range of duty cycle control, low power losses during switching, and optimal utilization of the input DC source. The switch and diodes experience less voltage stress. The common ground between the input and output eliminates leakage current.

B.

Modes of Operation in CCM

The proposed converter operates in two modes. Mode 1 is when the switch is turned on and Mode 2 is when the switch is turned off for a single switching period. Analysis of the converter in continuous conduction mode (CCM) is first presented. The operational principle of the proposed converter is explained assuming the following: (a) all the components of the circuit, including inductors, capacitors, diodes, and the MOSFET switch, are ideal and have negligible series resistance; (b) any voltage drops across diodes, parasitic capacitance, and on resistance of the switch are disregarded; and (c) all capacitors are sufficiently large to maintain a consistent voltage without any variations.

Mode 1$({DT}_s)$: See Figure 2b. $S_1$ is turned on for the duty ratio, D, of the switching period, $T_s$. $D_1$, $D_3$, and $D_o$ are reverse-biased, while only $D_2$ is forward-biased. A closed loop is formed by $V_{in}$, $L_1$, $D_2$, and $S_1$. The resulting current, $i_{L_1}$, flows through $L_1$. In parallel, another closed loop is created by $V_{in}$, $C_1$, $L_2$, and $S_1$. The subsequent inductor current, $i_{L_2}$, flows through this loop. A third closed loop is created by $C_2$, $L_3$, $C_3$, and $S_1$. The inductor current, $i_{L_3}$, flows through this closed loop. $C_o$ discharges to the output. Figure 2a displays critical waveforms of the proposed quadratic converter in CCM, showing the continuous nature of all inductor currents.

By applying KVL on the first loop ($V_{in}-L_1-D_2-S_1-V_{in}$), $V_{L_1}$, across $L_1$ during the active time of the switch $({DT}_s)$ and the ensuing increasing linear current,$i_{L_1}$, is expressed as

$$V_{L_1}=V_{in}, {di}_{L_1}={\displaystyle \frac{V_{in}}{L_1}}dt$$

(1)

For the second ($V_{in}-C_1-L_2{-S}_1-V_{in}$), the result of $V_{in}$ and $V_{C_1}$ is seen across$L_2$. Therefore, $V_{L_2}$ across $L_2$ and the corresponding linear current, $i_{L_2}$, are

$$V_{L_2}=V_{in}+V_{C_1}, {di}_{L_2}={\displaystyle \frac{V_{in}+V_{C_1}}{L_2}}dt$$

(2)

From Figure 2b, ($C_2-L_3-C_3-S_1-C_2$), the voltage, $V_{L_3}$, developed across $L_3$ and its corresponding current, $i_{L_3}$, are expressed as

$$V_{L_3}=V_{C_3}-V_{C_2}, {di}_{L_3}={\displaystyle \frac{V_{C_3}-V_{C_2} }{L_3}}dt$$

(3)

All three closed loops share the active switch, $S_1$. The switch current, $i_s$, and the input current are

$$i_s=i_{L_1}+i_{L_2}+i_{L_3}, i_{in}=i_{L_1}+i_{L_2}$$

(4)

In this mode, the capacitors’ currents, according to Figure 2b, are given by the expressions

$$i_{C_1}=C_1{\displaystyle \frac{d{V}_{C_1}}{dt}}=-i_{L_2}=i_{L_1}-i_{in}, i_{C_2}=C_2{\displaystyle \frac{d{V}_{C_2}}{dt}}=i_{L_3}, i_{C_3}=C_3{\displaystyle \frac{d{V}_{C_3}}{dt}}=-i_{L_3}, i_{C_O}=-{\displaystyle \frac{V_O}{R}}$$

(5)

Mode 2$(1-D)T_s$: See Figure 2c. $S_1$ is turned off and $D_1$, $D_3$, and $D_o$ are forward-biased, while $D_2$ is reverse-biased. A closed path is formed by $C_1$ and $L_1$. As a result, $V_{C_1}$ is built across $L_1$. In parallel, a closed loop is formed by $V_{in}$, $C_1$, $C_2$, $L_2$, and $C_o$. A third loop is created by $C_2$ and $L_3$. $V_{C_2}$ is developed across $L_3$. An alternative loop for $L_3$ is created by $C_3$, $L_3$, and $C_o$.

For $(1-D)T_s$, the voltage across $L_1$ and the resulting current,$i_{L_1}$, are expressed as

$$V_{L_1}={-V}_{C_1}, {di}_{L_1}={\displaystyle \frac{{-V}_{C_1} }{L_1}}dt$$

(6)

The voltage developed across $L_2$ and its corresponding linear current, $i_{L_2}$, are

$$V_{L_2}=V_{in}+V_{C_1}+V_{C_2}-V_o, {di}_{L_2}={\displaystyle \frac{V_{in}+V_{C_1}+V_{C_2}-V_o }{L_2}}dt$$

(7)

The electrical expressions for $V_{L_3}$ and the subsequent current,$I_{L_3}$, are defined as

$$V_{L_3}=-V_{C_2}=V_{C_3}-V_o, {di}_{L_3}={\displaystyle \frac{V_{C_3}-V_o }{L_3}}dt$$

(8)

In this mode, the circuit in Figure 2c shows that the currents flowing through the capacitors can be described as follows.

$$i_{C_1}=C_1{\displaystyle \frac{d{V}_{C_1}}{dt}}={i_{L_1}-i}_{L_2}, i_{C_2}-i_{C_3}=C_2{\displaystyle \frac{d{V}_{C_2}}{dt}}={i_{L_3}-i}_{L_2}, i_{C_O}=i_{L_3}-i_{C_2}-{\displaystyle \frac{V_O}{R}}$$

(9)

By applying the volt-second balance condition on $L_1$, $L_2$, and $L_3$, the equations below are obtained.

$$\left\{\begin{array}{c}{V}_{L_{1avg}}=V_{in}D {-V}_{C_1}\left(1-D\right)=0\\ V_{L_{2avg}}=\left(V_{in}+V_{C_1}\right)D+\left(V_{in}+V_{C_1}+V_{C_2}-V_o \right)\left(1-D\right)=0\\ V_{L_{3avg}}={(V}_{C_3}-V_{C_2})D+{(V}_{C_3}-V_o)(1-D)=0\end{array}\right.$$

(10)

The voltage stresses on the capacitors and the output voltage gain in CCM are calculated. From (10), the normalized capacitor voltage stresses are as follows:

$${\displaystyle \frac{V_{C_1}}{V_{in}}}={\displaystyle \frac{D}{\left(1-D\right)}}, {\displaystyle \frac{V_{C_1}}{V_{in}}}={\displaystyle \frac{D}{{\left(1-D\right)}^2}}, {\displaystyle \frac{V_{C_3}}{V_{in}}}={\displaystyle \frac{1}{{\left(1-D\right)}^2}}$$

(11)

The output voltage gain, expressed in terms of D, is

$${\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{\left(1+D\right)}{{\left(1-D\right)}^2}}$$

(12)

Assuming $I_{in}{V}_{in}=I_o{V}_o$, applying the current second balance condition on the capacitors results in

$$I_{L_1}={\displaystyle \frac{\left(1+D\right)}{\left(2-D\right){\left(1-D\right)}^2}}{I}_o, I_{L_2}={\displaystyle \frac{\left(1+D\right)}{\left(2-D\right)\left(1-D\right)}}{I}_o, I_{L_3}={\displaystyle \frac{1}{\left(2-D\right)}}{I}_o, I_{in}={\displaystyle \frac{\left(1+D\right)}{{\left(1-D\right)}^2}}{I}_o$$

(13)

3. Operation of the Proposed Converter in DCM

In the discontinuous conduction mode (DCM), the three inductor currents, $i_{L_1},i_{L_2}$, and $i_{L_3}$, are considered zero at a point, making them discontinuous in the switch-off period for a switching cycle. In this regard, there are seven possible discontinuous modes. However, the current drawn by $L_1$ is relatively high because of the inherent voltage-boosting process, making it less probable that $i_{L_1}$ will enter the discontinuous region. As a result, the three more likely discontinuous scenarios are shown in Figure 3. Figure 3b shows the scenario when only $i_{L_2}$ is discontinuous, while $i_{L_1}$and $i_{L_3}$ are continuous (${DCM}_a$). Figure 3c shows the operation of the converter when only $i_{L_3}$ assumes a zero value at some point, while $i_{L_1}$ and $i_{L_2}$ are continuous (${DCM}_b$). In ${DCM}_c$ (see Figure 3d), both $i_{L_2} and i_{L_3}$ are discontinuous and only $i_{L_1}$ is continuous. The three discontinuous scenarios (${DCM}_a$, ${DCM}_b$, and ${DCM}_c$) are analyzed below.

A.

Analysis of ${DCM}_a$

In the context of ${DCM}_a$, the converter operates in three distinct modes (see Figure 3b). Mode I occurs from ${0 \mathrm{t}\mathrm{o} t}_0$, when the switch is in the on state. This is like Mode 1 in CCM, as depicted in Figure 2a. The duty ratio for this period is $d$. Mode II occurs from ${t_0 \mathrm{t}\mathrm{o} t}_1$, when the switch is in the off state and $i_{L_2}$ is non-zero. The duty ratio for this interval is $d_1$. The operational circuit in Mode II is the same as Mode 2 in CCM, as shown in Figure 2c. Mode III spans from ${t_1 \mathrm{t}\mathrm{o} t}_2$, when $i_{L_2}$ is zero. Equations (13) and (14) detail the three inductors’ currents in ${DCM}_a$.

$$\begin{array}{c}{i}_{L_{1max}}={\displaystyle \frac{V_{in} }{L_1}}d{T}_s, i_{L_{2}max}={\displaystyle \frac{V_{in}+V_{C_1} }{L_2}}d{T}_s, i_{L_{3}max}={\displaystyle \frac{V_{C_3}-V_{C_2} }{L_3}}d{T}_s \end{array} \mathrm{Mode}\mathrm{I}$$

(14)

$$\begin{array}{c}{i}_{L_{1min}}={\displaystyle \frac{{-V}_{C_1} }{L_1}}(1-d{)T}_s, i_{L_{3}min}={\displaystyle \frac{V_{C_3}-V_o }{L_3}}(1-d{)T}_s, i_{L_{2}min}={\displaystyle \frac{V_{in}+V_{C_1}+V_{C_2}-V_o }{L_2}}{d}_1{T}_s\end{array} \mathrm{Mode}\mathrm{II}$$

(15)

Since the inductor current, $i_{L_{2}min}$, is zero at the end of Mode II, Mode III is exempted from the mathematical analysis. The application of the volt-second balance condition on the inductors leads to the following set of equations.

$${\displaystyle \frac{V_{C_1}}{V_{in}}}={\displaystyle \frac{d}{\left(1-d\right)}}, {\displaystyle \frac{V_{C_2}}{V_{in}}}={\displaystyle \frac{d\left(d+d_1\right)}{d_1\left(1-d\right)}}, {\displaystyle \frac{V_{C_3}}{V_{in}}}={\displaystyle \frac{(d+d_1)}{d_1\left(1-d\right)}}, {\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{(1+d)(d+d_1)}{d_1\left(1-d\right)}}$$

(16)

B.

Analysis of ${DCM}_b$

In${DCM}_b$, the three operational modes are as follows: Mode I, with duty ratio $d$, occurs from ${0 \mathrm{t}\mathrm{o} t}_0;$ Mode II occurs from ${t_0 \mathrm{t}\mathrm{o} t}_1$ m, with the duty ratio $d_2$; and Mode III occurs from ${t_1 \mathrm{t}\mathrm{o} t}_2$, as shown in Figure 3c. Circuit illustrations of Modes I and II are identical to Modes 1 and 2 in CCM (see Figure 2). Mode I in ${DCM}_b$ is the same for the other DCM analysis. Equation (14) depicts all inductor currents in this mode. In Mode II, (17) describes the inductor currents. $i_{L_3}$ is zero in Mode III, spanning from ${t_1 \mathrm{t}\mathrm{o} t}_2$.

$$\begin{array}{c}{i}_{L_{1min}}={\displaystyle \frac{{-V}_{C_1} }{L_1}}(1-d{)T}_s, i_{L_{3}min}={\displaystyle \frac{V_{C_3}-V_o }{L_3}}{d}_2{T}_s, i_{L_{2}min}={\displaystyle \frac{V_{in}+V_{C_1}+V_{C_2}-V_o }{L_2}}(1-d{)T}_s \mathrm{Mode}\mathrm{II}\end{array}$$

(17)

The application of the volt-second balance condition on the three inductors results in (18). $V_{C_1}$ remains the same as expressed in (16).

$$\begin{array}{c}{\displaystyle \frac{V_{C_2}}{V_{in}}}={\displaystyle \frac{d}{\left(d+d_2\right){\left(1-d\right)}^2}}, {\displaystyle \frac{V_{C_3}}{V_{in}}}={\displaystyle \frac{1}{{\left(1-d\right)}^2}}, {\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{\left(2d+d_2\right)}{\left(d+d_2\right){\left(1-d\right)}^2}}\end{array}$$

(18)

C.

Analysis of ${DCM}_c$

In ${DCM}_c$, the three operating modes are represented as follows: Mode I transpires from ${0 \mathrm{t}\mathrm{o} t}_0$, marked as $d$ (duty ratio) in Figure 3d. Subsequently, Mode II occurs from ${t_0 \mathrm{t}\mathrm{o} t}_1$, also denoted as $d_3$ in Figure 3d. Mode III ensues from ${t_1 \mathrm{t}\mathrm{o} t}_2$. The circuit configurations corresponding to Modes I and II remain consistent with Modes 1 and 2 observed in the context of CCM (see Figure 3). Equation (14) still depicts the inductors’ currents in Mode I. At the same time, Mode II is defined by (19). Notably, inductor currents $i_{L_2}$ and $i_{L_3}$ become zero in Mode III. The circuit layout for Mode III is represented in Figure 2d.

$$\begin{array}{c}{i}_{L_{1min}}={\displaystyle \frac{{-V}_{C_1} }{L_1}}(1-d{)T}_s, i_{L_{3}min}={\displaystyle \frac{V_{C_3}-V_o }{L_3}}{d}_3{T}_s , i_{L_{2}min}={\displaystyle \frac{V_{in}+V_{C_1}+V_{C_2}-V_o }{L_2}}{d_{3}T}_s \mathrm{Mode}\mathrm{II}\end{array}$$

(19)

Applying the volt-second balance condition on the three inductors results in (20). The voltage across $C_1$, denoted as $V_{C_1}$, remains unchanged and is expressed in (15). The other capacitors and the output voltages are expressed as

$$\begin{array}{c}{\displaystyle \frac{V_{C_2}}{V_{in}}}={\displaystyle \frac{d}{d_3\left(1-d\right)}}, {\displaystyle \frac{V_{C_3}}{V_{in}}}={\displaystyle \frac{\left(d+d_3\right)}{d_3\left(1-d\right)}}, {\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{\left(2d+d_3\right)}{d_3\left(1-d\right)}}\end{array}$$

(20)

A comparison of the voltage gain in CCM and the three DCMs is illustrated in Figure 4. ${DCM}_c$ provides the highest voltage gain; however, high current flows through the inductors in DCM.

4. Design Specifications of the Proposed Converter

A.

Inductor Design

The proposed quadratic topology has three inductors, $L_1$, $L_2$, and $L_3.$ Equation (1) represents the current ripple of $L_1$ for ${DT}_s.$ Therefore, the maximum value of the ripple current occurs when $D=1.$ $L_1$ can be determined from (1) as

$$L_1\ge {\displaystyle \frac{{V_{in}}^{2}D }{x\%f_s{P}_o}}$$

(21)

where $P_o$ is the output power, $f_s$ is the switching frequency, and $x\%$ represents the percentage factor of the ripple with respect to the load current and ranges from 10% to 20%.

From (2) and (11), the ripple current recorded through $L_2$ is

$${∆I}_{L_2}={\displaystyle \frac{ V_{in} }{L_2(1-D)}}{DT}_s$$

(22)

$L_2$ experiences maximum ripple as D→1.

Computation for the inductor size for $L_2$ follows the equation

$$L_2\ge {\displaystyle \frac{{V_{in}}^{2}D }{x\%f_s{P}_o(1-D)}}$$

(23)

The ripple current through $L_3$, according to (3) and (11), is

$${∆I}_{L_3}={\displaystyle \frac{V_{in} }{L_3\left(1-D\right)}}{DT}_s$$

(24)

Maximum ripple is experienced by $L_3$ as D approaches 1. The equation below serves as the basis for computing the required value of the inductor.

$$L_3\ge {\displaystyle \frac{{V_{in}}^{2}D }{x\%f_s{P}_o(1-D)}}$$

(25)

B.

Capacitor Design and Selection

The capacitors ensure the stable operation of the converter by managing voltage ripple and accommodating the required current levels. Their design involves careful consideration of parameters such as the switching frequency, input voltage, duty cycle, and the maximum allowable voltage ripple. The capacitors can be designed by considering their maximum current values and the acceptable voltage ripple. The parameter, ${∆V}_C$, represents the maximum allowable voltage ripple for each capacitor, usually between 1 and 10%. The voltage rating of the selected capacitors must exceed the peak voltage levels in the circuit to ensure reliability and safety. Capacitors with low ESR are preferred to minimize power loss and heat generation.

From (5) and (11), $C_1-C_3$ are designed with the expressions beneath.

$$\begin{array}{c}{C}_1={\displaystyle \frac{I_{L_2}D}{f_s{∆V}_{C_1} }}={\displaystyle \frac{I_{L_2}\left(1-D\right)}{y\%f_s{V}_{in} }}, C_2={\displaystyle \frac{I_{L_3}D}{f_s {∆V}_{C_2}}}={\displaystyle \frac{I_{L_3}{\left(1-D\right)}^2}{y\%f_s{V}_{in} }}, C_3={\displaystyle \frac{I_{L_3}D}{f_s {∆V}_{C_2}}}={\displaystyle \frac{I_{L_3}D{\left(1-D\right)}^2}{y\%f_s{V}_{in} }}\end{array}$$

(26)

C.

Semiconductor selection

The voltage, $V_{DS}$, is seen across the terminals of the switch in Mode 2 (see Figure 2c). Applying KVL results in

$$V_{DS}= {\displaystyle \frac{V_o}{(1+D)}}$$

(27)

From Figure 2b, the current passing through $S_1$ is the sum of all inductor currents, as expressed in (4).

The current and voltage stress analysis of $D_1-D_3$ is as follows:

In Figure 2b, $D_1$ is off. $V_{D_1}$ represents the voltage across the diode terminals. Thus, from (2) and (11)

$$V_{D_1}={\displaystyle \frac{\left(1-D\right)}{\left(1+D\right)}} V_o$$

(28)

In Mode 2, $D_1$ experiences the flow of current, $i_{L_1}$. From Figure 2c,

$$i_{D_1}=i_{L_1}$$

(29)

From Figure 2c, $D_2$ is reverse-biased and $V_{D_2}$ is the voltage developed across it. Accordingly, a deduction can be drawn from (7) and (11) as

$$V_{D_2}={\displaystyle \frac{D}{\left(1+D\right)}}{V}_o$$

(30)

In Mode 1 (see Figure 2b), $D_2$ is in the forward mode. The diode current, $i_{D_2}$, is expressed as

$$i_{D_2}=i_{L_1}$$

(31)

Similarly, $D_3$ is reverse-biased in Mode 1, as displayed in Figure 2b. The reverse blocking voltage,$V_{D_2}$, and the output diode, $D_O$, voltage stress is computed in Mode 1 as

$$V_{D_3}=V_{D_o}={\displaystyle \frac{V_o}{\left(1+D\right)}}$$

(32)

5. Proposed Converter with Magnetic Coupling

To achieve a higher voltage boost and operate the converter with a lower switching duty cycle, a trans-inverse coupled inductor is employed, as can be seen in Figure 5a. The key waveforms for CCM operation are displayed in Figure 6a. The operating modes and analysis are provided below.

A. 

Operating modes

The proposed converter with a coupled inductor operates through three distinctive modes: Mode A involves switch activation; in Mode B, the switch is turned off; and in Mode C, both the switch and the output diode are deactivated.

Mode A: The circuit operation involves four closed loops with different components when $S_1$ is active for a fraction, D, of the switching period, $T_s$. Only diode $D_2$ is forward-biased, while $D_1$, $D_3$, and $D_o$ are reverse-biased. Loop 1 consists of $V_{in}$, $L_1$, $D_2$, and $S_1.$ The input voltage, $V_{in}$, charges $L_1$, causing the flow of $i_{L_1}$ through $L_1$. Loop 2 consists of $V_{in}$, $C_1$, $L_2$, and $S_1.$ The combination of $V_{in}$ and $C_1$ charges $L_2$. This induces $i_{L_2}$ in this loop. Loop 3 involves $C_2$, $C_3$, $L_3$, and $S_1.$ $L_3$, the coupled inductor with windings $N_1$ and $N_2(\mathrm{w}\mathrm{i}\mathrm{t}\mathrm{h} \mathrm{N}={\displaystyle \frac{N_2}{N_1}})$ is charged by $C_2$ and $C_3$. Loop 4 consists of $C_o$ and $R_L$. In this mode, the currents flowing through $L_1$, $L_2$, and $L_m$, all of which increase. Refer to Figure 5b for the circuit configuration.

Equation (33) represents the voltages and currents through the inductors in this mode.

$$\left.\begin{array}{c}{V}_{L_1}=V_{in}\\ V_{L_2}=V_{in}+V_{C_1}\\ V_{L_m}={\displaystyle \frac{V_{C_3}-V_{C_2} }{N-1}}\end{array}\right| \left.\begin{array}{c}{di}_{L_1}={\displaystyle \frac{V_{in} }{L_1}}dt \\ {di}_{L_2}={\displaystyle \frac{V_{in}+V_{C_1} }{L_2}}dt\end{array}\right|$$

(33)

Mode B: $S_1$ is deactivated, causing $D_1$, $D_3$, and $D_o$ to conduct while $D_2$ is off. This results in the formation of four distinct closed loops. Loop 1 involves $L_1$, $D_{1 }$, and $C_1.$ $L_1$ discharges its stored energy into $C_1$ via $D_1$. Loop 2 consists of $V_{in}$, $C_1$, $C_2$, $D_o, L_2$, and$C_o$. The input voltage and $L_2$ provide the energy to the capacitors in this loop. Loop 3 consists of $C_2$, $D_3$, and $N_1.$ $C_2$ is charged by the energy discharged by $N_1$. Figure 5c shows the circuit.

$$\left.\begin{array}{c}{V}_{L_1}={-V}_{C_1}\\ V_{L_2}=V_{in}+V_{C_1}+V_{C_2}-V_o \\ V_{L_m}={\displaystyle \frac{V_{C_3}-V_o }{N-1}}\end{array}\right| \left.\begin{array}{c}{dI}_{L_1}={\displaystyle \frac{{-V}_{C_1} }{L_1}}dt \\ {dI}_{L_2}={\displaystyle \frac{V_{in}+V_{C_1}+V_{C_2}-V_o }{L_2}}dt \end{array}\right|$$

(34)

Mode C: While $S_1$ is inactive, the leakage inductance of the coupled inductor causes $D_o$ to activate before the end of the switching period. During steady-state analysis, an ideal behavior of the coupled inductor is assumed, yet the influence of its leakage inductance is evident. This effect causes $D_o$ to deactivate before the switching period ends, even when the power switch is inactive. This state, displayed in Figure 5d, underscores the need for careful design of the coupled inductor, prioritizing high magnetizing inductance and minimal leakage inductance to mitigate this issue effectively. The voltage stresses on the capacitors are calculated as

$$\begin{array}{c}{\displaystyle \frac{V_{C_1}}{V_{in}}}={\displaystyle \frac{D}{\left(1-D\right)}}, {\displaystyle \frac{V_{C_2}}{V_{in}}}={\displaystyle \frac{ND}{{(N-1)\left(1-D\right)}^2}}, {\displaystyle \frac{V_{C_3}}{V_{in}}}={\displaystyle \frac{N-1+D}{{(N-1)\left(1-D\right)}^2}} \end{array}$$

(35)

The output voltage gain expressed in terms of the duty ratio is

$${\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{N-1+ND}{{(N-1)\left(1-D\right)}^2}}$$

(36)

Figure 6b illustrates the voltage gain of the proposed magnetic coupling converter versus the transformer turns ratio and duty cycle. It can be observed that the voltage boost capability of the proposed converter with coupled inductors is increased by lowering the transformer turns ratio.

B. 

Built-in regenerative snubber circuit

In practice, the presence of leakage inductance can cause significant voltage spikes on the power switch due to resonance with the switch’s parasitic capacitance. These spikes can occur when the converter transitions from Mode A to Mode B when the switch is turned off. In the proposed converter, this issue is mitigated through a design that eliminates the need for an additional lossy snubber circuit. In Mode A, capacitor C₃ charges the coupled transformer. When the power switch turns off, Mode B starts, and the transformer is clamped to the output capacitor, releasing the stored energy from the coupled inductors and their leakage inductances to Co. In this mode, diodes D₃ and Do are activated, clamping the switch voltage to the difference between the output voltage and the capacitor voltage, V_C2. This configuration, depicted in Figure 7, shows that the built-in regenerative snubber circuit is created using capacitors C₂ and C_O, and the diode, D_O, safely redirects the leakage energy to the power capacitors, which allows the output capacitor to absorb the energy from the leakage inductances, effectively recycling it and preventing voltage spikes on the power switch, enhancing the overall efficiency and reliability of the converter. Additionally, the presence of the DC current blocking capacitor C₃ in series with winding N₂ prevents DC current saturation of the core.

6. Power Loss Analysis

For power dissipation in the proposed converter, the conduction losses of the parasitic components and the switching losses of the MOSFET are the major contributors. The parasitic components, $r_{DS}$, $r_{D_n}$, $V_{F_n}$, $r_{L_n}$, and $r_{c_n}$, are the switch on-state resistance, the diode’s forward resistance, the diode threshold voltage, the inductor’s ESR, and the capacitor’s ESR, respectively.

Using (4) and (13), the conduction loss of $S_1$ ($P_{{con}_{s1}}$) can be expressed in the form

$$P_{{con}_{s1}}={I_{{S1}_{rms}}}^2.r_{DS}$$

(37)

The primary source of switching losses during transitions is the capacitive turn-on loss, which arises from the discharge of the junction capacitor, $C_{oss}$, of the MOSFET. This loss is dependent on the switched voltage and the switching frequency. Typically, the capacitive turn-on energy dissipation, $E_{oss}$, can be found in the device datasheet. Therefore, the switching loss for the MOSFET can be expressed as

$$P_{{sw}_1}=f_s.E_{oss}.V_{DS}=f_s.E_{oss}.{\displaystyle \frac{V_o}{\left(1+D\right)}}$$

(38)

where $I_{{S1}_{rms}}$ is the switch rms current and $f_s$ is the switching frequency.

The conduction loss of the diodes ${(P}_{{con}_{Dn}})$ is due to $r_{D_n}$ and $V_{F_n}$. The estimated conduction loss is

$$P_{{con}_{Dn}}=I_{{Dn}_{avg}}{.V}_{F_n}+{I_{{Dn}_{rms}}}^2.r_{D_n}$$

(39)

The conduction losses of the inductors are estimated as

$$P_{{con}_{Ln}}={I_{{Ln}_{rms}}}^2.r_{L_n}$$

(40)

The conduction losses of the capacitors take the form

$$P_{{con}_{Cn}}={I_{{Cn}_{rms}}}^2.r_{L_n}$$

(41)

The inductors also experience core losses in their operation. The core loss of an inductor is calculated as

$$P_{fe\left(Ln\right)}=lm . Ac .Kfe . {B_{max}}^{\beta }$$

(42)

where $lm$, $Ac$, $Kfe$, $B_{max}$, and $\beta$ represent the magnetic path length, the core’s cross-sectional area, the core loss coefficient, the maximum flux density, and the core loss exponent, respectively.

7. Comparative Analysis

The proposed quadratic boost converter was compared with other similar topologies. The analysis in terms of voltage gain, switch and diode voltage stresses, and number of elements (switches, diodes, inductors, and capacitors) is summarized in

Table 1. Comparison of basic features of DC-DC converters.

Description	QBC	[2]	[3]	[4]	[5]	[35]	[37]	[38]	Proposed
G	${\displaystyle \frac{1}{{(1-D)}^2}}$	${\displaystyle \frac{1+2D}{\left(1-D\right)}}$	${\displaystyle \frac{4}{(1-D)}}$	${\displaystyle \frac{4}{(1-D)}}$	${\displaystyle \frac{2D}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{3D}{\left(1-D\right)}}$	${\displaystyle \frac{D^2}{{(1-D)}^2}}$	${\displaystyle \frac{(1+2D-D^2)}{{(1-D)}^2}}$	${\displaystyle \frac{(1+D)}{{(1-D)}^2}}$
$V_S$	$V_o$	${\displaystyle \frac{V_o}{(1+2D)}}$	${\displaystyle \frac{V_o}{2}}$	${\displaystyle \frac{V_o}{4}}$	${\displaystyle \frac{V_o\left(1-D\right)}{2D}}$	${\displaystyle \frac{V_o}{3D}}$	${\displaystyle \frac{V_o}{D^2}}$	${\displaystyle \frac{V_o}{(1+2D-D^2)}}$	${\displaystyle \frac{V_o}{(1+D)}}$
$V_{Do}$	$V_o$	${\displaystyle \frac{V_o}{(1+2D)}}$	${\displaystyle \frac{V_o}{2}}$	${\displaystyle \frac{V_o}{2}}$	${\displaystyle \frac{V_o}{2D}}$	${\displaystyle \frac{V_o}{3D}}$	${\displaystyle \frac{V_o}{D}}$	${\displaystyle \frac{V_o}{(1+2D-D^2)}}$	${\displaystyle \frac{V_o}{(1+D)}}$
NS	1	1	2	2	3	1	1	1	1
ND	3	3	4	5	4	3	5	5	4
NL	2	3	2	2	3	4	3	4	3
NC	2	5	4	5	4	6	3	6	4
NTotal	8	12	12	14	14	14	12	16	12

G: voltage gain, V_S: maximum voltage stress on the power switch, V_DO: maximum voltage stress on the output diode, N_S: number of switches, N_D: number of diodes, N_L: number of inductors, N_C: number of capacitors, N_Total: total number of components.

. From Table 1, it can be observed that the proposed converter has a comparable number of circuit elements. Figure 8a gives a graphical analysis of the voltage gain versus duty ratio of the proposed converter, the conventional quadratic boost converter (QBC), and other topologies. It can be observed that for $D>0.6$, the proposed topology provides the highest voltage gain. Furthermore, Figure 8b provides a comparison of the relationship of the normalized voltage stress on the power switches against their respective voltage gains for various topologies. In comparison to these topologies, the voltage stress on the power switch employed in the proposed converter is minimal. Similarly, the normalized voltage stress of the output diode of the proposed converter compared to that of the other stated topologies is displayed in Figure 8c. Here, again, the normalized voltage stress of the proposed converter is reasonably low. High-voltage gain DC-DC converters sometimes have high voltage stresses on capacitors. Figure 8d provides a comparison of the input capacitor voltage stress for the proposed converter and the previously mentioned topologies. The proposed converter shows the least voltage stress across the input capacitor. Thus, the proposed converter is a good candidate for applications requiring higher voltage gain and low stress on components.

The proposed magnetic coupling quadratic converter was compared with its counterparts. For a fair comparison, we considered the same turns number for all topologies (50:40). As can be seen in Figure 9a, the proposed magnetic coupling converter provides a higher voltage gain than its counterparts for $D>0.36$. Figure 9a,b illustrate that the proposed converter provides the lowest voltage stress on both the power switch and the output diode compared to similar quadratic magnetic coupling topologies. This reduction in voltage stress can result in significant cost savings by allowing the use of less expensive components and decreasing maintenance needs, while also enhancing overall efficiency. Finally,

Table 2. Comparison of magnetic coupling in quadratic converters.

Description	[9]	[18]	[19]	[22]	[23]	Proposed
NS	2	1	2	1	1	1
ND	4	5	6	6	6	4
NL + NCL	1+1	2+1	1+1	2+1	1+1	2+1
NC	4	3	6	4	5	4
NTotal	12	12	16	14	14	12
G	${\displaystyle \frac{1+D+2(\frac{1-D}{N})}{{(1-D)}^2}}$	${\displaystyle \frac{1+\frac{D}{N}}{{(1-D)}^2}}$	${\displaystyle \frac{1+\frac{2}{N}}{{(1-D)}^2}}$	${\displaystyle \frac{1+\frac{D}{N}}{{(1-D)}^2}}$	${\displaystyle \frac{(\frac{3D+2}{N})+(2-D)}{2{(1-D)}^2}}$	${\displaystyle \frac{N-1+ND}{{(N-1)\left(1-D\right)}^2}}$
$V_S$	${\displaystyle \frac{\left(1+D\right)V_o}{1+D+2(\frac{1-D}{N})}}$	${\displaystyle \frac{V_o}{1+\frac{D}{N}}}$	${\displaystyle \frac{V_o}{1+\frac{2}{N}}}$	${\displaystyle \frac{V_o}{1+\frac{D}{N}}}$	${\displaystyle \frac{(2+D(\frac{1}{N}-1))V_o}{(\frac{3D+2}{N})+(2-D)}}$	${\displaystyle \frac{N(N+2)V_o}{N-1+ND}}$
$V_{Do}$	${\displaystyle \frac{(1+\frac{2-D}{N})V_o}{{(1-D)}^2}}$	${\displaystyle \frac{(1+D(\frac{1}{N}-1))V_o}{1+(\frac{D}{N})D}}$	${\displaystyle \frac{(\frac{V_o}{N})}{1+\frac{2}{N}}}$	${\displaystyle \frac{(2+D(\frac{1}{N}-1))V_o}{1+(\frac{1}{N})D}}$	${\displaystyle \frac{(\frac{{2V}_o}{N})}{(\frac{3D+2}{N})+(2-D)}}$	${\displaystyle \frac{N(N+2)}{N-1+ND}}$

presents a brief comparison between the proposed converters and selected magnetic coupling quadratic converters.

8. Experimental Results

To assess the performance and functionality of the proposed converter, a hardware prototype with a power rating of 260 W was developed and tested. The electrical specifications of the components utilized in the prototype can be found in

Table 3. Components’ electrical specifications.

Components	Values
Input voltage ($V_{in}$)	24 V
Rated output voltage ($V_o$)	400 V
Rated output power ($P_o$)	260 W
MOSFET ($S_1$)	NTHL065N65S3HF
Switching frequency	50 kHz
Diodes ($D_1-D_4$)	BYC30JT-600PSQ
Controller	TMS320F28335
Inductors ($L_1-L_3$)	0.176 mH
Capacitors ($C_1-C_3$)	100 $\mathsf{\mu }\mathrm{F}$
Output Capacitor ($C_o$)	100 $\mathsf{\mu }\mathrm{F}$

. A voltage PI controller was used to analyze the closed-loop operation of the proposed converter, as depicted in Figure 10. The loop regulates the output voltage with the PI controller implemented using a digital signal processor (DSP). The outcomes of the experiments are depicted in Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18. Figure 11, Figure 12, Figure 13, Figure 14, Figure 15 and Figure 16 show the results for the proposed converter without the coupled inductor, and Figure 17 and Figure 18 show the results obtained with the coupled inductor. In Figure 11, the input and output voltages, switch drain-source voltage ($V_{DS}$), and current ($i_S$) for a resistive load of $625 \mathsf{\Omega }$ at a switching frequency of 50 kHz and a duty ratio of 0.7 are shown. The output voltage is 400 V, with an input of 24 V. The results demonstrated that the drain-source voltage of the switch did not exhibit notable voltage stress or spikes. Figure 12 shows the voltage and current waveforms of $L_1$ and $L_2$. The inductor currents show fewer ripples and are continuous. Figure 13 illustrates the capacitor voltages and the output diode voltage stress. The input capacitor has a stress of less than 50 V, while the output diode stress is lower than the output voltage. With an increase in the input voltage from 24 V to 30 V, Figure 14a shows the closed-loop response of the converter. The duty ratio is quickly adjusted to maintain a constant output voltage of 400 V for a step input voltage change. Furthermore, Figure 14b displays the response of the converter when there is a step change in load from $625 \mathsf{\Omega }$ to $1250 \mathsf{\Omega }$. Results for other loads tested with the proposed converter are illustrated in Figure 15. Figure 15a,b show results for an RL load ($R=250 \mathsf{\Omega }$, L=50 mH) and an RC load ($R=250 \mathsf{\Omega }$, C = 10 mF), respectively. DCM experimental results for the proposed converter are shown in Figure 16. Figure 16a,b highlight the results for ${DCM}_b$ and ${DCM}_c$. The results confirm the theoretical findings in Figure 5. To evaluate leakage current, a 1 nF capacitor was placed between the positive terminal of the input DC voltage source and the negative terminal of the output. The measurement results, presented in Figure 16c, demonstrate an insignificant leakage current, validating that the proposed inverter effectively mitigates any leakage current concerns.

With a load of $625 \mathsf{\Omega }$, the results for the input and output voltages, as well as the drain-source voltage ($V_{DS}$) and current ($i_S$) through the switch of the converter with the coupled inductor at a switching frequency of 50 kHz and a duty ratio of 0.54, are displayed in Figure 17. As shown, the proposed converter with the coupled inductor achieved the required output voltage at a lower duty ratio. Notably, the output voltage was maintained at 400 V, while the input voltage was set at 24 V. Figure 18 shows the voltage and current waveforms of inductors $L_1$ and $L_2$ of the coupled inductor-based converter. The prototype of the hardware and the experimental setup are displayed in Figure 19.

The experimental results not only validate the theoretical analysis but also demonstrate close alignment with the simulation findings in terms of output voltage regulation in Figure 4, switch voltage stress, inductor current behavior, and overall system response. The experimentally observed low ripple in inductor currents and minimal voltage stress on the switch corroborate the simulation, thereby confirming the accuracy of the simulated waveforms and theoretical predictions. Furthermore, the closed-loop performance shown in Figure 14a,b is consistent with simulation responses, indicating reliable controller implementation and robust converter behavior.

At 260 W output power, the power loss of individual components of the proposed converter carried out in PSIM is illustrated in Figure 20a. Figure 20b further provides a percentage loss distribution of the various components of the proposed converter. With a constant output power of 200 W, Figure 21a provides a relationship between voltage gain and measured efficiency. With lower gain, higher efficiency is experienced. The relationship between output power and measured efficiency is illustrated in Figure 21b. A maximum efficiency of 91.43% can be noticed at 260 W output power. Also, a comparison between the simulated and experimental efficiency of the proposed converter is illustrated in Figure 21c. While the two curves look similar, the simulated efficiency is slightly higher than the measured efficiencies. Finally, Figure 22 shows that the proposed converter has a higher efficiency compared with similar high-voltage gain converters.

9. Conclusions

This paper presents two innovative DC-DC quadratic semi-SEPIC boost converters with high voltage gain. These converters are adept at generating a high output voltage from a low-DC source. What truly distinguishes these converters is their unique capability to establish low voltage stress on the input capacitor and the semi-conductor elements while providing a shared ground between the source and the load. This proves highly advantageous in eradicating common-mode leakage. Furthermore, the design of this converter boasts simple control circuitry. A magnetic coupling is applied to the proposed converter to obtain the same output voltage with a lower duty ratio and low stresses on devices. These improvements collectively result in heightened overall performance. To substantiate the practicality of this proposed converter, its operational effectiveness was validated through experimental testing.