# Practical Implementation of the Indirect Control to the Direct 3 × 5 Matrix Converter Using DSP and Low-Cost FPGA

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Construction of the 3 × 5 Matrix Converter

## 3. Theory of Indirect Control for the Direct Matrix Converter

_{in}, applies:

_{ϒ}, d

_{δ}, and d

_{0}represent the duty cycles of the active and zero vectors, and I

_{ϒ}, I

_{δ}, and I

_{0}represent adjacent vectors in the sector, where the output vector, I

_{in}, lies. The duty cycles are calculated according to the following equations [31]:

_{r}represents the modulation index of the virtual rectifier, which can be in the range of 0–1. Similarly, for the output voltage inverter, the decagon was constructed. Since the output was five-phase output, the usable vectors were divided into large, medium, and small, according to Figure 3.

_{α}, d

_{β}, and d

_{Z}are duty cycles of the active and zero vectors. The duty cycles can be calculated by adjusting from three-phase to five-phase [31]:

_{i}represents the modulation index of the virtual inverter. Since only medium and large vectors were used due to the simplification of the FPGA control algorithm, the duty cycles of these vectors must be calculated relative to each other, as follows:

_{DC}is calculated from the peak input voltage, V

_{in}, the rectifier modulation index, m

_{r}, and the input displacement angle, φ

_{in}, as follows:

## 4. Practical Implementation of the Indirect Control

## 5. Practical Verification of the Indirect Control

_{R}, was set to 1, and the value of the inverter modulation index, m

_{I}, changed in range from 0.1 to 1.6. Inverter modulation index 1,6 is the maximum value, because higher values overmodulate the inverter part of the MxC. The measured results can be seen in Figure 12, Figure 13, Figure 14 and Figure 15.

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 12.**Measured results at f

_{IN}= 50 Hz and f

_{OUT}= 50 Hz. CH1—output current, CH2—output load voltage, CH3—output phase to phase voltage.

**Figure 13.**Measured results at f

_{IN}= 50 Hz and f

_{OUT}= 25 Hz. CH1—output current, CH2—output load voltage, CH3—output phase to phase voltage, CH4—output phase to input neutral voltage.

**Figure 14.**Measured results at f

_{IN}= 50 Hz and f

_{OUT}= 100 Hz. CH1—output current, CH2—output load voltage, CH3—output phase to phase voltage, CH4—output phase to input neutral voltage.

**Figure 15.**Measured results at f

_{IN}= 50 Hz and f

_{OUT}= 200 Hz. CH1—output current, CH2—output load voltage, CH3—output phase to phase voltage, CH4—output phase to input neutral voltage.

**Figure 16.**Measured results from the YOKOGAWA analyzer: top waveform—output phase current, bottom waveform—output phase voltages.

Rectifier Sector | I_{δ} | I_{ϒ} | I_{0} |
---|---|---|---|

1 | I_{1} | I_{2} | I_{7} |

2 | I_{2} | I_{3} | I_{9} |

3 | I_{3} | I_{4} | I_{8} |

4 | I_{4} | I_{5} | I_{7} |

5 | I_{5} | I_{6} | I_{9} |

6 | I_{6} | I_{1} | I_{8} |

Vector/Switch | S_{1} | S_{3} | S_{5} | S_{2} | S_{4} | S_{6} |
---|---|---|---|---|---|---|

1 | 1 | 0 | 0 | 0 | 1 | 0 |

2 | 1 | 0 | 0 | 0 | 0 | 1 |

3 | 0 | 1 | 0 | 0 | 0 | 1 |

4 | 0 | 1 | 0 | 1 | 0 | 0 |

5 | 0 | 0 | 1 | 1 | 0 | 0 |

6 | 0 | 1 | 1 | 0 | 0 | 0 |

7 | 1 | 0 | 0 | 1 | 0 | 0 |

8 | 0 | 1 | 0 | 0 | 1 | 0 |

9 | 0 | 0 | 1 | 0 | 0 | 1 |

Sector | V_{α m} | V_{α l} | V_{β m} | V_{β l} | V_{z1} | V_{z2} |
---|---|---|---|---|---|---|

1 | V_{11} | V_{1} | V_{12} | V_{2} | V_{31} | V_{32} |

2 | V_{13} | V_{3} | V_{12} | V_{2} | ||

3 | V_{13} | V_{3} | V_{14} | V_{4} | ||

4 | V_{15} | V_{5} | V_{14} | V_{4} | ||

5 | V_{15} | V_{5} | V_{16} | V_{6} | ||

6 | V_{17} | V_{7} | V_{16} | V_{6} | ||

7 | V_{17} | V_{7} | V_{18} | V_{8} | ||

8 | V_{19} | V_{9} | V_{18} | V_{8} | ||

9 | V_{19} | V_{9} | V_{20} | V_{10} | ||

10 | V_{11} | V_{1} | V_{20} | V_{10} |

Vector/Switch | S_{7} | S_{9} | S_{11} | S_{13} | S_{15} |
---|---|---|---|---|---|

1 | 1 | 1 | 0 | 0 | 1 |

2 | 1 | 1 | 0 | 0 | 0 |

3 | 1 | 1 | 1 | 0 | 0 |

4 | 0 | 1 | 1 | 0 | 0 |

5 | 0 | 1 | 1 | 1 | 0 |

6 | 0 | 0 | 1 | 1 | 0 |

7 | 0 | 0 | 1 | 1 | 1 |

8 | 0 | 0 | 0 | 1 | 1 |

9 | 1 | 0 | 0 | 1 | 1 |

10 | 1 | 0 | 0 | 0 | 1 |

11 | 1 | 0 | 0 | 0 | 0 |

12 | 1 | 1 | 1 | 0 | 1 |

13 | 0 | 1 | 0 | 0 | 0 |

14 | 1 | 1 | 1 | 1 | 0 |

15 | 0 | 0 | 1 | 0 | 0 |

16 | 0 | 1 | 1 | 1 | 1 |

17 | 0 | 0 | 0 | 1 | 0 |

18 | 1 | 0 | 1 | 1 | 1 |

19 | 0 | 0 | 0 | 0 | 1 |

20 | 1 | 1 | 0 | 1 | 1 |

31 | 0 | 0 | 0 | 0 | 0 |

32 | 1 | 1 | 1 | 1 | 1 |

Category | Available on FPGA | Used by the Algorithm |
---|---|---|

Logic Cells | 1280 | 325 |

PLBs | 160 | 81 |

I/Os | 72 | 55 |

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**MDPI and ACS Style**

Praženica, M.; Resutík, P.; Kaščák, S.
Practical Implementation of the Indirect Control to the Direct 3 × 5 Matrix Converter Using DSP and Low-Cost FPGA. *Sensors* **2023**, *23*, 3581.
https://doi.org/10.3390/s23073581

**AMA Style**

Praženica M, Resutík P, Kaščák S.
Practical Implementation of the Indirect Control to the Direct 3 × 5 Matrix Converter Using DSP and Low-Cost FPGA. *Sensors*. 2023; 23(7):3581.
https://doi.org/10.3390/s23073581

**Chicago/Turabian Style**

Praženica, Michal, Patrik Resutík, and Slavomír Kaščák.
2023. "Practical Implementation of the Indirect Control to the Direct 3 × 5 Matrix Converter Using DSP and Low-Cost FPGA" *Sensors* 23, no. 7: 3581.
https://doi.org/10.3390/s23073581