A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM
Abstract
:1. Introduction
2. Architecture of Proposed SSPLL
2.1. Conceptual Block Diagram
2.2. Loop Analysis
3. Circuit Implementation
3.1. Class-C VCO with Start-Up Circuit
3.2. Voltage-Controlled Buffer
3.3. Rail-to-Rail Sub-Sampling Charge Pump
4. Phase Noise Analysis
5. Measurement Results
6. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Tech. (nm) | Supply (V) | Out Freq. (GHz) | Ref. Freq. (MHz) | Ref. Spur (dBc) | RMS Jitter (fs) | Power (mW) | FoM (dB) | |
---|---|---|---|---|---|---|---|---|
This work | 40 | 0.8 | 5.6 | 112 | −51.8 | 196.5 (10 k–100 M) | 1.8 | −251.6 |
[6] | 65 | 0.9 | 6.8 | 106.25 | −40 | 190 (10 k–100 M) | 2.25 | −251 |
[8] | 65 | 0.45 | 2.4 | 10 | −50.1 | 2800 (1 k–100 M) | 0.265 | −236.8 |
[15] | 28 | - | 7.77 | 80 | −66.4 | 82 (10 k–10 M) | 14.7 | −250 |
[23] | 16 | 0.9/1.8 | 18 | 450 | - | 164 (1 k–10 M) | 29.2 | −241 |
[24] | 65 | 1.2 | 5 | 50 | −77 | 357 (10 k–10 M) | 3.9 | −243 |
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Zuo, S.; Zhao, J.; Zhou, Y. A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM. Sensors 2021, 21, 7648. https://doi.org/10.3390/s21227648
Zuo S, Zhao J, Zhou Y. A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM. Sensors. 2021; 21(22):7648. https://doi.org/10.3390/s21227648
Chicago/Turabian StyleZuo, Shi, Jianzhong Zhao, and Yumei Zhou. 2021. "A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM" Sensors 21, no. 22: 7648. https://doi.org/10.3390/s21227648
APA StyleZuo, S., Zhao, J., & Zhou, Y. (2021). A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM. Sensors, 21(22), 7648. https://doi.org/10.3390/s21227648