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Open AccessArticle

Harmonic Distortion Optimization for Sigma-Delta Modulators Interface Circuit of TMR Sensors

Faculty of Information Science and Engineering, Ningbo University, Ningbo 315211, China
MEMS Center, Harbin Institute of Technology, Harbin 150001, China
Author to whom correspondence should be addressed.
Sensors 2020, 20(4), 1041; (registering DOI)
Received: 22 December 2019 / Revised: 4 February 2020 / Accepted: 12 February 2020 / Published: 14 February 2020
(This article belongs to the Special Issue Magnetic Sensing System)
The tunneling magnetoresistance micro-sensors (TMR) developed by magnetic multilayer material has many advantages, such as high sensitivity, high frequency response, and good reliability. It is widely used in military and civil fields. This work presents a high-performance interface circuit for TMR sensors. Because of the nonlinearity of signal conversion between sensitive structure and interface circuit in feedback loop and forward path, large harmonic distortion occurs in output signal spectrum, which greatly leads to the reduction of SNDR (signal noise distortion rate). In this paper, we analyzed the main source of harmonic distortion in closed-loop detection circuit and establish an accurate harmonic distortion model in TMR micro-sensors system. Some factors are considered, including non-linear gain of operational amplifier unit, effective gain bandwidth, conversion speed, nonlinearity of analog transmission gate, and nonlinearity of polycrystalline capacitance in high-order sigma-delta system. We optimized the CMOS switch and first-stage integrator in the switched-capacitor circuit. The harmonic distortion parameter is optimally designed in the TMR sensors system, aiming at the mismatch of misalignment of front-end system, non-linearity of quantizer, non-linearity of capacitor, and non-linearity of analog switch. The digital output is attained by the interface circuit based on a low-noise front-end interface circuit and a third-order sigma-delta modulator. The digital interface circuit is implemented by 0.35μm CMOS (complementary metal oxide semiconductor) technology. The high-performance digital TMR sensors system is implemented by double chip integration and the active interface circuit area is about 3.2 × 2 mm. The TMR sensors system consumes 20 mW at a single 5 V supply voltage. The TMR sensors system can achieve a linearity of 0.3% at full scale range (±105 nT) and a resolution of 0.25 nT/Hz1/2(@1Hz).
Keywords: harmonic distortion; interface circuit; tunneling magneto-resistance sensors harmonic distortion; interface circuit; tunneling magneto-resistance sensors
MDPI and ACS Style

Li, X.; Hu, J.; Liu, X. Harmonic Distortion Optimization for Sigma-Delta Modulators Interface Circuit of TMR Sensors. Sensors 2020, 20, 1041.

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