Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Rashid, Muhammad; Baloch, Naveed Khan; Shafique, Muhammad Akmal; Hussain, Fawad; Saleem, Shahroon; Zikria, Yousaf Bin; Yu, Heejung

doi:10.3390/s20185355

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Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Muhammad Rashid

^1,†,

Naveed Khan Baloch

^1,†,

Muhammad Akmal Shafique

Fawad Hussain

Shahroon Saleem

¹,

Yousaf Bin Zikria

^3,*

and

Heejung Yu

^4,*

Department of Computer Engineering, University of Engineering & Technology, Taxila 47050, Pakistan

Department of Electrical Engineering, University of Engineering & Technology, Taxila 47050, Pakistan

Department of Information and Communication Engineering, Yeungnam University, Gyeongsan-si 38541, Korea

⁴

Department of Electronics and Information Engineering, Korea University, Sejong 30019, Korea

Authors to whom correspondence should be addressed.

^†

These authors contributed equally to this work and are co-first authors.

Sensors 2020, 20(18), 5355; https://doi.org/10.3390/s20185355

Received: 8 August 2020 / Revised: 6 September 2020 / Accepted: 15 September 2020 / Published: 18 September 2020

(This article belongs to the Special Issue Next-Generation Internet of Things (IoT): Opportunities, Challenges, and Solutions)

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Abstract

Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers. View Full-Text

Keywords: IoT; heterogeneous computing systems; fault tolerance; network-on-chip; router architecture; permanent fault

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MDPI and ACS Style

Rashid, M.; Baloch, N.K.; Shafique, M.A.; Hussain, F.; Saleem, S.; Zikria, Y.B.; Yu, H. Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things. Sensors 2020, 20, 5355. https://doi.org/10.3390/s20185355

AMA Style

Rashid M, Baloch NK, Shafique MA, Hussain F, Saleem S, Zikria YB, Yu H. Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things. Sensors. 2020; 20(18):5355. https://doi.org/10.3390/s20185355

Chicago/Turabian Style

Rashid, Muhammad, Naveed K. Baloch, Muhammad A. Shafique, Fawad Hussain, Shahroon Saleem, Yousaf B. Zikria, and Heejung Yu. 2020. "Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things" Sensors 20, no. 18: 5355. https://doi.org/10.3390/s20185355

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Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

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