Next Article in Journal
Coalition Formation Based Compressive Sensing in Wireless Sensor Networks
Previous Article in Journal
The Odor Characterizations and Reproductions in Machine Olfactions: A Review
Previous Article in Special Issue
A Software-Defined Networking Framework to Provide Dynamic QoS Management in IEEE 802.11 Networks
Article Menu
Issue 7 (July) cover image

Export Article

Open AccessArticle
Sensors 2018, 18(7), 2330;

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Istituto Superiore Mario Boella (ISMB), 10138 Torino, Italy
Simula Research Laboratory, 1325 Lysaker, Norway
IT4Innovations, VSB-University of Ostrava, 70833 Ostrava–Poruba, Czech Republic
These authors contributed equally to this work.
Author to whom correspondence should be addressed.
Received: 11 June 2018 / Revised: 11 July 2018 / Accepted: 12 July 2018 / Published: 18 July 2018
(This article belongs to the Special Issue Software-Defined Networking Based Mobile Networks)
Full-Text   |   PDF [976 KB, uploaded 18 July 2018]   |  


The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers and general purpose hardware designers to provide more efficient and scalable systems. Cloud-based infrastructures must consist of more energy efficient components. The evolution must take place from the core of the infrastructure (i.e., data centers (DCs)) to the edges (Edge computing) to adequately support new/future applications. Adaptability/elasticity is one of the features required to increase the performance-to-power ratios. Hardware-based mechanisms have been proposed to support system reconfiguration mostly at the processing elements level, while fewer studies have been carried out regarding scalable, modular interconnected sub-systems. In this paper, we propose a scalable Software Defined Network-on-Chip (SDNoC)-based architecture. Our solution can easily be adapted to support devices ranging from low-power computing nodes placed at the edge of the Cloud to high-performance many-core processors in the Cloud DCs, by leveraging on a modular design approach. The proposed design merges the benefits of hierarchical network-on-chip (NoC) topologies (via fusing the ring and the 2D-mesh topology), with those brought by dynamic reconfiguration (i.e., adaptation). Our proposed interconnect allows for creating different types of virtualised topologies aiming at serving different communication requirements and thus providing better resource partitioning (virtual tiles) for concurrent tasks. To further allow the software layer controlling and monitoring of the NoC subsystem, a few customised instructions supporting a data-driven program execution model (PXM) are added to the processing element’s instruction set architecture (ISA). In general, the data-driven programming and execution models are suitable for supporting the DL applications. We also introduce a mechanism to map a high-level programming language embedding concurrent execution models into the basic functionalities offered by our SDNoC for easing the programming of the proposed system. In the reported experiments, we compared our lightweight reconfigurable architecture to a conventional flattened 2D-mesh interconnection subsystem. Results show that our design provides an increment of the data traffic throughput of 9.5% and a reduction of 2.2× of the average packet latency, compared to the flattened 2D-mesh topology connecting the same number of processing elements (PEs) (up to 1024 cores). Similarly, power and resource (on FPGA devices) consumption is also low, confirming good scalability of the proposed architecture. View Full-Text
Keywords: many-core; software-defined NoC; data-driven many-core; software-defined NoC; data-driven

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

Share & Cite This Article

MDPI and ACS Style

Scionti, A.; Mazumdar, S.; Portero, A. Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud. Sensors 2018, 18, 2330.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics



[Return to top]
Sensors EISSN 1424-8220 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top