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Open AccessArticle

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

Samsung Electronics, Hwaseong-si, Gyeonggi-do 18448, Korea
School of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Korea
School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA
Author to whom correspondence should be addressed.
Academic Editors: Luis Javier Garcia Villalba, Anura P. Jayasumana and Jun Bi
Sensors 2017, 17(2), 426;
Received: 30 November 2016 / Revised: 12 February 2017 / Accepted: 17 February 2017 / Published: 22 February 2017
(This article belongs to the Special Issue Advances on Resources Management for Multi-Platform Infrastructures)
Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. View Full-Text
Keywords: through-silicon via; stereo matching processor; technology scaling; low-power through-silicon via; stereo matching processor; technology scaling; low-power
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Ok, S.-H.; Lee, Y.-H.; Shim, J.H.; Lim, S.K.; Moon, B. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. Sensors 2017, 17, 426.

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