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Sensors 2017, 17(10), 2232;

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan
These authors contributed equally to this work.
Author to whom correspondence should be addressed.
Received: 22 August 2017 / Revised: 21 September 2017 / Accepted: 27 September 2017 / Published: 28 September 2017
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This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. View Full-Text
Keywords: spike sorting; VLSI; competitive learning; brain machine interface spike sorting; VLSI; competitive learning; brain machine interface

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Chen, H.-Y.; Chen, C.-C.; Hwang, W.-J. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks. Sensors 2017, 17, 2232.

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