An overall resource and power assessment is then presented.

#### 2.1.1. Carrier

Assuming that all RF signals are taken down to a common Intermediate Frequency (IF), it then becomes possible to track any GNSS signal with the proposed universal channel. In order to accommodate most GNSS signals, a 30 MHz processed bandwidth appears to be a good compromise. This imposes a 60 MHz real sampling frequency and a 15 MHz Intermediate Frequency (IF), common to all RF bands. This architecture is thus compliant with all open signals.

A local carrier complex oscillator (namely a pair of sinusoidal 64-point waveforms in phase quadrature and encoded on 4 bits) is used to convert the IF signal down to baseband. Furthermore, in order to preserve a low architecture complexity, a signed multiplication optimization is proposed: $Y\text{bits}\times Z\text{bits}=\left(Y+Z-1\right)\text{bits}$. This is true only if the minimal twos complement value is never used on both operands, e.g., $0\mathrm{b}0000\times 0\mathrm{b}0000$ would not be permitted in such 4-bit multiplications.

The flexibility offered by this frequency down-conversion allows simplifying the RF front-end. Indeed, a common RF front-end could be used to manage signals on carriers nearby one another, such as:

More importantly, dealing with the several frequency channels of the GLONASS FDMA scheme requires a Numerically Controlled Oscillator (NCO) frequency span over several MHz,

i.e.,

$\left[-7,6\right]\cdot 0.5625=7.3125$ MHz for L1OF and equivalently

$5.6875$ MHz for L2OF:

This NCO span represents a large increase compared to the traditional ±10 kHz required for Doppler removal for a high-dynamics receiver.

#### 2.1.2. Sub-Carriers

As seen in

Table 1, signal modulations involve up to two sub-carriers combined in different phase relations. In fact, a phase-controlled sub-carriers generation module based on a single NCO makes up a universal channel. This NCO is used to derive up to two slower periodic signals from a third one (

i.e., SC2); the slowest signal being used to dictate the chipping rate of the primary spreading code. By doing so, an NCO phase ambiguity issue arose, which was overcome with the introduction of a SC2 period counter used in the navigation solution algorithm.

To properly deal with signals characterized by a quarter of a cycle phase shift between chip transition and carrier rising edge (

i.e., cBOC), a minimalistic approach requires a source clock with twice the required rate and a dual-edge register, as depicted in

Figure 2. This approach would equally apply to Galileo E1A signal with

$\text{cBOC}\left(15,2.5\right)$, where a sub-carrier six times that of the spreading code rate, both clock signals being in phase quadrature.

Another requirement brought up by the sub-carriers is their respective weight in time. Indeed, the TMBOC pilot component requires the ability to null (i.e., switch off) sub-carriers in time. To be future-compliant with any periodicity length, applied on any sub-carrier, a single 16 kbit RAM block is used, achieving a maximum periodicity of 512 addresses × 32 bits/(2 components × 2 sub-carriers) = 4096. To use it efficiently, the RAM block is configured as a dual port RAM, written from the 32-bit data bus until the RAM is filled up, but only four bits are read per address to accommodate data and pilot components at once.

Furthermore, CBOC and TMBOC impose different sub-carrier amplitudes. Pursuing a matched filter approach, the replica should mimic the targeted signal as much as possible. The resulting weighing factors α for sub-carrier SC1 and β for SC2 must carry the following values:

$\alpha \in \left[1,0.95,0\right]$ and

$\beta \in \left[1,\pm 0.30,0\right]$. The signed resolution requires a total of 6 signed bits to induce a representative ratio between one another:

$\frac{\beta}{\alpha}=\frac{0.30}{0.95}=\frac{6/32}{19/32}$ with

$\alpha +\beta =25/32$, introducing a potential scaling loss. These 6-bit coefficients may be updated at every chip in this simple TMBOC implementation, as depicted in

Figure 3. For example, during the sequential acquisition process, four steps are followed:

For each component, both 1-bit square sub-carriers are delayed to obtain Early (E), Prompt (P) and Late (L) replicas; the correlator spacing is set to $\pm {T}_{s}/4$ with the fastest sub-carrier period ${T}_{s}$.

Prompt and Differential (D = E − L) are obtained on 2 bits for each sub-carrier.

P & D replicas are scaled to their pre-defined constant weight through a mapping function or Look-Up Table (LUT).

For each component, the two scaled sub-carriers are summed.

#### 2.1.3. Spreading Codes

As seen in

Table 1, codes have different lengths and generation methods. Since all signals have their own primary (and secondary) code generation method, a universal channel would need to support them all. Linear Feedback Shift Register (LFSR) logic is definitely the best approach in the case of a dedicated signal channel. However, duplicating such resources customized for every signal becomes a burden: one channel can only track one signal at a time, resulting in many idle resources. Furthermore, considering this highly dynamic field, one may want to plan ahead. Indeed, a pre-computed memory code approach not only applies to all currently defined signals, but also allows for an easy, over-the-air, update link whenever a new Signal In Space (SIS) Interface Specification (IS) is released.

In recent GNSS signals, longer code periods also reduce the transit time integer ambiguity; the transit time for GPS satellites on L1 varies from about 66 ms (at zenith) to 80 ms (at horizon) [

34]. Hence, the longer the code duration, the smaller the resulting ambiguity becomes. To further improve on this, secondary codes are laid over the primary ones, artificially making them longer (while improving the inter-correlation protection). To account for the secondary code, whose length may vary from 4 to 1800 chips, the memory codes approach is once again adopted. Another side effect of these secondary codes is the basic integration time period: they constrain the coherent integration time to the primary code period, which in turn, limits the correlation gain achieved during acquisition (at early acquisition stages, while the secondary code is still unknown).

The only civil code for which the memory code approach is not suited is GPS L2CL. Indeed, CL is 767,250-chip long, which would impose a much too high upper bound on the size of the memory dedicated to each channel, especially if we consider two such memory blocks (one for each component). A more realistic memory block size is 16 kbit (a standard size for the Virtex4 [

35], on which the proposed universal channel is implemented), which is greater than 10,230—the second longest code, found on the L5, E5 and B3 signals. Hence, this requirement imposes two 16 kbit RAM blocks and a 27-register long LFSR as the minimum resources for each universal channel.

More importantly, the GPS L2C signal introduces an additional particularity,

i.e., the time multiplexing of two spreading codes of different lengths. The resulting merged code has twice the chipping rate compared to that of their individual sequences L2CM and L2CL, as seen in

Figure 4.

The 1.5 s long L2CL code cannot be acquired directly at cold start. Nevertheless, its chip offset can be predicted from the satellite clock timestamp decoded through L2CM or inferred from another signal from the same satellite. A full (L2CM & L2CL) integration may then occur, harvesting twice as much signal power compared to only L2CM during the acquisition phase.

#### 2.1.4. Correlation

In order to provide the feedback to the carrier and code NCOs, several feedback signals are required to compute the error to be compensated for. For the code, a Non-coherent Early Minus Late (NEML) discriminator requires three correlators,

i.e., E, P and L code replicas on both the phase (I) and quadrature (Q) branches as illustrated in

Figure 5. With the current implementation based on 4 16-bit addressable registers (as opposed to dedicated RAM blocks with improved delay resolution), the different code replica offsets may belong to

$P\pm 32/{f}_{S}$ samples, thus achieving a correlator spacing

$\mathsf{\Delta}=\pm \delta $ slightly larger than ±½ chip for a 1.023 Mchip/s spreading code. The resulting 6 correlators are deployed for both components of a signal.

To reduce the correlator number, the Delay Lock Loop (DLL) discriminator could only involve in-phase (carrier and eventually sub-carrier phases) measurements, thus requiring a lock on the Phase Lock Loop (PLL) (and eventually Sub-carrier Lock Loop or SLL). Such a coherent approach may not be as robust as its non-coherent equivalent [

36].

Hodgart, Blunt and Unwin [

37] specify that an SLL provides more precise (due to higher rate), but ambiguous (periodic clock signal) measurements compared to the DLL based on the primary code Pseudo-Random Noise (PRN). Both these estimates may be combined as:

where:

- ${\widehat{\tau}}^{+}$
is the combined delay estimate;

- ${\widehat{\tau}}^{*}$
is the sub-carrier delay estimate;

- ${\widehat{\tau}}^{}$
is the code delay estimate;

- ${T}_{s}$
is the sub-carrier half-period.

To keep the correlator count as low as possible, the sub-carriers are weighted

$\left(\alpha ,\beta \right)$ and summed,

i.e., SC2 + SC1, prior correlation, avoiding an extra loop. Also, only Prompt (P) and Differential (D = E − L) instances are used to implement the NEML sub-carriers discriminator. Note that combining the sub-carriers also simplifies the discriminator, which then becomes identical as the Dual Estimator (DE), rather than the Triple Estimator (TE) extension for MBOC [

25], with the same performances.

Having higher chipping rates requires greater accumulation registers. Multiplication and accumulation are performed through a DSP48 slices available in the Xilinx XC4VSX55-10FF1148 Field Programmable Gate Array (FPGA). Hence, the number of bits for these operations is not critical, as long as it remains below $48-{\mathrm{log}}_{2}\left(60,000\right)\approx 32$, assuming the integration of 60,000 samples in 1 ms.

Coherent integration provides better post-correlation Signal to Noise Ratios (SNR) than non-coherent ones, where navigation bit (or secondary chip) removal introduces squaring losses [

38]. The navigation data period limits the coherent integration time, thus imposing a lower limit on the sensitivity of an unaided, stand-alone receiver.

#### 2.1.6. Discriminator and Filter

In a multi-signal receiver, the phase relationship from one signal to another may not be cancelled out as part of a common timing error and must thus be specifically accounted for. Similarly, dual-component signals are bound by their phase relationship. With a standard definition where the quadra-phase component leads the in-phase one, we have:

That is to say, an in-phase (e.g., sin) signal (such as GPS L1CI) may use the $I$ and $Q$ correlator values, while a signal in phase quadrature (e.g., cos) with its RF carrier (such as GPS L1 C/A) should use $\u2013Q$ and $I$. In the current implementation, the discriminators are programmed into the embedded MicroBlaze controller, thus allowing for great flexibility. Basically, any coherent and/or non-coherent discriminator could be used based on the signal characteristics; this is simpler than generating sinusoidal waveforms with different phases.

More precisely, considering the infinite bandwidth signal auto-correlation function,

Figure 6 shows that the BOC main peak has a slope of

$\pm 1.5n$ and a correlation main peak width of

$\pm \frac{1}{n}$ chip, with the BOC modulation ratio

$n=2\cdot \frac{{f}_{s}}{{f}_{c}}=2\cdot \frac{p}{q}$. However, the squaring involved in non-coherent correlation steepens the peak slopes: which can be approximated by

$\pm 2n$ between the correlation peak and the zero-amplitude level, separated by approximately

$\pm \frac{1}{2n}$ chip. The coherent correlator spacing should not extend beyond

$\pm \frac{1}{n}$ chip, above which an inversion of the EML discriminator S-curve in

Figure 7 could compromise the DLL behavior (

i.e., it would amplify the error) [

39]. Each one of the

$2\left(n-1\right)$ side peaks in the squared BOC correlation function leads to a potential false-lock (

i.e., a biased discriminator output) as a result of as many side S-curves.

Also, a rule of thumb imposes, neglecting dynamic stress error ([

8] (Chapter 5):

The normalized correlation function $R\left(\tau \pm \delta \right)$ is estimated by its main peak positive and negative slopes: $\left\{1+m\left(\tau -\delta \right)\right\}$ and $\left\{1-m\left(\tau -\delta \right)\right\}$ with EML correlators spaced by $\pm \delta $ chip and a chip code delay error $\left|\tau \right|<\frac{1}{2n}-\delta $. The EML tracking architectures for BOC, should offer a code tracking improvement of $m$ over BPSK.

In non-coherent discriminators,

$C/{N}_{0}$ squaring losses are due to doubled random noise, while the ±1 data is wiped off. Non-coherent processing would typically be 3 dB less sensitive than coherent processing for a given duration, although it allows for much longer integration periods, thus achieving a better overall sensitivity. This squaring loss was isolated in square brackets in the code noise jitter equations below. Hence, in non-coherent discriminators, the associated code noise may have a larger variance while preserving the same null mean. It is well known that code phase jitter performances depend on the slope of the discriminator curve (

i.e., better performances for steeper slopes). In fact, the code phase 1

$-\sigma $ error (m) derived from the non-coherent Early Minus Late Power (EMLP) code discriminator closed loop noise variance (squared chip periods) are defined as (extended from [

12,

40] to BOC derived modulations):

where:

- $c$
is the speed of light (m/s);

- ${T}_{c}$
is the chip period, the inverse of the chipping rate ${f}_{c}$;

- ${B}_{L}$
is the unilateral noise equivalent bandwidth of the code tracking loop, a.k.a. one-sided equivalent rectangular bandwidth, with the time frame of interest $\u03f5\left[1/{B}_{L},{T}_{obs}\right]$;

- ${T}_{P}$
is the pre-integration time (s);

- $\tau $
is the signal vs. replica misalignment (chip);

- $\mathsf{\Delta}$
is the early-late correlator spacing (chip), i.e, $2\cdot \delta $;

- $\delta $
is the early to prompt and prompt to late correlator spacing (chip);

- $\raisebox{1ex}{$C$}\!\left/ \!\raisebox{-1ex}{${N}_{0}$}\right.$
is the Carrier power to Noise density ratio (dB-Hz);

- $m$
is the slope of the correlation function;

- $b$
is the normalized receiver front-end complex bandwidth $\left({\beta}_{r}\cdot {T}_{c}/n\right)$;

- ${\beta}_{r}$
is the ideal front-end complex bandwidth (with a brick-wall filter (Hz)).

In Equation (12), the term in square brackets reflects the squaring losses attributed to the non-coherent discriminator computations, while the term in braces results from approximations depending on the value of

$\mathsf{\Delta}\cdot b$. Given a fix front-end bandwidth and an equivalent chip spacing during tracking, the approximation mainly involves the signal modulation represented by

${T}_{c}/n$. The Cramer-Rao Lower band is reported by Betz

et al. [

40] to be:

It thus becomes interesting to determine what DLL noise variance can be expected for each GNSS signal when tracked with the proposed channel. Analysis in [

40] reports that for limited front-end bandwidths, the discriminator gain diminishes as the early-late correlator spacing

$\mathsf{\Delta}$ decreases, while increasing the loop bandwidth and thus the loop variance. Three discriminator regions are identified as: Spacing-Limited, Transition and Bandwidth-Limited, in accordance with Equation (12). Looking at MBOC, while assuming

${\beta}_{r}=22.3$ MHz and

${T}_{c}/n=1/\left(12\cdot 1.023\times {10}^{6}\right)$,

$b\approx 2$ for the BOC(6,1) signal component, which rapidly falls under the Bandwidth-Limited during tracking area with

$\mathsf{\Delta}\le 0.5$ chip. One should bear in mind that the relative power ratio of BOC(6,1) is one tenth that of BOC(1,1), for which

$b\approx 12$, well within the Spacing-Limiting function. Looking at other GNSS signals, it appears that in the presented configuration,

$b$ ranges from 2 to 47, as depicted in

Figure 8. For signals where

b is high, it still is beneficial to reduce

$\delta $, also mitigating multipath errors. Nevertheless, unless dedicated RAM blocks are available for all the code phases used, a 60 MHz sampling frequency poses a 1 sample limit on

$\delta $ based on delayed code phases based on the shift registers approach described above, the impact of which will vary with the GNSS signal chipping rates.

#### 2.1.7. Power Consumption and Resource Usage

Table 3 summarizes both the power consumption, as obtained with the Xilinx ISE XPower software, and the FPGA resource usage for different tracking channel complexities, leading to the proposed universal channel. The power consumption percentages presented herein are taken relatively to the “BPSK with FDMA” reference implementation, assessing the overhead associated with the implementations derived with added feature sets.

It can be seen that the quiescent power is relatively constant across all implementations, and may be attributed to the chip itself, leaving the dynamic power as a more meaningful comparison metric. The single-component MBOC implementation consumes 33% more power, while the dual-component (data and pilot) requires twice as much, i.e., 66% increase compared to the reference BPSK implementation.

For each implementation, the absolute number of resources and associated percentage (vs. available) are presented. As a result, the proposed optimizations led to a dual-component MBOC universal channel of complexity comparable to that of two traditional BPSK reference channels, but with a lot more flexibility. For flexibility and maintainability, the universal channel has been implemented with VHDL configurations that can easy be changed to enable or not several feature sets.