Sensors 2015, 15(8), 19830-19851; https://doi.org/10.3390/s150819830
An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan
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Academic Editor: Vittorio M. N. Passaro
Received: 17 June 2015 / Revised: 5 August 2015 / Accepted: 7 August 2015 / Published: 13 August 2015
(This article belongs to the Section Physical Sensors)
Abstract
A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. View Full-TextKeywords:
spike sorting; VLSI; brain machine interface
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Chen, Y.-L.; Hwang, W.-J.; Ke, C.-E. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm. Sensors 2015, 15, 19830-19851.