Lattice Patch Structure for Fixed-Frequency Transmon Quantum Computer with High-Fidelity CNOT Gates

Abstract

Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit–coupler–qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code. To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler. This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability. Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual $R_z$ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.

1. Introduction

A variety of quantum computing algorithms, including Shor’s algorithm and Grover’s algorithm, have demonstrated both the necessity and the feasibility of implementing quantum computers. In particular, the potential of quantum computing to surpass the limits of classical computation has driven its rapid adoption across diverse industrial and research fields [1,2,3,4,5]. Among the various physical platforms for qubit implementation, superconducting systems are prominent candidates due to their rapid gate operation times and robust scalability [6,7,8,9,10,11]. Transitioning from the Noisy Intermediate-Scale Quantum (NISQ) era to practical quantum computation necessitates large-scale Quantum Error Correction (QEC) [12].

Surface codes, which implement logical qubits on a lattice structure, are central to QEC and are the subject of intense research within superconducting hardware development [13,14,15,16,17,18,19,20]. To date, superconducting architectures have primarily diverged into grid-based layouts (Google) and heavy-hexagon structures (IBM). While Google’s grid architecture—incorporating individual couplers between qubit pairs—allows for direct surface-code mapping, the escalating number of couplers in larger systems triggers performance degradation through unwanted interactions and crosstalk [21]. Conversely, IBM’s heavy-hexagon structure suppresses these interactions by reducing connectivity [22], yet it incurs mapping inefficiencies, such as the requirement for additional SWAP gate overhead. Furthermore, many current platforms utilize tunable couplers for gate control [23,24], which require dedicated flux-bias lines and expose the system to decoherence from flux noise [25].

To address these structural bottlenecks, research has shifted toward alternative hardware architectures. Recent proposals have explored coupling three fixed-frequency qubits to a single fixed-frequency coupler [26], demonstrating high gate fidelities via microwave-based control [27,28,29]. However, these configurations still face structural constraints when aligning with surface-code lattice units, necessitating complex mapping procedures for large-scale expansion.

In this work, we propose a “lattice-patch” architecture that integrates four fixed-frequency transmon qubits with a single fixed-frequency coupler. This design achieves topological alignment with the surface code, overcoming the mapping limitations of previous structures. By employing an entirely fixed-frequency configuration, we minimize sensitivity to flux noise and maximize physical stability. Through numerical simulations, we demonstrate CNOT gates across six distinct directions within the patch, establishing this architecture as an efficient and stable building block for next-generation fault-tolerant quantum computers.

2. System Configuration

The proposed architecture integrates four fixed-frequency transmon qubits with a single fixed-frequency coupler, a configuration we define as the Lattice-Transmon system.

2.1. Comparison of Hardware Architecture and Connectivity

Figure 1 illustrates the structural advantages of the Lattice-Transmon system relative to representative superconducting quantum computing architectures.

Conventional designs, such as Google’s grid architecture (Figure 1a) and IBM’s heavy-hexagon layout (Figure 1b), deploy individual couplers between every adjacent qubit pair to mediate direct interactions [8,9]. As systems scale, this approach leads to a prohibitive increase in the number of couplers and control lines. Moreover, during CNOT operations on a target qubit pair, these architectures are highly susceptible to parasitic interactions from the dense surrounding network of couplers and qubits [21]. In contrast, our proposed architecture (Figure 1c) utilizes a patch-based geometry where four qubits are locally coupled through a single central mediator. By minimizing the number of physical components involved in gate operations, this design significantly reduces hardware complexity and mitigates operational overhead [30].

2.2. Physical Model and Energy Level Design

The detailed architecture and circuit model of the proposed system are illustrated in Figure 2. The central fixed-frequency coupler is designed as an LC resonator, to which four transmon qubits are capacitively coupled with strengths $G_i$ (Figure 2a,b).

By utilizing entirely fixed-frequency components, we ensure the system is intrinsically robust against $1/f$ flux noise—a primary decoherence mechanism in superconducting qubits. To prevent frequency crowding, the operating frequencies of the qubits (${\omega }_i$) are designed with substantial detunings on the order of several hundred MHz. Furthermore, the coupler frequency is positioned approximately 2 GHz above the qubit frequency band. This high-frequency placement suppresses direct energy exchange between qubits and the coupler, allowing the latter to serve as a stable, dispersive mediator.

2.3. Definition of the System Hamiltonian

We formulate the system Hamiltonian $\widehat{\mathcal{H}}$ using a lumped-element circuit model. For computational convenience, we set $\hslash =1$. The total Hamiltonian is defined as the sum of the resonator (${\widehat{H}}_R$), transmon (${\widehat{H}}_T$), and interaction (${\widehat{H}}_I$) terms:

$$\widehat{H}={\widehat{H}}_R+{\displaystyle \sum _{i=0}^3}{\widehat{H}}_{T,i}\left(t\right)+{\widehat{H}}_I,$$

(1)

First, the coupler, implemented as an LC circuit, is modeled as a quantum harmonic oscillator. The Hamiltonian for the resonance frequency ${\omega }_C$ is given by:

$${\widehat{H}}_R={\omega }_C{\widehat{a}}^{†}\widehat{a},$$

(2)

where ${\widehat{a}}^{†}$ and $\widehat{a}$ denote the creation and annihilation operators, respectively.

Second, the Hamiltonian for each transmon qubit, ${\widehat{H}}_{T,i}$, is defined by its charging energy ($E_{C,i}$) and Josephson energy ($E_{J,i}$) [31,32]:

$${\widehat{H}}_{T,i}\left(t\right)=4E_{C,i}{({\widehat{n}}_i-n_{g,i}\left(t\right))}^2-E_{J,i}\cos {\widehat{\varphi }}_i,$$

(3)

where $\widehat{n}i$ is the Cooper-pair number operator, ${\widehat{\varphi }}_i$ is the phase operator, and $n_{g,i}\left(t\right)$ represents the external microwave voltage pulses applied for qubit control. The system is designed in the transmon regime ($E_J\gg E_C$) to ensure insensitivity to charge noise.

Third, the interaction between the coupler and qubits follows the Jaynes–Cummings model and is expressed as [33]:

$${\widehat{H}}_I={\displaystyle \sum _{i=0}^3}{G}_i(\widehat{a}+{\widehat{a}}^{†}){\widehat{n}}_i.$$

(4)

where $Gi$ represents the coupling strength between the coupler and the i-th qubit.

Given the reliance on fixed-frequency elements, minimizing the residual $ZZ$ interaction during the idle state is critical [34]. By optimizing qubit detunings within the dispersive regime, we suppress unintended parasitic phase accumulation in the computational basis. This design strategy serves as a foundation for mitigating crosstalk in large-scale lattice expansions.

2.4. Numerical Simulation and Multi-Level Considerations

To accurately simulate gate dynamics within a realistic hardware environment, we model the transmons as multi-level systems rather than simple two-level systems. This approach enables a rigorous analysis of leakage errors into non-computational states during gate execution [35]. The total Hilbert space of the system is defined by the tensor product of the resonator’s Fock states and the eigenbasis of each transmon:

$$\mathcal{S}={|k\rangle }_R\otimes {\displaystyle \underset{i=0}{\overset{3}{⨂}}}|m_i\rangle ,(k,m_i\in 0,1,2).$$

(5)

To balance computational efficiency with numerical accuracy, we include the three lowest energy levels ($|0\rangle ,|1\rangle ,|2\rangle$) for each component. By monitoring state transitions out of the computational basis $\left\{\right|0\rangle ,|1\rangle \}$, we identified the optimal parameters required for achieving high-fidelity gate performance.

3. Pulse Protocol and Quantum Gatme Optimization

In this section, we discuss the pulse design strategies and numerical optimization procedures required to implement high-fidelity two-qubit gates within the constrained lattice-patch architecture. Our control protocol utilizes a cross-resonance (CR) pulse-based framework, which has been previously validated in a system coupling three fixed-frequency qubits to a single fixed-frequency coupler [36]. By adapting and expanding this established approach to our proposed architecture, we aim to demonstrate that structural scalability and operational consistency can be maintained even under a more complex interaction environment.

3.1. Control Strategy and Scability

Compared to the previous researching structure coupling three qubits to a single fixed-frequency coupler, the proposed architecture introduces a more pronounced frequency crowding problem, which inherently exacerbates parasitic crosstalk. Despite these physical challenges, we retain the exact pulse framework established in previous literature to verify the physical viability and operational feasibility of our proposed hardware. Maintaining this identical pulse framework ensures its universal applicability within the local patch, thereby offering significant architectural advantages for scaling up large-scale quantum processors.

3.2. Parameter Optimization

Optimizing pulse parameters in superconducting qubit systems not only demonstrates hardware viability but also elucidates the potential limitations and future scalability of the proposed system. To implement the system, we employ two primary pulse types: a CR pulse to induce conditional interactions between the control and target qubits, and a DRAG-based Gaussian flat-top pulse to finalize the CNOT gate implementation. Optimizing the gates using each pulse type serves as a critical metric for evaluating the performance of the proposed system, making the optimization process a key technical challenge. To optimize these pulse parameters, we performed a grid search via a comprehensive parameter sweep.

In this simulation, to demonstrate that CNOT gates can be implemented across all connectivity directions, we realized a total of twelve gates: six forward CNOT gates ($CNO{T}_{01},CNO{T}_{02},CNO{T}_{03},CNO{T}_{12},CNO{T}_{13},CNO{T}_{23}$) and six reverse CNOT gates ($CNO{T}_{10},CNO{T}_{20},CNO{T}_{21},CNO{T}_{30},CNO{T}_{31},CNO{T}_{32}$). For the reverse gates, we leveraged the pulses already developed for the forward operations and applied an additional Gaussian pulse to achieve the reverse implementation. Specifically, the pulse used for the reverse operations was configured by additionally applying the same Gaussian flat-top gate sequence used in the forward CNOT gate framework. Consequently, to optimize the reverse CNOT gates, it is also necessary to optimize the auxiliary parameters introduced by these additional pulses.

3.3. Pulse Parameter Initization and Pulse Composition

To implement the CNOT gate, the cross-resonance (CR) pulse is characterized by five parameters, $(f_1,T_S,{\Omega }_S,\rho ,{\gamma }_1)$, while the Gaussian pulse relies on four parameters, $(f_2,T_X,{\Omega }_X,{\gamma }_2)$. Consistent with the approach used in the 1-coupler-3-qubit system, the initial values for the CR pulse parameters were set to $(f_1,T_S,{\Omega }_S,\rho ,{\gamma }_1)=(f_{\mathrm{target} \mathrm{qubit}},150,0.05,0.1,0)$. A grid search was subsequently conducted via parameter sweeps with step sizes or ranges of $[0.01,5,0.01,5,0]$ for each respective parameter.

For the Gaussian pulse, the four parameters $(f_2,T_X,{\Omega }_X,{\gamma }_2)$ were initialized to $(f_2,T_X,{\Omega }_X,{\gamma }_2)=(f_{\mathrm{target} \mathrm{qubit}}10,0.01,0)$, following the same methodology as the 1-coupler-3-qubit system. This was also optimized using a grid search via parameter sweeps within the bounds of $[0.01,1,0.005,0.01\pi ]$. In particular, the phase parameter for the Gaussian pulse was meticulously scanned across the range of $[-\pi ,\pi ]$ with a fine interval of 0.01.

It is worth noting that in demonstrating the reverse gate fidelities in this study, the pulses for single-qubit gates and their associated physical errors were not explicitly modeled. This is because the single-qubit error rate in current superconducting transmon processor platforms is remarkably low $(\sim$${10}^{-4})$, making it negligible compared to that of two-qubit gates like the CNOT gate. Furthermore, the primary objective of this work is to introduce and validate a novel architecture where four qubits are coupled to a single mediator. Specifically, the implementation of the reverse gate aims to confirm that a bidirectional CNOT gate can be successfully achieved not by driving the conventional control qubit, but rather by applying the CR pulse to the target qubit.

The applied microwave drive pulses $n_{g,i}\left(t\right)$ conform to the assumed physical model and are designed to interact with the four-qubit energy spectrum via the pre-configured driving Hamiltonian. Figure 3a illustrates the pulse sequence for the forward CNOT gate, while Figure 3b displays the pulse sequence for the reverse CNOT gate.

The pulse sequence employed here is identical to the framework used in the conventional 1-coupler-3-qubit system, and its detailed description is as follows:

• Simple Cross-Resonance Pulse Design: We utilized the most foundational, simple CR pulse scheme to validate the structural feasibility of our 1-coupler-4-qubit architecture. By employing this basic CR drive, our primary objective was to demonstrate that conditional dynamics between two qubits can be successfully realized even within this expanded hardware topology.
• Leakage Suppression via DRAG: To mitigate frequency crowding and prevent leakage into higher energy levels, we apply the Derivative Removal by Adiabatic Gate (DRAG) technique to all Gaussian pulse envelopes:

  $$n_{g,i}\left(t\right)={\Omega }_G\left(t\right)\cos (2\pi f_{i}t-{\gamma }_i)+{\beta }_i{\dot{\Omega }}_G\sin (2\pi f_{i}t-{\gamma }_i).$$

  (6)

  where the scaling parameter ${\beta }_i$ is set to $0.5/E_C$ to effectively suppress charge-noise sensitivity and transitions to higher-order levels.

3.4. Flexibility in Reverse-Directional Gate Implementation

Despite the reliance on fixed-frequency components, our architecture enables the efficient implementation of bidirectional CNOT gates through pulse-level calibration (Figure 3b). Rather than wrapping a forward-direction gate with virtual Hadamard transformations, we ensure gate robustness by physically optimizing auxiliary pulses. This optimization explicitly accounts for the hardware-specific coupling strengths ($G_i$) and frequency detunings, allowing for high-performance operations in both directions.

3.5. Numerical Optimization and Validation Methodology

To evaluate the impact of the designed pulses on the system Hamiltonian and derive the final unitary operator $\widehat{\mathcal{U}}$, we perform numerical optimization based on the time-dependent Schrödinger equation. The system Hamiltonian is formulated as the sum of a static term (${\widehat{H}}_0$) and a pulse-controlled driving term (${\widehat{H}}_1\left(t\right)$):

$$\widehat{H}\left(t\right)={\widehat{H}}_0+{\widehat{H}}_1\left(t\right).$$

(7)

We calculate the time evolution over the total pulse duration T using a Dyson series expansion. For enhanced numerical precision, we employ a Suzuki-Trotter decomposition [37,38]:

$$\exp (-i\tau \widehat{H}\left(\tilde{t}\right))\simeq \exp (-i\tau {\widehat{H}}_0/2)V\exp (-i\tau \widehat{\Lambda }\left({\tilde{t}}_n\right))V^{†}\exp (-i\tau {\widehat{H}}_0/2).$$

(8)

where $\widehat{\Lambda }\left({\tilde{t}}_n\right)=V^{†}{\widehat{H}}_1\left({\tilde{t}}_n\right)V$, and V denotes the transformation matrix composed of the eigenvectors corresponding to the transmon qubit states. The time step $\tau$ is chosen to guarantee numerical convergence and satisfy the required error bounds. In this study, we adopt a fine interval of $\tau =0.001$ ns to minimize higher-order truncation errors and ensure the reliability of the calculated gate fidelities.

When performing the time evolution of the aforementioned Hamiltonian, the high-frequency oscillations intrinsic to the qubits impose physical and numerical limitations on interpreting the qubit system. To circumvent this challenge, it is necessary to transition from the current laboratory (Lab) frame to a rotating frame. Since this frame transformation must be applied universally across the Hamiltonian terms partitioned via the Suzuki-Trotter decomposition, the frame transition is executed by incorporating additional gauge-like operational terms into the Hamiltonian. The corresponding governing equation can be expressed as follows:

$$\begin{array}{c}\exp (-i\tau {\widehat{H}}_0/2)\to \exp (-i\tau ({\widehat{H}}_0+i\dot{R}{R}^{†}/2)),\\ {\widehat{U}}_{\mathrm{final}}=\exp (-i\tau ({\widehat{H}}_0+i\dot{R}{R}^{†}/2))RV\exp -i\widehat{\Lambda }{\left(\right(\tilde{t})}_n)V^{†}{R}^{†}\exp (-i\tau ({\widehat{H}}_0+i\dot{R}{R}^{†}/2)).\end{array}$$

(9)

where R and $\dot{R}$ are defined as follows:

$$R\left(t\right)=\left[\begin{array}{ccc}0& 0& 0\\ 0& e^{i\omega t}& 0\\ 0& 0& e^{2i\omega t}\end{array}\right],\dot{R}={\displaystyle \frac{d}{dt}}R\left(t\right)=\left[\begin{array}{ccc}0& 0& 0\\ 0& i\omega e^{i\omega t}& 0\\ 0& 0& 2i\omega e^{2i\omega t}.\end{array}\right]$$

(10)

By incorporating these frame-transformation terms, we perform numerical simulations that effectively account for the high-frequency dynamics within the Hamiltonian evaluation.

Furthermore, we apply virtual-Z gate techniques to compensate for residual phase errors post-pulse application, yielding the final unitary matrix $\widehat{\mathcal{U}}\mathrm{total}$ [39]:

$${\widehat{R}}_z^{\left(\mathbf{v}\right)}\left(\theta \right)={\displaystyle \underset{i=0}{\overset{3}{⨂}}}{R}_z^{\left(i\right)}\left({\theta }_i\right),{\widehat{\mathcal{U}}}_{\mathrm{total}}={\widehat{R}}_z^{\left(\mathbf{v}\right)}\widehat{\mathcal{U}}.$$

(11)

Gate performance is quantified by the average gate fidelity ($F_{\mathrm{avg}}$), calculated via numerical Monte Carlo integration over $M={10}^4$ samples:

$$F_{\mathrm{avg}}={\displaystyle \frac{1}{M}}{\displaystyle \sum _{j=1}^M}|\langle {\psi }_j|{\widehat{\mathcal{U}}}_{\mathrm{opt}}^{†}{\widehat{\mathcal{U}}}_{\mathrm{total}}|{\psi }_j{\rangle |}^2.$$

(12)

Since the final unitary gate incorporated with the virtual-Z (VZ) gates may not yet represent a fully optimized pulse configuration, an additional fine-tuning optimization process is conducted. Based on the approximate parameter regions identified via the initial grid search sweep, these discovered points are set as the initial coordinates. Subsequently, the derivative-free Nelder–Mead simplex algorithm is executed to further enhance the fidelity and performance of the implemented gate. The comprehensive optimization protocol for the final unitary operator ${\mathcal{U}}_{\mathrm{final}}$ is structured as follows:

• Initial Point Setup:
  The parameters swept during the primary CR and Gaussian pulse calibrations are utilized to construct the initial points within the proximity of the optimal region. Starting the derivative-free Nelder–Mead algorithm from these pre-localized coordinates is crucial to prevent the optimizer from getting trapped in unfavorable local minima.
• Loss Function Setup:
  To drive the optimization process, we define a loss function $\mathcal{L}$. This loss is formulated using the average gate fidelity $F_{\mathrm{avg}}$ calculated from the implemented unitary operator ${\mathcal{U}}_{\mathrm{total}}$ evaluated over random states $|\psi \rangle$ spanning the computational basis. The loss function $\mathcal{L}$ is computed as follows:

  $$\mathcal{L}=1-F_{\mathrm{avg}}.$$

  (13)
• Convergence Criteria:
  The optimization process is terminated and deemed converged when either the variation in the simplex size $\Delta x$ within the parameter space or the fractional change in the loss function $\Delta \mathcal{L}$ drops below a predefined threshold of ${10}^{-4}$, indicating that no further numerical improvement is achievable.

This rigorous validation framework demonstrates that the proposed lattice-patch architecture achieves high operational reliability within a complex four-qubit network while maintaining the control simplicity of previous microwave-only schemes.

4. Setting Parameters of the Lattice-Transmon System

In this section, we present the hardware specifications and optimized gate parameters to demonstrate the physical viability of the proposed Lattice-Transmon system. We further validate the architectural effectiveness through numerical simulations, analyzing the resulting success probabilities and gate fidelities.

4.1. Hardware Specifications and Frequency Allocation

The hardware parameters for the proposed system are detailed in

Table 1. Hardware specifications.

	C	${\mathit{Q}}_0$	${\mathit{Q}}_1$	${\mathit{Q}}_2$	${\mathit{Q}}_3$
$\omega /2\pi$	7.0	5.03260	4.91339	4.79421	4.67259
$E_{C,i}/2\pi$	–	0.33	0.32	0.31	0.3
$E_{J,i}/2\pi$	–	11.0	10.8	10.6	10.4
$G_i/2\pi$	–	0.06	0.05	0.03	0.06

. This study extends a previously validated model to a four-qubit architecture, with qubit operating frequencies ranging from ${\omega }_0/2\pi =5.03260$ GHz to ${\omega }_3/2\pi =4.67259$ GHz. These frequencies are designed to coincide with the eigenfrequencies of the system Hamiltonian in the absence of external driving pulses.

To mitigate frequency crowding—a common bottleneck in large-scale processors—we maintained inter-qubit detunings between 100 and 300 MHz. Furthermore, by assigning distinct qubit–coupler coupling strengths ($G_i$), we analyzed how variations in coupling affect gate implementation and overall performance. To quantify the crosstalk in our system, the residual $ZZ$ interaction strength ${\zeta }_{ij}$ between qubits i and j is defined as follows:

$${\zeta }_{ij}=E_{|1_i{1}_j\rangle }-E_{|1_i{0}_j\rangle }-E_{|0_j{1}_i\rangle }+E_{|0_j{0}_i\rangle }.$$

(14)

Moreover, to evaluate the multi-body crosstalk across the entire four-qubit system, we investigate the fourth-order residual $ZZ$ interaction ${\zeta }_{1111}$, which is expressed as:

$$\begin{array}{cc}\hfill {\zeta }_{1111}=& E_{|1110\rangle }-(E_{|1101\rangle }+E_{|1011\rangle }+E_{|0111\rangle })\hfill \\ \hfill & +(E_{|1100\rangle }+E_{|1010\rangle }+E_{|1001\rangle }+E_{|0110\rangle }+E_{|0101\rangle }+E_{|0011\rangle })\hfill \\ \hfill & -(E_{|0001\rangle }+E_{|0010\rangle }+E_{|0100\rangle }+E_{|1000\rangle })+E_{|1111\rangle }\hfill \end{array}$$

(15)

The resulting residual $ZZ$ interactions for the system are summarized in

Table 2. Residual ZZ Interactions (MHz).

${\mathit{\zeta }}_{01}$	${\mathit{\zeta }}_{02}$	${\mathit{\zeta }}_{03}$	${\mathit{\zeta }}_{12}$	${\mathit{\zeta }}_{13}$	${\mathit{\zeta }}_{23}$	${\mathit{\zeta }}_{1111}$
0.02339	0.01164	0.16352	0.00536	0.03352	0.00811	0.23288

.

4.2. Optimization of CNOT Gate Pulse Parameters

Table 3. Forward CNOT gate parameters.

Gate	${\mathit{f}}_1$ [GHz]	${\mathit{f}}_2$ [GHz]	${\mathit{T}}_{\mathit{S}}$ [ns]	${\mathit{T}}_{\mathit{X}}$ [ns]	${\mathbf{\Omega }}_{\mathit{S}}$	${\mathbf{\Omega }}_{\mathit{X}}$	$\mathit{\rho }$	${\mathit{\gamma }}_1$	${\mathit{\gamma }}_2$
${\mathrm{CNOT}}_{01}$	4.91339	4.91339	220	9	0.05	0.01	0.178	0	0.776
${\mathrm{CNOT}}_{02}$	4.79396	4.79421	295	10	0.07	0.01	0.12	0	0.5
${\mathrm{CNOT}}_{03}$	4.67257	4.67259	200	10	0.06	0.025	0.3	0	−0.05
${\mathrm{CNOT}}_{12}$	4.79398	4.79421	440	10	0.05	0.017	0.1	0	0.03
${\mathrm{CNOT}}_{23}$	4.67298	4.67259	400	10	0.075	0.003	0.1	0	0.87

lists the optimized pulse parameters for the six forward-direction CNOT gates implemented in this architecture. Each gate protocol was optimized by applying a Cross-Resonance (CR) drive at the target qubit frequency ($f_2$), integrated with Gaussian auxiliary pulses to cancel parasitic interactions. To maximize gate fidelity, we performed fine-frequency sweeps within a $\pm 10$ MHz range and optimized the ramp parameter ($\rho$) to refine the pulse rise and fall times, thereby minimizing leakage into higher-order energy levels.

Note that the amplitude parameters ${\Omega }_S$ and ${\Omega }_X$ are expressed as dimensionless scaling factors incorporated into the driving Hamiltonian, effectively corresponding to the normalized Rabi frequencies. For the implementation of reverse CNOT gates, we utilized a protocol where virtual Hadamard gates were applied to the control and target qubits based on the forward unitary.

The auxiliary drives used for these reverse operations share the same Gaussian flat-top envelope configuration as the forward gates. Specifically, the optimized pulse parameters are specified by the tuple $(f,T,\Omega ,\gamma )$, which represent the target qubit frequency, total pulse duration, dimensionless pulse amplitude, and initial phase, respectively. Detailed parameters for each reverse CNOT gate configuration are provided in

Table 4. Reverse CNOT gates parameters.

Gate	f [GHz]	T [ns]	$\mathbf{\Omega }$	$\mathit{\gamma }$
${\mathrm{CNOT}}_{10}$	4.91339	16	0.03	−0.78
${\mathrm{CNOT}}_{20}$	4.79421	45	0.04	0.5
${\mathrm{CNOT}}_{30}$	4.67259	42	0.01	−0.15
${\mathrm{CNOT}}_{21}$	4.99421	41	0.032	−0.9
${\mathrm{CNOT}}_{32}$	4.67259	10	0.015	0.6

and

Table 5. CNOT₁₃, CNOT₃₁ pulse parameter.

Gate	${\mathit{f}}_1$ [GHz]	${\mathit{f}}_2$ [GHz]	${\mathit{T}}_{\mathit{S}}$ [ns]	${\mathit{T}}_{\mathit{X}}$ [ns]	${\mathbf{\Omega }}_{\mathit{S}}$	${\mathbf{\Omega }}_{\mathit{X}}$	$\mathit{\rho }$	${\mathit{\gamma }}_1$	${\mathit{\gamma }}_2$
${\mathrm{CNOT}}_{13}$	4.67259	4.91339	210	10	0.085	0.02	0.17	0	0.75398
${\mathrm{CNOT}}_{31}$	4.91369	4.67259	430	20	0.09	0.0227	0.1	0	−1.13097

.

However, the ${\mathrm{CNOT}}_{31}$ gate exhibited a trend where fidelity failed to improve despite the application of ideal Hadamard gates and subsequent pulse optimization. Consequently, we configured the ${\mathrm{CNOT}}_{31}$ gate using a direct forward-drive pulse sequence rather than the reverse-wrapping method, as detailed in Table 5.

This observation suggests that increasing the qubit-to-coupler ratio narrows the frequency gaps between qubits, exacerbating frequency crowding. These results underscore the critical importance of frequency allocation strategies in large-scale systems, highlighting the need for sophisticated frequency-placement and dynamic tuning techniques in future research.

4.3. Analysis of Gate Fidelity and Success Probability

The final unitary operator is implemented by sequentially applying the virtual-Z (VZ) gates immediately following the primary pulse operations.

Table 6. Apply correcting VZ gate.

Gate	${\mathit{\theta }}_0$	${\mathit{\theta }}_1$	${\mathit{\theta }}_2$	${\mathit{\theta }}_3$	Gate	${\mathit{\theta }}_0$	${\mathit{\theta }}_1$	${\mathit{\theta }}_2$	${\mathit{\theta }}_3$
${\mathrm{CNOT}}_{01}$	−0.5966	−0.0314	0	0.3142	${\mathrm{CNOT}}_{10}$	0.0942	−0.0314	0	0
${\mathrm{CNOT}}_{02}$	0.4712	0	0	0	${\mathrm{CNOT}}_{20}$	0	0.0628	0	0
${\mathrm{CNOT}}_{03}$	−0.2512	0	0	0.3142	${\mathrm{CNOT}}_{30}$	0.0314	0.0314	0.0314	0.0628
${\mathrm{CNOT}}_{12}$	0.1884	1.4727	0.2826	0.2198	${\mathrm{CNOT}}_{21}$	0.0314	0.1256	−0.0314	−0.0314
${\mathrm{CNOT}}_{13}$	0.0942	0.942	0	−0.3768	${\mathrm{CNOT}}_{31}$	0.0942	0	0.0314	0.0942
${\mathrm{CNOT}}_{23}$	0.1727	0.0942	−0.0628	0.1099	${\mathrm{CNOT}}_{32}$	0.1256	0.0942	0.157	0.1256

lists the precise rotation angles ($\theta$) applied to each individual qubit to calibrate the pulse-induced unitary operator.

To evaluate the performance of the implemented gates, we performed unitary operations on prepared computational basis states and calculated the resulting success probabilities. As shown in

Table 7. Lattice-Transmon system results.

Gate	Max Success Probability	Average Fidelity	Gate	Max Success Probability	Average Fidelity
${\mathrm{CNOT}}_{01}$	0.9912	0.98265	${\mathrm{CNOT}}_{10}$	0.9878	0.98152
${\mathrm{CNOT}}_{02}$	0.9991	0.95864	${\mathrm{CNOT}}_{20}$	0.9657	0.94496
${\mathrm{CNOT}}_{03}$	0.9985	0.97833	${\mathrm{CNOT}}_{30}$	0.9688	0.94266
${\mathrm{CNOT}}_{12}$	0.9982	0.91509	${\mathrm{CNOT}}_{21}$	0.9081	0.89566
${\mathrm{CNOT}}_{13}$	0.9949	0.83292	${\mathrm{CNOT}}_{31}$	0.9644	0.85239
${\mathrm{CNOT}}_{23}$	0.9745	0.91256	${\mathrm{CNOT}}_{32}$	0.9956	0.95000

, the forward CNOT gates (${\mathrm{CNOT}}_{01}$ through ${\mathrm{CNOT}}_{23}$) exhibit high success probabilities exceeding 0.98. High success rates were maintained across varying coupling strengths, albeit with longer gate durations, suggesting that the proposed lattice-patch architecture possesses high robustness against physical parameter fluctuations.

The final average gate fidelities, calculated after virtual-Z phase corrections, are summarized in Table 7. The calibrated unitary gates achieved the target performance metrics across all connectivity directions. These numerical results demonstrate that our 1-coupler-4-qubit architecture can serve as an efficient building block for next-generation, large-scale quantum processors.

Here, the maximum success probability serves as a metric to evaluate how closely the implemented operator aligns with the ideal gate, evaluated across all computational basis states of the four-qubit system. Because this specific indicator is calculated by discarding phase errors, it inherently yields relatively higher numerical values. In contrast, the average gate fidelity represents the comprehensive mean value obtained only after executing the additional virtual-Z (VZ) gate calibrations. Crucially, because it encapsulates both state-flip errors and phase errors simultaneously, the average fidelity more accurately and rigorously reflects the actual gate performance from a physical hardware perspective.

Particularly, in superconducting qubit platforms, VZ gates are executed entirely through digital frame rotations without applying any physical microwave drive pulses; thus, they introduce zero additional gate overhead or physical error in actual experimental implementations. Furthermore, the auxiliary calibration pulses employed for the reverse CNOT gate implementations were fully integrated into the time-evolution calculations of the total system Hamiltonian during the numerical simulations. Consequently, any potential physical errors induced by these secondary drives, such as parasitic crosstalk or leakage to higher energy levels, are strictly and comprehensively reflected within the final average fidelity values.

4.4. Leakage Error and Error Budget

Because the current numerical simulations explicitly incorporate energy levels higher than the computational basis, the formulated system Hamiltonian naturally includes these higher-dimensional terms. Consequently, by applying the implemented unitary operator to the computational basis, we can quantitatively assess the leakage error. This can be formalized by projecting the final state ${\rho }_{\mathrm{final}}$, which evolves from an arbitrary initial computational state $|\psi \rangle$ under the action of ${\widehat{\mathcal{U}}}_{\mathrm{final}}$, onto the respective Pauli operators ${\sigma }_x$, ${\sigma }_y$, and ${\sigma }_z$:

$$x=\mathrm{Tr}\left({\sigma }_x{\rho }_{\mathrm{final}}\right),y=\mathrm{Tr}\left({\sigma }_y{\rho }_{\mathrm{final}}\right),z=\mathrm{Tr}\left({\sigma }_z{\rho }_{\mathrm{final}}\right).$$

(16)

where the density matrix ${\rho }_{\mathrm{final}}$ is defined as follows:

$${\rho }_{\mathrm{final}}={\widehat{\mathcal{U}}}_{\mathrm{final}}|\psi \rangle \langle \psi |{\widehat{\mathcal{U}}}_{\mathrm{final}}^{†}.$$

(17)

Through this procedure, the final state evolving within the higher-dimensional Hilbert space can be effectively projected back onto the two-dimensional computational subspace. Using these calculated expectation values $(x,y,z)$, the leakage out of the computational subspace can be quantitatively measured. The resulting leakage error ${\epsilon }_L$ is expressed by the following equation:

$${\epsilon }_L=1-(x^2+y^2+z^2).$$

(18)

The calculated average leakage errors for the implemented CNOT gates across the various computational basis states are summarized in the following

Table 8. Final CNOT gate leakage error.

	CNOT01	CNOT02	CNOT03	CNOT10	CNOT12	CNOT13	CNOT20	CNOT21	CNOT23
${\epsilon }_L$	0.0251	0.0252	0.0238	0.0242	0.0239	0.0228	0.0244	0.0252	0.0218

.

Furthermore, the physical simulations of the proposed hardware were conducted utilizing a three-level energy system ($|0\rangle ,|1\rangle ,|2\rangle$). This explicitly incorporates states higher than the standard two-level computational basis commonly defined in quantum computing architectures. Crucially, as the simulated energy dimension per qubit increases, the overall computational complexity of the proposed system scales as $\mathcal{O}\left(N^5\right)$. Although the first excited state outside the computational basis (the second energy level) represents the primary channel where leakage directly occurs, higher-order leakage into even more elevated states remains a physical possibility. To investigate this phenomenon quantitatively, we tracked the specific leakage errors distributed across the higher energy levels 2, 3, and 4 during the execution of the ${\mathrm{CNOT}}_{01}$ gate, the results of which are compiled in the following

Table 9. Energy Level Error Budget.

Energy Level	2	3	4
${\epsilon }_L$	0.9941	0.9748	0.9739

.

On the other hand, the Hadamard gates ($X_{\pi /2}$ gate) implemented for the current reverse CNOT gates were initially modeled as ideal gates. However, in actual hardware implementations, while single-qubit gates generally exhibit lower error rates compared to CNOT gates, even a minor error rate can significantly impact the overall system performance, making a detailed analysis of single-qubit gates highly critical. These single-qubit gates can be implemented using the same Gaussian pulses previously employed for the CNOT gate configuration, and the pulse parameters optimized for executing the Hadamard gates on each qubit are summarized in

Table 10. Pulse parameters for the implemented $X_{\pi /2}$ gates.

Gate	f [GHz]	T [ns]	$\mathbf{\Omega }$	$\mathit{\gamma }$	Fidelity
$X_{\pi /2,0}$	5.10260	10	0.023	1.5707	0.998
$X_{\pi /2,1}$	4.91339	10	0.0185	0.3141	0.999
$X_{\pi /2,2}$	4.71721	10	0.024	−0.6283	0.993
$X_{\pi /2,3}$	4.47259	10	0.025	0.3141	0.993

.

Accounting for these single-qubit operations, the effective fidelity of the reverse CNOT gate incorporating the physical Hadamard transformations is calculated as:

$$F_{\mathrm{eff}}\approx F_{ij}\times (1-{\epsilon }_i)(1-{\epsilon }_j)$$

(19)

where $F_{ij}$ denotes the maximum success probability achieved by the reverse CNOT gate under idealized conditions, and ${\epsilon }_i=1-F_{X_{\pi /2,i}}$ represents the error rate of each respective Hadamard gate. Based on this formulation, the total effective fidelities for the reverse CNOT gates are evaluated as follows in

Table 11. Effective fidelities of the reverse CNOT gates.

Gate	${\mathbf{CNOT}}_{10}$	${\mathbf{CNOT}}_{20}$	${\mathbf{CNOT}}_{21}$	${\mathbf{CNOT}}_{30}$	${\mathbf{CNOT}}_{32}$
$F_{\mathrm{eff}}$	0.9848	0.9364	0.9008	0.9600	0.9817

.

These comprehensive results demonstrate the profound impact of single-qubit errors originating from actual physical pulse sequences compared to idealized 2-qubit operations that only incorporate virtual phase corrections. Consequently, this analysis highlights that evaluating the full operation sequence is indispensable, thereby providing a rigorous and clear benchmark for assessing the practical lower bound of physical hardware performance.

4.5. Scalability and Structural Advantages

From a hardware implementation perspective, the 1:4 lattice-patch structure drastically reduces the total coupler count compared to conventional 1:1 or 1:2 coupling schemes, thereby mitigating control-line complexity. Furthermore, each patch functions as a unit cell [plaquette] for the surface code, and periodic tiling of these patches can form a global square lattice. This structural advantage addresses frequency crowding in fixed-frequency systems while providing an efficient physical-layer foundation for fault-tolerant quantum computing.

5. Discussion

The single-coupler 4-qubit lattice-patch architecture proposed in this study presents a novel framework for overcoming the physical and structural constraints inherent in conventional fixed-frequency transmon systems. Our numerical simulations demonstrate the successful implementation of six independent forward CNOT gates mediated by a single LC resonator, with the flexibility to extend these operations to bidirectional gates. Despite the increased qubit density, the system achieves an average gate fidelity ($F_{\mathrm{avg}}$) exceeding 0.98—comparable to the performance of previous 1:3 qubit configurations. These results confirm that individual qubit controllability and coherence can be maintained within a more complex, multi-qubit coupled environment.

The primary advantage of this architecture lies in its structural scalability. Conventional 1:2 coupling schemes, such as Google’s Sycamore, face an inevitable and prohibitive surge in wiring complexity and coupler count as the system scales. Furthermore, previously studied 1:3 coupling systems suffer from structural limitations that require complex encoding or significant SWAP gate overhead to implement the surface code.

In contrast, our 4-qubit unit functions as a fundamental unit cell (plaquette), enabling direct topological mapping onto the surface code without additional compilation overhead. This offers a significant paradigm shift for hardware design in fault-tolerant quantum computing. However, challenges such as frequency crowding and residual interactions intensify as qubit density increases.

The primary objective of the pulse configuration implemented in the current hardware model is to validate the structural feasibility and foundational viability of the proposed architecture using a simple CR pulse scheme. As cross-resonance pulse engineering matures, advanced variations—such as echoed CR or active-cancellation CR techniques—have emerged. Incorporating these sophisticated protocols into future physical simulations is highly expected to yield substantial further improvements in gate fidelities.

Furthermore, it should be noted that the current numerical simulations were evaluated within a closed quantum system that excludes dissipative environments and auxiliary coupling elements. In practical hardware implementations, shifting away from a closed-system idealization to account for open-system dynamics—such as energy relaxation ($T_1$), dephasing ($T_2$) mediated by the Lindblad master equation, and interactions with readout Purcell filters—is of paramount importance. Nevertheless, the core focus of this study remains squarely on the architectural paradigm of coupling four or more fixed-frequency qubits to a single, localized fixed-frequency coupler. Introducing these additional physical components will naturally alter the overall system Hamiltonian and consequently perturb the pulse parameters, which will necessitate subsequent parameter recalibration in future engineering stages.

The relatively low fidelities (ranging from 0.83 to 0.91) observed in certain gate directions in Table 7 stem from frequency crowding and residual crosstalk. These phenomena are inherently induced by the tight structural layout where four multi-level qubits are densely coupled within a narrow bandwidth spanning $\left[4.67–5.03\right]\mathrm{GHz}$ via a single fixed mediator. Crucially, rather than arbitrarily tuning or individually optimizing the hardware specifications to favor specific gate directions, this numerical simulation strictly applied a single, uncompromised set of global hardware parameters to validate all twelve bidirectional CNOT gates simultaneously. Consequently, the physical control limits became apparent along certain vulnerable gate paths depending on the localized frequency detunings and coupling strengths ($G_i$).

While the resulting non-uniformity highlights the intrinsic trade-offs embedded in fixed-frequency architectures, it does not imply an absolute or permanent performance ceiling for the proposed topology. In physical device fabrication and blueprint design phases, these bottlenecks can be effectively mitigated by meticulously engineering the native qubit-to-coupler frequency allocations, optimizing inter-qubit detunings, and adopting advanced pulse-shaping technologies. If adjacent qubit frequency crowding can be systematically suppressed in subsequent works, the currently degraded gate fidelities can comfortably surpass the rigorous fault-tolerant thresholds required for surface-code error correction.

In conclusion, the core scholarly value of this study transcends the mere localized fine-tuning of specific gate parameters; rather, it represents the first successful proof-of-concept demonstrating that a 1-coupler-4-qubit architecture can be numerically controlled and physically realized under strict quantum dynamics. By introducing a novel hardware topology that fundamentally circumvents the exponential surge in coupler count and control-line complexity—traditionally the most critical bottleneck in scaling large-scale quantum processors—this architecture holds distinct academic significance. It establishes a primary foundational milestone toward achieving scalable quantum error correction (QEC) schemes. Therefore, granular optimization of hardware specifications, quantitative sensitivity analyses against parameter fluctuations, and advanced pulse engineering will serve as clear and highly valuable directions for follow-up research built upon the architectural foundation established in this work.

6. Conclusions

In this work, we proposed and validated a lattice-patch architecture designed to resolve the scalability bottlenecks of fixed-frequency transmon processors. Our primary findings are summarized as follows:

First, we achieved structural optimization by coupling four fixed-frequency qubits to a single central resonator. This configuration reduces hardware complexity and enhances control-line efficiency. Second, we demonstrated high-fidelity gate operations; by utilizing optimized CR pulses and DRAG techniques, we achieved CNOT gate fidelities exceeding 0.98 and confirmed the robust implementation of bidirectional gates. Finally, we verified that this structure allows for direct correspondence with surface-code lattice units, significantly reducing the computational overhead typically associated with logical qubit implementation.

In conclusion, the lattice-patch architecture offers a promising path toward scalable superconducting quantum processors and is expected to serve as a standard building block for future large-scale, fault-tolerant systems. Future research will explore the integration of active coupling control [tunable couplers] to shorten gate durations and further enhance the system’s robustness against external noise.