The Effect of Trap Design on the Scalability of Trapped-Ion Quantum Technologies

Abstract

To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.

1. Introduction

The electronic and motional states of ions trapped in an electromagnetic field can be used to store and process quantum information, enabling a host of quantum technologies, such as atomic clocks [1], quantum sensors [2], and analog [3] and digital [4,5] quantum computers. Qubits encoded in the electronic states of trapped ions enjoy fast and high-fidelity state preparation and measurement (SPAM) [6], along with single- and two-qubit operations using optical [7,8,9] or electronic [10,11,12] gates. Traditionally, trapped-ion experiments use a macroscopic linear Paul trap with a deep and harmonic trapping potential [13]. However, the bulky structure limits the number of qubits in a given volume.

Two-dimensional surface-electrode traps have emerged as an alternative to the traditional 3D Paul trap [14] and are currently the prevailing choice for trapped-ion experiments due to their versatility and scalability. Indeed, surface traps underpin the most advanced trapped-ion quantum information processors to date, enabling high-fidelity quantum computing demonstrations with tens of qubits [15,16,17,18,19,20], including initial demonstrations towards fault-tolerant encoding [20] and operation [21]. Still, the field remains far from a utility-scale trapped-ion quantum processor. Though many factors hinder the scalability of trapped-ion quantum technologies, here, we focus on the effect of trap electrode geometry.

The geometry of the radio-frequency (rf) electrodes fixes the shape and relative strength of the trapping potential. Here, we are interested in understanding how trap geometry affects the trap frequency for a given set of drive parameters. While there are entangling gate schemes that do not use the motional modes [22,23], or that can be run arbitrarily fast [24,25], many platforms currently rely on gates with a speed limit set by the radial trap frequency [26]. Moreover, a higher trap frequency will reduce gate errors due to electric field noise [27]. The requirement to trap many ions in potentials with high radial trap frequencies suggests that power dissipation may become a problem if not considered during trap optimization. Finally, any scalable trap geometry must be reproducible in an industrial setting and provide enough optical access for the necessary control beams.

With these constraints in mind, we consider three distinct trap geometries for their suitability for scaling trapped-ion quantum systems. First, we consider a surface trap (Figure 1a) with a representative electrode geometry [14]. Second, we consider a miniature version of a linear Paul trap (Figure 1c), or “cross-rf” trap. Finally, we introduce a simpler multi-wafer trap design (Figure 1b), which consists of the same surface trap but with an added ground plane above the electrodes. We do not fully optimize the trap geometries, but rather explore the effect of wafer separation on the trapping field for the two multi-wafer designs. We restrict our discussion to the scaling of the radial trapping potential, as this is completely defined during trap fabrication. In contrast, the axial trapping field is set by the voltages applied to the dc electrodes. Thus, in the following, we focus on understanding the scaling of trapping parameters to guide future work in trap optimization for particular experimental design constraints.

We calculate the expected pseudopotential, find the trapping height, and evaluate the three designs through three figures of merit: harmonicity k (Section 2.3), trap depth D (Section 2.4), and radial trapping frequency ${\omega }_{\mathrm{rad}}$ (Section 2.5). We use these figures of merit to compare the expected performance and power dissipation of the three designs within a set of reasonable experimental assumptions (Section 3). Finally, we discuss optical access and fabrication techniques (Section 4).

2. Field Characterization

2.1. Calculation of Trapping Potential

The radial quadrupole electric potential due to an rf drive with amplitude $V_{\mathrm{rf}}$, frequency ${\Omega }_{\mathrm{rf}}$, and phase $\varphi$ is [28]:

$${\Phi }_{\mathrm{rf}}(x,y,t)={\displaystyle \frac{V_{\mathrm{rf}}}{2r_0^2}}(k_{\mathrm{x}}{x}^2+k_{\mathrm{y}}{y}^2)cos({\Omega }_{\mathrm{rf}}t+\varphi )$$

(1)

where $r_0$ is the distance from the ion to the closest electrode surface and $k_{\mathrm{x}}$ and $k_{\mathrm{y}}$ are coefficients that satisfy the Laplace equation ${\nabla }^2{\Phi }_{\mathrm{rf}}=0$.

Rapid oscillations of the rf field create a ponderomotive potential, or “pseudopotential”, proportional to the square of this field’s amplitude, ${\left|E\left(\mathbf{r}\right)\right|}^2$. For a particle with charge e and mass m in an oscillating electric field, the pseudopotential is [29]:

$$\psi \left(\mathbf{r}\right)={\displaystyle \frac{e}{4m{\Omega }_{\mathrm{rf}}^2}}|\nabla {\Phi }_{\mathrm{rf}}{\left(\mathbf{r}\right)|}^2={\displaystyle \frac{e}{4m{\Omega }_{\mathrm{rf}}^2}}{\left|E\left(\mathbf{r}\right)\right|}^2$$

(2)

In the following, we consider the pseudopotential for ⁴⁰Ca⁺, although our results are directly applicable to any ion species. We assume a source with voltage $V_{\mathrm{rf}}=10$ V and frequency ${\Omega }_{\mathrm{rf}}=2\pi \times 20$ MHz, unless otherwise specified.

We simulate the electric field due to each rf electrode to obtain the pseudopotential for a given geometry. The simulations are conducted in COMSOL Multiphysics 6.2 using the boundary element (BE) method. In the BE method, the boundary constraints defined by the electrodes are used to define the integral form of Maxwell’s equations for the structure of interest. These equations are then solved for points on a pre-defined mesh. This method has been used in several previous studies and has been validated against experiments [30,31,32,33,34,35]. The full simulation volume is $8\times 8\times 5$ mm³. This area is meshed using a built-in adaptive meshing routine within COMSOL with an element size of 100 µm. A finer meshing volume of $0.6\times 0.6\times 0.5$ mm³ is centered at the expected rf-null point. The same COMSOL adaptive meshing algorithm is used with an element size of 1–10 µm, giving a minimum mesh size of 1 µm at the ion location. This is performed to ensure that our mesh size is smaller than our fabrication precision, and thus, errors due to the finite meshing should be smaller than errors due to fabrication imperfections. With these simulation parameters, each simulation takes approximately half an hour to run.

We construct the pseudopotential from the simulated electric field following Equation (2). Figure 1d–f shows the xy cross-section of the pseudopotential of the three trap designs, reported in meV. For the two multi-wafer trap designs, we pick the same wafer separation, $h=200$ µm, to illustrate the qualitative differences in the pseudopotential for the different trap designs. The ion is trapped where the pseudopotential is zero, as indicated. Figure 1g,h show the pseudopotential along the y coordinate at $x=0$ for surface and gnd-surface geometries, while Figure 1i is the pseudopotential running from rf electrode to rf electrode crossing through the rf-null point. The red arrow indicates the trap depth, and the dashed line illustrates the saddle point (see Section 2.4).

In the following sections, the trapping performance of each trap geometry is investigated for varying wafer separation, h. For the cross-rf trap, the horizontal electrode–electrode spacing is also kept at h to maintain the symmetry of the potential (see Figure 1c). All other parameters are kept constant.

2.2. Ion Height

The ion height, d, is the vertical distance between the rf-null point and the bottom wafer, as indicated in Figure 1d–f. The position of the rf null does not directly impact the scalability of a trapped-ion system, but it does influence the achievable trap frequency (Section 2.5) and heating rate (Section 3) and has implications for optical addressing [36,37]. We note that d can also be controlled by changing the lateral geometry of the electrodes [38], but here, we focus on the relationship between trapping height d and wafer separation h for the multi-wafer traps.

Figure 2 presents the ion height d derived from simulations as a function of h, the distance between wafers. The trap height for the surface trap is shown in red for reference. Our uncertainty for the estimation of d is defined by our mesh size of 1 µm. This uncertainty could be reduced with interpolation or a finer mesh. For the cross-rf trap, the rf-null point is always directly between the two wafers, or $d=h/2$. As expected, as h increases, the rf-null point of the gnd-surface trap approaches that of the bare surface trap.

2.3. Harmonicity

Harmonicity, k, measures how closely the trapping field resembles an ideal harmonic potential. From Equation (1), $k_{\mathrm{x}}=-k_{\mathrm{y}}=1$ for a perfect quadrupole field. Deviations from this can cause gate errors due to increased cross-Kerr nonlinearity [39,40], and the entangling gate control must be optimized with the particular anharmonicity in mind [41]. Anharmonicity also reduces the achievable trap frequency for a given drive voltage in two ways. First, it reduces the amount of applied voltage converted to a quadratic trapping potential as described below (Equation (3)). It also reduces the experimentally accessible extent of the stability region of the dynamic trapping field [42,43,44]. A full multipole expansion of the field can provide further insight into the expected ion dynamics and provide corrections to the trap frequencies [45], but here, we only consider harmonicity.

We determine radial harmonicity by performing a quadratic fit of the electric potential along the two radial axes. For the multi-wafer traps, we investigate how harmonicity changes with wafer separation h. The cross-rf trap is symmetric, and we conducted the fit along the diagonal axis as described in Figure 1i. For the surface and gnd-surface traps, $k_y<k_x$ due to the asymmetry of the y axis. Figure 3 shows $k_y$ as a function of h for the two multi-wafer traps. The error bars derived from the quadratic fit are smaller than the symbol size and are all less than 0.001.

The surface trap design (red line) suffers from large anharmonicity due to the highly non-symmetric geometry. The gnd-surface trap exhibits a modest increase in harmonicity in comparison to the surface trap for most heights. However, it suffers a steep decrease in k when h is less than the rf-rf electrode distance. For large separation, the configuration effectively transitions into a surface-electrode trap. In contrast, the harmonicity of the cross-rf trap is inversely proportional to h and is generally high due to its symmetric geometry.

2.4. Trap Depth

The trap depth D is the minimum potential energy difference between the rf-null point and the saddle point, which is indicated by a red arrow in Figure 1g–i. D defines the maximum kinetic energy an ion can have without escaping confinement. Low trap depth can hinder ion loading and increase ion loss due to background gas collisions [32,46]. As above, we only consider the contribution from the rf trapping fields and do not consider the effect of the dc potential, as that is determined post-fabrication by the voltages applied to the dc electrodes.

Figure 4 shows the relationship between D and h for the multi-wafer traps. The trap depth for the surface trap design is shown in red. We use the same trapping parameters as in previous sections, ${\Omega }_{\mathrm{rf}}=2\pi \times 20$ MHz and $V_{\mathrm{rf}}=10$ V. For both multi-wafer traps, D generally increases with decreasing h. Though again, the field of the gnd-surface trap is distorted when the wafer height is less than the rf-rf electrode separation, reducing D.

2.5. Trap Frequency

Finally, we discuss the radial trap frequency. The radial oscillation frequency of a charged particle with charge e and mass m with a drive voltage $V_{\mathrm{rf}}$ and drive frequency ${\Omega }_{\mathrm{rf}}$ is [28]:

$${\omega }_{\mathrm{rad}}={\displaystyle \frac{V_{\mathrm{rf}}ke}{\sqrt{2}m{\Omega }_{\mathrm{rf}}{r}_0^2}}={\displaystyle \frac{q{\Omega }_{\mathrm{rf}}}{2\sqrt{2}}}$$

(3)

where q on the left-hand side of Equation (3) is the instability parameter.

$$q={\displaystyle \frac{2e{V}_{\mathrm{rf}}k}{m{\Omega }_{\mathrm{rf}}^2{r}_0^2}}=2\sqrt{2}{\displaystyle \frac{{\omega }_{\mathrm{rad}}}{{\Omega }_{\mathrm{rf}}}}$$

(4)

In an ideal harmonic system, the first stability region of the Matthieu equation spans the entire range $0\le q\le 1$ [28,43], and ideally, ${\Omega }_{\mathrm{rf}}$ and $V_{\mathrm{rf}}$ would be chosen such that $q\simeq 1$ increases the trap frequency achievable for a given voltage, as illustrated in Figure 5b. However, for surface traps, the trap frequency is generally kept at $\omega <0.1{\Omega }_{\mathrm{rf}}$ or $q<0.3$ [13,47] to achieve stable trapping. This deviation from the ideal case is attributed to the anharmonicity of the trap, which is not captured by the idealized potential derived from the Matthieu Equation [48]. Thus, the achievable radial trap frequency depends on the trap geometry through both the harmonicity k and the trapping position $r_0$.

The cross-rf wafer trap is symmetric along the principal radial axes indicated in Figure 1i. For the surface and the gnd-surface wafer trap, we simply focus on the radial frequency ${\omega }_y$ to be consistent with the axis we have chosen for harmonicity and trap depth. Figure 5a shows the radial frequency of a ⁴⁰Ca⁺ ion in the three trap designs for ${\Omega }_{\mathrm{rf}}=2\pi \times 20$ MHz and $V_{\mathrm{rf}}=10$ V. As above, we vary the wafer separation h for the two multi-wafer trap designs. The trap frequency for the surface trap under the same drive parameters is shown in red as a reference.

The trap frequency generally increases with smaller h, although the trap frequency reduces when h is less than the electrode–electrode separation for the gnd-surface trap.

Figure 5b shows the relationship between ${\Omega }_{\mathrm{rf}}$, the q-parameter, and the trapping frequency for the three trap designs for $V_{\mathrm{rf}}=10$ V. For the two multi-wafer traps, $h=105$ µm, as marked in Figure 5a. At the same q, the multi-wafer traps produce a higher radial trap frequency, with the cross-rf trap having a slightly better performance. High trap depth [43] and high harmonicity [49] allow for certain traps to operate at much higher instability q values, increasing the attainable radial trap frequency [49].

Trap frequency can be increased by increasing the trap drive amplitude,$V_{\mathrm{rf}}$. However, the maximum voltage is set by the breakdown field of the dielectric used to separate neighboring electrodes [50]. Moreover, for large-scale trapped-ion systems, increased rf amplitude and frequency will increase power dissipation, which can be limiting, especially for systems working at cryogenic temperatures. This is discussed further in Section 3. Therefore, it is important to understand the maximum trap frequency that can be achieved given a set drive amplitude.

Figure 5c shows the maximum achievable frequency for $V_{\mathrm{rf}}=10$ V) as a function of h. To find this, we pick an operating q parameter for each trap by scaling a typical working parameter for surface traps ($q=0.250$) with the harmonicity of each design, e.g., $q=q_{\mathrm{st}}{\displaystyle \frac{k}{k_{\mathrm{st}}}}$ [28]. This results in $q=0.905$ for the cross-rf trap, matching recent results in a miniature 3D-printed trap [49], and a more modest $q=0.333$ for the gnd-surface trap. These q parameters are indicated in Figure 5b. This q parameter then defines the drive frequency for a given $V_{\mathrm{rf}}$ with Equation (4). These parameters then give the maximum achievable trap frequency for a given rf drive amplitude from Equation (3). As seen in Figure 5c, the multi-wafer traps show a gain in maximum trap frequency due to the increased harmonicity. In particular, the cross-rf trap provides a more than 10x improvement over the surface trap design considered here (6.12 MHz vs. 1.00 MHz). For the gnd-surface trap in particular, we find that the maximum trap frequency (2.84 MHz) is achieved when the wafer height equals the rf-rf electrode separation. These results can be used to focus design optimization for other electrode geometries and highlight the importance of the harmonicity of the trapping potential.

3. Expected Experimental Performance

In this section, we explore the expected experimental performance of the three trap designs. We use the field-dependent parameters presented above to understand the expected heating rate and how the necessary voltage and expected power dissipation scale with the target trap frequency.

3.1. Heating Rate

Noisy electric fields at frequencies near the secular trap frequency $\omega$ cause a time-dependent increase in the thermal population of an ion’s motional modes [51,52], causing entangling gate errors [53]. The origin of electric field noise is not well understood [27], but the average increase in phonon number, or the heating rate $\dot{\overline{n}}$, generally fits the following trend [27]:

$$\dot{\overline{n}}\propto {\omega }^{-2}{r}_0^{-4}$$

(5)

Unfortunately, $\omega$ and $r_0$ generally counteract each other (Equation (3)). The expected heating rates of the three trap designs, normalized to the expected heating rate of a surface trap (Equation (5)), are shown in Figure 6. This indicates that with all other factors kept equal, the cross-rf trap would exhibit nearly an order-of-magnitude-lower heating rate than the other two designs, and the gnd-surface trap can still achieve approximately half the heating rate of a surface trap. This may be negated by the introduction of a greater surface area, depending on the origin of the noise. Still, it is clear that multi-wafer traps can help reduce the heating rate under the assumption that the electric field noise is not affected by trap geometry.

3.2. Achieving a Target Trap Frequency

Here, we compare the performance of the surface trap design and the two multi-wafer traps when $h=105$ µm (as highlighted in Figure 5). This wafer height provides both high harmonicity and large trap frequency for both multi-wafer trap designs. The rf-null position d and harmonicity k are set by the trap geometry. We use the operating q parameters found in Section 2.5 and reported in

Table 1. Experimental values of the investigated FoMs and the heating and power scaling for each trap geometry. The errors on the reported values are discussed in the text and are limited by the resolution of the simulations, which limits the estimation of d.

Geometry	d [µm]	k	q	${\mathit{\omega }}_{\mathbf{rad}}/2\mathit{\pi }$ $\left[\mathbf{MHz}\right]$	${\mathit{V}}_{\mathbf{rf}}$ [kV]	${\mathbf{\Omega }}_{\mathbf{rf}}/2\mathit{\pi }$ $\left[\mathbf{MHz}\right]$	$\overline{\mathit{P}}$ (norm)
Surface	90	0.210	0.250	10	15	110	1
gnd-surface	46	0.280	0.333	10	4.0	85	$4.0\times {10}^{-2}$
Cross-rf	60	0.697	0.905	10	0.42	31	$6.1\times {10}^{-5}$

. Here, we use the values of d, k, and q to calculate the minimum trap voltage and drive frequency needed to achieve a target trap frequency of ${\omega }_{\mathrm{rad}}=2\pi \times 10$ MHz using Equations (3) and (4). This is summarized in Table 1. This example underlines, again, the importance of harmonicity—as in Figure 5c, a higher harmonicity reduces the necessary source voltage and frequency by increasing the workable q parameter and by improving the conversion efficiency between applied voltage and trap frequency. Thus, the multi-wafer traps require significantly reduced drive voltage and frequency with respect to the surface trap geometry. This will be particularly important if trapped-ion systems are to increase the number of ions per chip.

The drive parameters define the expected power dissipation for each of the trap geometries. Power dissipation can occur due to electrical and dielectric losses. Here, we focus on electrical power consumption as dielectric loss varies with material. COMSOL simulations show that the capacitance values of the rf electrodes in the three trap designs are all around 0.1 pF ($C_{\mathrm{surface}}=91.0$ fF, $C_{\mathrm{gnd}-\mathrm{surface}}=115.0$ fF, and $C_{\mathrm{cross}-\mathrm{rf}}=89.5$ fF). In practice, the capacitance will likely be dominated by the trace layout and external wiring with standard values in the order of 10 pF [14,37,54,55]. Thus, we present the power dissipation normalized to the system capacitance, which scales with the amplitude and frequency of the rf drive [56]:

$$P\propto V_{rf}^2{\Omega }_{rf}^2.$$

(6)

As seen in Table 1, the cross-rf (gnd-surface) trap will need orders-of-magnitude less power with respect to a surface trap due to reduced drive amplitude and frequency. This further highlights the need for high harmonicity to enable operation at $q\sim 1$.

4. Practicality

4.1. Fabrication

Section 2 and Section 3 suggest that the two multi-wafer designs present a path forward to achieving significantly reduced power dissipation for a given target trap frequency, a key to increasing the number of trap sites in a trapped-ion quantum computer. However, multi-wafer traps complicate fabrication and reduce the overall optical access. Here, we consider how the increased complexity of the multi-wafer traps will affect the overall reliability and performance.

Surface-electrode ion traps can be fabricated using traditional clean-room microfabrication techniques [14]. Simple planar geometries are straightforward to make on a variety of different substrates, and advanced fabrication techniques have been leveraged to create complex surface electrode traps offering specific functionalities such as high optical access through the trap [37] and junctions between trapping zones [34,57,58,59].

Multi-wafer traps are more difficult to fabricate than surface traps, but traps with geometries similar to the cross-rf trap discussed herein have been demonstrated with a variety of different techniques. Solutions include manual wafer stacking [60,61] and clean-room-based MEMS techniques for monolithic ion traps [62]. Wafer alignment can be quite precise, with reported angular, lateral, and wafer separation errors of less than 0.05°, 2 µm, and 5 µm, respectively, for a 2 cm × 2 cm chip [61].

The gnd-surface trap is significantly simpler than the cross-rf multi-wafer trap and can take advantage of all the microfabrication techniques developed for high-performance surface traps. The ground plane is unpatterned, and thus, lateral misalignment has no impact on the trap parameters. Errors in the trap height will change the ion position but will not distort the potential. Thus, though it provides more modest gains with respect to a surface trap, the simplicity may improve repeatability and reliability.

4.2. Optical Access

The main focus of this manuscript has been the effect of trap geometry on the radial trapping potential. However, a truly scalable architecture must also include optical control, including fast control of the spectral, temporal, and spatial degrees of freedom across the visible spectrum [63]. In general, current experiments take advantage of the large optical access of well-engineered surface traps to excite ions with lasers parallel to the trap and collect fluorescence from the top hemisphere, which has unimpeded optical access. However, as architectures begin to tile trapping regions in a 2D plane [18,64], this will not be sufficient. Instead, the optical control beams will likely need to come from below or above the trap. In surface traps, this has been achieved by integrating slits under the ions [37] or with integrated photonics and grating couplers [36,65,66,67].

In previous demonstrations of multi-wafer traps similar to our cross-rf design, optical access was achieved through the opening between the rf and ground electrodes, both perpendicular and parallel to the wafers [60,61,62,68,69,70]. In this case, the electrode–electrode separation will define the achievable numerical aperture for both excitation and fluorescence collection. The gnd-surface trap design does not naturally provide the same separation between electrodes for optical access. However, we propose two possible solutions. First, the ground plane could be made from a transparent wafer (e.g., borosilicate) with a grounded coating of a transparent conductive material such as indium–tin oxide. This would enable all of the benefits laid out in the previous sections without a large change to the optical access with respect to the surface trap. However, there will likely still be small reflections from each interface, and care will have to be taken to reduce the effect of this stray light. Second, openings in the ground plane could be engineered for collection and excitation, similar to previous high-optical-access surface traps [37]. While this would change the electrical trap properties, the co-optimization of electronic and optical properties is an opportunity for future work.

5. Conclusions and Outlook

The geometry of an ion trap’s electrodes defines the shape of the radial trapping potential, which, in turn, affects the operation of the trapped-ion device. Here, we present a study of how overall design choices affect the experimental performance and, ultimately, the scalability of a trapped-ion device. We compare three generic trap geometries: (1) a surface trap, (2) a miniaturized 3D linear Paul trap, and (3) a multi-wafer design comprising a surface trap with the same dimensions as in (1) but with a ground plane above. We do not perform a complete optimization of any of the three geometries but rather consider how the wafer separation affects the trapping parameters and scalability.

We find that the two multi-wafer trap designs provide improved harmonicity, trap depth, and trap frequency. In particular, we find that the improved harmonicity in the multi-wafer traps is particularly important for increasing the maximum trap frequency as it increases the experimentally achievable stability parameter [28]. This is particularly evident when considering the maximum achievable trap frequency for a given rf drive voltage or, conversely, the expected power dissipation for a target trap frequency. In both cases, the cross-rf trap provides an orders-of-magnitude improvement over a surface trap design, and the gnd-surface trap provides a more modest, but still significant, improvement. While it does not provide the same confinement as a miniaturized 3D linear Paul trap, the gnd-surface trap presents a promising balance between improved confinement and manufacturability, making it a viable candidate for scalable trapped-ion quantum technologies. Future work should be conducted to co-optimize the electrodes with the necessary optical access for qubit control and measurement. As the demand for quantum technologies grows, optimizing ion trap architectures will be essential for the realization of practical, large-scale quantum processors.