# Electronic Implementation of a Deterministic Small-World Network: Synchronization and Communication

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## Abstract

**:**

## 1. Introduction

## 2. Brief Review on Synchronization of Complex Networks

#### 2.1. Synchronization of Complex Network

#### 2.2. Synchronization Conditions

**Theorem**

**1**

## 3. Generator Algorithm of DSWN

## 4. Synchronization of a DSWN with Chaotic Chua’s Circuits as Node

#### 4.1. Chaotic Chua’s Circuit

#### 4.2. Synchronization of 24 Chaotic Chua’s Circuits in a DSWN

#### Numerical Simulations of DSWN with 24 Chaotic Chua’s Circuits

## 5. Analog Synchronization of Six Chua’s Circuits in a DSWN

#### 5.1. Experimental Application for analog Encryption in a DSWN

#### 5.2. Experimental Application for Bit Encryption in a DSWN

## 6. Digital Synchronization and Communication of a DSWN Implemented in FPGA

#### 6.1. Uncoupled Nodes

#### 6.2. Coupled Nodes

#### 6.3. Digital Application in Communications Using FPGA in a DSWN

## 7. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 2.**Synchronization error dynamics ${x}_{11}-{x}_{i1}$, ${x}_{12}-{x}_{i2}$, ${x}_{13}-{x}_{i3}$, $i=1,2,\dots ,24$ of the chaotic Chua’s circuits with $c=30$, different colors are used for the sole purpose of differentiating the error synchronization signals.

**Figure 9.**(

**a**) Phase portrait of states ${x}_{11}$ versus ${x}_{i1}$, (

**b**) phase portrait of states ${x}_{12}$ versus ${x}_{i2}$ for 6 chaotic Chua’s circuits.

**Figure 10.**(

**a**) Electrical diagram to generate a ${Z}_{d}$ cryptogram and send it from node $Tx$ ($N4$), (

**b**) electrical diagram to recover the message $\overline{m}$ in the node $Rx$ ($N6$).

**Figure 11.**(

**a**) Cryptogram in the frequency domain ${Z}_{d}={x}_{41}+m$, (

**b**) original message m (green line) in $N4$ and decrypted message $\overline{m}$ (purple line) in node $N6$.

**Figure 13.**(

**a**) Transmission of encrypted digital data using a DSWN: clock (yellow line), data (green line), and synchrony error (purple line); (

**b**) chaotic dynamics of the states ${x}_{11}$ and ${x}_{51}$ when $Tx$ sends a 1 binary from $N1$ to $N5$.

**Figure 15.**Schematic diagram to implement the processor Nios II fast version within FPGA Cyclone-IV U1 and the pins distribution to set the SPI protocol.

**Figure 16.**Comparison of the phase planes of the discretized network (36) and (37) and the average states of the network (48) for $k=0$: (

**a**) ${x}_{11\left(k\right)}$ vs. ${x}_{1prom\left(k\right)}$, (

**b**) ${x}_{12\left(k\right)}$ vs. ${x}_{2prom\left(k\right)}$, (

**c**) ${x}_{13\left(k\right)}$ vs. ${x}_{3prom\left(k\right)}$, (

**d**) ${x}_{1prom\left(k\right)}$ vs. ${x}_{2prom\left(k\right)}$, (

**e**) ${x}_{1prom\left(k\right)}$ vs. ${x}_{3prom\left(k\right)}$, and (

**f**) ${x}_{2prom\left(k\right)}$ vs ${x}_{3prom\left(k\right)}$.

**Figure 18.**Comparison of the phase planes of system (36) and (37) and the average states of the network (48) using $k=10$: (

**a**) ${x}_{11\left(k\right)}$ vs. ${x}_{1prom\left(k\right)}$, (

**b**) ${x}_{12\left(k\right)}$ vs. ${x}_{2prom\left(k\right)}$, (

**c**) ${x}_{13\left(k\right)}$ vs. ${x}_{3prom\left(k\right)}$, (

**d**) ${x}_{1prom\left(k\right)}$ vs. ${x}_{2prom\left(k\right)}$, (

**e**) ${x}_{1prom\left(k\right)}$ vs. ${x}_{3prom\left(k\right)}$, and (

**f**) ${x}_{2prom\left(k\right)}$ vs. ${x}_{3prom\left(k\right)}$.

**Figure 19.**Yellow line represents chaotic carrier ${x}_{41}$ in the node $ND4$, blue line represents cryptogram $Z={x}_{41}+{m}_{p}\left(t\right)$, and the white line represents the message recovered $\widehat{m}=Z-{x}_{61}$ in the node $ND6$.

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**MDPI and ACS Style**

Reyes-De la Cruz, D.; Méndez-Ramírez, R.; Arellano-Delgado, A.; Cruz-Hernández, C.
Electronic Implementation of a Deterministic Small-World Network: Synchronization and Communication. *Entropy* **2023**, *25*, 709.
https://doi.org/10.3390/e25050709

**AMA Style**

Reyes-De la Cruz D, Méndez-Ramírez R, Arellano-Delgado A, Cruz-Hernández C.
Electronic Implementation of a Deterministic Small-World Network: Synchronization and Communication. *Entropy*. 2023; 25(5):709.
https://doi.org/10.3390/e25050709

**Chicago/Turabian Style**

Reyes-De la Cruz, Daniel, Rodrigo Méndez-Ramírez, Adrian Arellano-Delgado, and César Cruz-Hernández.
2023. "Electronic Implementation of a Deterministic Small-World Network: Synchronization and Communication" *Entropy* 25, no. 5: 709.
https://doi.org/10.3390/e25050709