Electronic Implementation of a Deterministic Small-World Network: Synchronization and Communication

In this paper, synchronization and encrypted communication transmissions of analog and digital messages in a deterministic small-world network (DSWN) are presented. In the first instance, we use a network with 3 coupled nodes in a nearest-neighbor (NN) topology, then the amount of nodes is increased until reaching a DSWN with 24 nodes. The synchronization and encrypted communication transmissions using a DSWN are presented experimentally by using Chua’s chaotic circuit as node, in both analog and digital electronic implementations, where for the continuous version (CV) we use operational amplifiers (OA), and in the discretized version (DV) we use Euler’s numerical algorithm implemented in an embedded system by using an Altera/Intel FPGA and external digital-to-analog converters.


Introduction
Many real-life phenomena, such as biological networks, electrical networks, social networks, etc., are modeled as complex dynamical networks that follow certain general and robust patterns, for example, a large number of interconnections among the nodes that integrate the networks. In some cases, the nodes work as team to achieve objectives that would be difficult to reach for a single node. The nodes that integrate these types of networks are modeled as dynamic systems by non-linear differential equations, linear piece-wise, or chaotic maps, and the interactions among the nodes present instantaneous behaviors or with time delays. The synchronization state can converge to a periodic or chaotic trajectories which depend on the initial conditions and/or the parameter values, where in some cases multi-stability can occur.
Recent studies have attempted modeling the behaviors of a particular type of networks, referred to as small-world (SW) networks, with Watts and Strogatz being pioneers in the study of these type of networks [1]. A model of an SW network starts with a NN topology network, and subsequently, based on a probability p (represented in the interval 0 ≤ p ≤ 1), connections are added in the original NN network to obtain an SW network. An SW network presents two main characteristics: a high clustering coefficient and a low average path length. The current literature reports many papers related to SW networks, for example, see [2][3][4][5][6][7].
Furthermore, Comellas et al. in [8] present a deterministic SW model to streamline the flow of information in wireless communication networks. Comellas and Sampels present a deterministic SW network as an alternative to stochastic models in order to calculate relevant parameters of the SW network by using a simplest method [9]. Zhang and Rong [10] present a deterministic model created by edge iterations. In 2010, Zhang et al. published a deterministic model with different weights connections in order to improve the performance in the transmission of packets in communication networks, see [11]. Given the random nature of small-world stochastic networks, they have the disadvantage that the resulting complex network topology is unknown when the number of nodes or connections are varied. For this reason, the DSWN presents an advantageous alternative over the stochastic models, since they allow us a direct calculation of the relevant parameters of the network, for example, average degree, grade distribution, clustering coefficient, average path length, and diameter of the network. On the other hand, the synchronization of complex systems has been studied in regular, irregular, and random networks, see [12][13][14][15]; therefore, this study seeks to achieve synchronization in DSWNs.
This work is organized as follows: In Section 2, a brief review on synchronization of complex networks is presented. Section 3 describes the used algorithm to generate a DSWN. In Section 4, synchronization of a DSWN network using Chua's chaotic circuit as node is presented. Section 5 describes the experimental synchronization and communication of a DSWN by using six Chua's circuits as nodes, where the electronic representation in its CV is implemented using operational amplifiers (OA) in order to develop private communications. Section 6 describes the experimental synchronization and communication of a DSWN by using six Chua's circuits as nodes, where its DV is obtained using Euler's numerical algorithm, and a digital communication and its implementation are conducted by using an FPGA as the embedded system. Finally, in Section 7 a conclusion is presented.

Synchronization of Complex Network
We consider a complex network composed of N identical nodes, linearly and diffusively coupled through the first state of each node. In this network, each node constitutes a n-dimensional dynamical system, described as follows: where x i = (x i1 , x i2 , . . . , x in ) T ∈ R n are the state variables of the node i, u i = (u i1 , 0, . . . , 0) T ∈ R n is the input signal of the node i, and is defined by the constant c > 0 represents the coupling strength of the complex network and Γ ∈ R n×n is a constant 0 − 1 matrix linking coupled state variables. For simplicity, we assume that Γ = diag(r 1 , r 2 , . . . , r n ) is a diagonal matrix with r i = 1 for a particular i and r j = 0 for j = i, this means that two coupled nodes are linked through their i − th state variables, whereas A = a ij ∈ R N×N is the coupling matrix, which represents the coupling topology of the complex network. If there is a connection between node i and node j, then a ij = 1; otherwise a ij = 0 for i = j. The diagonal elements of coupling matrix A are defined as If the degree of node i is d i , then d i = −a ii , i = 1, 2, . . . , N. Now, suppose that the complex network (1) and (2) is connected without isolated clusters. Then, A is a symmetric irreducible matrix. In this case, it can be shown that zero is an eigenvalue of A with multiplicity 1 and all the other eigenvalues of A are strictly negative [16,17].
Synchronization states of nodes in complex systems can be characterized by the nonzero eigenvalues of A. The complex network (1) and (2) is said to achieve (asymptotically) synchronization if [17] x 1 The diffusive coupling condition (3) guarantees that the synchronization state is a solution, s(t) ∈ R n , of an isolated node, that iṡ where s(t) can be an equilibrium point, a periodic orbit, or a chaotic attractor. Thus, stability of the synchronization state, of complex network (1) and (2) is determined by the dynamics of an isolated node, the coupling strength c, the inner linking matrix Γ, and the coupling matrix A.
The dynamics of an isolated node are determined byd, which is a positive constant, such that zero is an exponentially stable point, the n-dimensional isolated system is determined by Note that system (7) corresponds to the mathematical model of an isolated node with state feedback −dz 1 .

Synchronization Conditions
The following theorem gives the conditions to achieve synchronization of the network (1) and (2) as is established in (4).
Theorem 1 ([16,17]). Consider the dynamical network (1) and (2). Let be the eigenvalues of a coupling matrix A. Suppose that there exists an n × n, D > 0, and two constantsd < 0 and τ > 0, such that for all d ≤d, where I n ∈ R n×n is an unit matrix. If, moreover, then the synchronization state (6) of dynamical network (1) and (2) is exponentially stable.
Since λ 2 < 0 andd < 0, inequality (10) is equivalent to Therefore, the synchronizability of (1) and (2) with respect to a specific coupling topology can be characterized by the second-largest eigenvalue of A.

Generator Algorithm of DSWN
In this work, we use the algorithm introduced by Zhongzhi Zhang et al. in 2006, see [10]. A network is denoted as N(l) after the evolution of l iterations. In this algorithm, the network grows through an iterative procedure. The algorithm is as follows: for l = 0 the initial network N(0) is a triangle that contains three coupled nodes in an NN topology, For l = 1, the network N(l) is obtained from N(l − 1) by adding a new node for each connection created in the step l − 1 and connecting it to the nearest nodes. The algorithm can be summarized as follows: in each step iteration, for each edge that exists in the network, a new node is added and connected to its two nearest neighbors, see details in [10].
Furthermore, according to [10], the total number of nodes N T (l) for each iteration l is as follows: where N T (0) = 3. With respect to the number of edges N e (l) added to each iteration, we have the following where N e (0) = 3. Taking into consideration (12) and (13), the average node degree k of the network for each iteration l is as follows: Generally, SW networks can be identified by three main properties: (i) the average path length does not increase logarithmically with the size of the network or with the increase in the number of nodes, but it grows or decreases as the number of nodes varies; (ii) the average degree of nodes of the network is small, and (iii) the network has a high clustering coefficient.

Chaotic Chua's Circuit
In this section, we describe the chaotic Chua's circuit that we use as node to construct the DSWNs, see [18]. The Chua's circuit consists of four linear elements (a resistor R, an inductor L, and two capacitors C1 and C2) and a non-linear element, which is described in [19]. In order to simulate the behavior of the Chua's circuit in a computer, we used the normalized version described below, see details in [20].

Synchronization of 24 Chaotic Chua's Circuits in a DSWN
Now, we present the synchronization of a DSWN for an iteration l = 3, which is formed by N = 24 chaotic Chua's circuits. The second eigenvalue λ 2 = −0.5501 of the network N(3) is used and the minimum coupling strength (obtained from (11)) to synchronize the network is obtained as follows:

Numerical Simulations of DSWN with 24 Chaotic Chua's Circuits
For the numerical simulations with N = 24 chaotic Chua's circuits, the values of initial conditions in the numerical simulations are chosen as follows: Figure 2 shows the synchronization error dynamics where we can see that the synchronization state for all nodes in the DSWN is convergent.
. . , 24 of the chaotic Chua's circuits with c = 30, different colors are used for the sole purpose of differentiating the error synchronization signals.

Analog Synchronization of Six Chua's Circuits in a DSWN
This section presents an experimental implementation by using OA and analog components for a potential application with electrical circuits in private communications, by way of illustration we implemented a DSWN for l = 1 conformed by the following: where the inputs signals u i , i = 1, 2, . . . , 6 are as follows:

Experimental Application for analog Encryption in a DSWN
This section presents the chaotic encryption and transmission of information using a DSWN with six Chua's circuits, the encryption is achieved using the network of N(1) previously synchronized. Once the network is synchronized, encrypted analog messages can be transmitted (Tx) from any node in the network and can be received (Rx) and decrypted in any other node that integrates the network. By way of illustration, the following example is presented: the message m = sin(2π f t), with f = 1 khz, is encrypted in the node N4 configured as Tx, and it is recovered in the node N6 configured as Rx. The communication scheme consists of adding the chaotic dynamics of the x 41 state to the message m, therefore the resulting cryptogram is Z d = x 41 + m, see Figure 10a, then, the Rx node N6 uses the chaotic dynamics of the x 61 state to recover the encrypted message, which results in the recovered messagem = Z d − x 61 , see Figure 10b. In Figure 11a, the cryptogram Z d = x 41 + m is presented in the frequency domain, whereas Figure 11b shows the original message m = sin(2π f t) (green line) and the decrypted messagem = Z d − x 61 (purple line). From Figure 11a, we can establish that the signal m = sin(2π f t) is hidden in the chaotic carrier.

Experimental Application for Bit Encryption in a DSWN
In this section, we conducted the encryption of a digitized image using the experimental implementation of the Chua's circuit. Figure 12 shows the electronic circuit for the encryption process by varying the resistance R7 using a microcontroller microchip P16F84A, where we chose node N1 as a Tx. The binary information of the scanned image was taken from [20]. Only unidirectional bits can be sent in this application, this is because the information flows from the Tx node N1 to the Rx nodes N i , i = 2, . . . , 6, where this is achieved by adding the electronic circuit of Figure 12 in the node that is selected as the Tx; the Rx nodes remain without modifications. Figure 13a shows the message to be sent in green color (3 bytes) and the synchronization error between nodes N1 and N5 in (purple line), where a 1 binary represents synchrony between systems and a 0 binary represents no synchronization. In the synchrony error (purple signal), there are quite a few unwanted peaks due to the use of a mechanical relay. The synchrony error signal can be recovered using filters to clean the undesired peaks and comparators to restore the information to appropriate voltage levels, in this case the main idea is to show the digital encryption in a general way. Figure 13b shows the chaotic dynamics of the states x 11 and x 51 , it is observed that the dynamics are similar, this is the case when a binary 1 is sent from N1 to N5.

Digital Synchronization and Communication of a DSWN Implemented in FPGA
For the digital implementation, we used Euler's method to approximate the ordinary differential equations (ODEs) and to obtain the model proposed in (21)-(33). Euler's method is used in order to discretize a continuous system that is derived from Taylor's series, when the quadratic and upper order term are truncated [21,22], i.e., if we have the following equationẋ = f(x); then the DV using Euler's method is given by where τ is the step size and k is the iteration number that represents the time in discrete version. Euler's numerical algorithm (35) was considered to obtain the DV of the proposed DSWN (21)-(33) as follows: 12(k) ).
h(x 61(k) ) = m 1 x 61(k) We used the FPGA Cyclone IV DEi-150 Altera-Intel main-board to design the hardware of the embedded system (ES) to implement the DSWN (36)-(47), which has a general purpose input/output (GPIO) that is configured to connect six external digital-to-analog converters (DACs); all the hardware of the ES is described in Figure 14.
To build the algorithm for the digital circuit implementation of the ES, we used the Quartus II version 12 software, which offers the Qsys tool to design the hardware and software, specifically, the 32-bit embedded main processor Nios II (fast version) and the serial-peripheral-interface (SPI) protocol were implemented inside of the FPGA [23,24]. Subsequently, the SPI port was configured to create the links that use the GPIO port from the FPGA De-i150 main board, which is setting in MOSI (master-output-slave-input) mode where the 32-bit micro-controller in the FPGA generates control signals such as chip-select and clock to set the external DACs, MISO (master-input slave-output) mode is not used. Figure 15 shows the schematic circuit of the FPGA to implement the DV of the DSWN (36)-(47). x 11(k) x 12(k) x 13(k) x 1prom(k) x 2prom(k) x 3prom(k) The FPGA Cyclone IV DEi-150 was configured in master mode and the GPIO pins were used to reproduce the SPI control signals: SCK, SDO, and SS1-SS6 for each DAC1-DAC6 as slaves, in order to represent the state variables, respectively. The experimental results showed good performance, presenting a time complexity of t = 664 µs using a clock of 50 MHz. According to the value of the parameter k, we proposed to analyze two cases for systems (36)-(47), these are k = 0, i.e., the nodes are decoupled, and k = 10, i.e., the discretized nodes are coupled.

Uncoupled Nodes
In Figure 16, for k = 0, the phase planes of node ND1 are presented corresponding to the discretized network (36) and (37) versus the representation of the average states of the six nodes of the expression (48).

Coupled Nodes
In Figure 18, the phase planes of the node ND1 corresponding to the system (36) and (37) versus the representation of the average states of the six coupled nodes of the system (48) are presented, where for this case we use k = 10.

Digital Application in Communications Using FPGA in a DSWN
We consider an experimental implementation to encrypt a signal m p (t) using the digital circuit with FPGAs, the signal m p (t) is described as follows: Figure 19 shows the signal of the chaotic carrier x 14 used in the node ND4 to encrypt the signal m p (t). The message m p (t) was received successfully in the node ND6.

Conclusions
We have proposed the synchronization and encrypted communication transmissions of analog and digital messages in a DSWN using Chua's circuit as chaotic node. Analytical, numerical, and experimental studies to confirm the obtained results were conducted. We have presented a numerical method to build DSWNs starting with an iteration l = 0 with N = 3 nodes until iteration l = 3 conformed by N = 24 nodes. We have proposed the electronic implementation of DSWNs for a continuous version and also the digital implementation in a novel digital FPGA-tool Nios II embedded processor. One of the main disadvantages in the presented algorithm is that it does not have flexibility with respect to the modification of the DSWN topologies obtained at each iteration l, i.e., there is a fixed topology obtained at each iteration l. On the other hand, we believe that this work can motivate some possible future works. For example, we can build DSWNs using different chaotic nodes (or even fractional order chaotic nodes). Additionally, outwardly coupled DSWNs can be implemented in order to achieve outer synchronization. Furthermore, different components in the analog and digital implementations (OA or FPGA, respectively) can be applied, among other potential future works.  Institutional Review Board Statement: Not applicable.

Data Availability Statement:
The data used to support the findings of this study are included within the article.