Search Results (3)

In this study, we propose a novel silicon (Si)/silicon carbide (4H–SiC) heterojunction vertical double–diffused MOSFET with an electron tunneling layer (ETL) (HT–VDMOS), which improves the specific on–state resistance (R_ON), and examine the hetero–transfer mechanism by simulation. In this structure, the high channel mobility and high breakdown voltage (BV) are obtained simultaneously with the Si channel and the SiC drift region. The heavy doping ETL on the 4H–SiC side of the heterointerface leads to a low heterointerface resistance (R_H), while the R_H in H–VDMOS is extremely high due to the high heterointerface barrier. The higher carrier concentration of the 4H–SiC surface can significantly reduce the width of the heterointerface barrier, which is demonstrated by the comparison of the conductor energy bands of the proposed HT–VDMOS and the general Si/SiC heterojunction VDMOS (H–VDMOS), and the electron tunneling effect is significantly enhanced, leading to a higher tunneling current. As a result, a significantly improved trade–off between R_ON and BV is achieved. With similar BV values (approximately 1525 V), the R_ON of the HT–VDMOS is 88% and 65.75% lower than that of H–VDMOS and the conventional SiC VDMOS, respectively. Full article

In the traditional SJ MOSFET structure, n/p pillars with the same doping concentrations in the drift region are introduced to decrease the on-resistance. However, SJ MOSFET will turn on the parasitic diodes due to fast reverse recovery, further inducing severe oscillation in the reverse recovery of the device and the corresponding adverse effect on the circuit. In this study, a fast recovery vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars was studied. Unlike other structures, such as the 4H-SiC superjunction UMOSFET with a heterojunction diode or the ultra-low recovery charge cell-distributed Schottky contacts SJ-MOSFET with integrated isolated NMOS, we introduce a Schottky barrier diode (SBD) on the source contact at the top of the n-Si pillar in the SJ-MOSFET to improve the device reverse recovery. The simulation software TCAD Silvaco was utilized to simulate the device properties. Compared with the conventional Si SJ, the proposed Si/SiC SJ with the Schottky barrier diode (SBD) connected demonstrated a lower reverse recovery charge, which was reduced by 90.5%, respectively. The waveform of the reverse recovery current demonstrates that the electrons in the device are withdrawn from SBD during reverse recovery, preventing the opening of the parasitic diode in the SJ MOSFET. Finally, another structure is illustrated to decrease the gate capacitance by introducing a thin p-base layer between the gate metal and N-Si pillar so that it can improve the switching characteristics of devices. The open-loss and off-loss of the improved device were reduced by 33% and 42.3%, respectively. Full article

The vertical heterojunction Ga₂O₃ MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with the p-type oxide as the current-blocking layer (CBL) is investigated for the first time using SILVACO simulation software. The results show that the threshold voltage of the device is easily positive, which means that the device works in the enhancement mode. By adjusting the doping concentration (from 2 × 10¹⁷ cm⁻³ to 2 × 10¹⁸ cm⁻³) and thickness (from 0.4 um to 2 um) of p-SnO CBL, the threshold voltage is around from 2.4 V to 2.8 V and the breakdown voltage of the device can be increased from 361 V to 518 V. Compared with the original homojunction Ga₂O₃ vertical MOSFET with CBL, the p-SnO CBL can greatly improve the performance of the device. Other p-type oxides are also investigated as the CBL and show promising performances. This work has a certain guiding significance for the design of a vertical enhanced current-blocking layer MOSFET device and for the development of a Ga₂O₃ heterojunction power device. Full article