MDPI - Publisher of Open Access Journals

16 pages, 3496 KB

Open AccessArticle

A CMOS Bandgap-Based VCSEL Driver for Temperature-Robust Optical Applications

by Juntong Li and Sung-Min Park

Photonics 2025, 12(9), 902; https://doi.org/10.3390/photonics12090902 - 9 Sep 2025

Viewed by 532

This paper presents a temperature-robust current-mode vertical-cavity surface-emitting laser (VCSEL) driver (or CMVD) fabricated in a standard 180 nm CMOS process. While prior art relies on conventional current-mirror circuits for bias generation, the proposed CMVD integrates a bandgap-based biasing architecture to achieve high thermal stability and process insensitivity. The bandgap core yields a temperature-compensated reference voltage and is then converted into both stable bias and modulation currents through a cascode current-mirror and switching logic. Post-layout simulations of the proposed CMVD show that the reference voltage variation remains within ±2%, and the bias current deviation is under 10% across full PVT conditions. Furthermore, the output current variation is limited to 7.4%, even under the worst-case corners (SS, 125 °C), demonstrating the reliability of the proposed architecture. The implemented chip occupies a compact core area of 0.0623 mm² and consumes an average power of 18 mW from a single 3.3 V supply, suggesting that the bandgap-stabilized CMVD is a promising candidate for compact, power-sensitive optical systems requiring reliable and temperature-stable performance. Full article

(This article belongs to the Special Issue Vertical-Cavity Surface-Emitting Laser Technology: Innovations and Future Trends)

► Show Figures

Figure 1

30 pages, 8304 KB

Open AccessArticle

Design of a Linear Floating Active Resistor with Low Temperature Coefficient

by Yu Liu and Pak Kwong Chan

Chips 2025, 4(2), 18; https://doi.org/10.3390/chips4020018 - 14 Apr 2025

Viewed by 1837

Abstract

This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include low process sensitivity, reduced temperature coefficient, and good linearity. Monte Carlo (MC) simulations are conducted to evaluate the active resistor’s performance under variations in temperature, process, and supply voltage. The proposed design has demonstrated an average resistance process sensitivity of 0.64%, a temperature coefficient (T.C.) of 57 ppm/°C across −25 °C to 85 °C, and a linearity figure of merit (FOM) of 2.4 × 10⁻² V⁻¹ with a resistance close to MΩ level. It can achieve a linear resistance tuning range of 430.5 kΩ to 1.714 MΩ. The typical power consumption of a single active resistor is 0.25 µW at 2.1 V bootstrapped supply voltage through a Dickson charge pump (DCP) circuit using a DC input of 1 V. These results have confirmed that the proposed active resistor can function as a robust and efficient resistor for low-voltage integrated circuits and systems. Full article

(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)

► Show Figures

Figure 1

16 pages, 5014 KB

Open AccessFeature PaperArticle

A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

by Jaehyeon Nam, Youngha Hwang, Junhyung Kim, Jiwoo Kim and Sang-Gyu Park

Electronics 2024, 13(9), 1758; https://doi.org/10.3390/electronics13091758 - 2 May 2024

Cited by 1 | Viewed by 2774

Abstract

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. Full article

(This article belongs to the Special Issue Analog Circuits and Analog Computing)

► Show Figures

Figure 1

16 pages, 2057 KB

Open AccessArticle

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

by Hao Xu, Yunda Liu, Yachi Duan, Tianke Li, Jun Zhang, Zhiqiang Li and Haiying Zhang

Electronics 2024, 13(2), 366; https://doi.org/10.3390/electronics13020366 - 15 Jan 2024

Viewed by 2257

Abstract

Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD). Full article

(This article belongs to the Section Circuit and Signal Processing)

► Show Figures

Figure 1

Search Results (4)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Saved Queries

Search Filter Reset All

Years

Feature Papers

Subjects

Journals

Article Types

Countries / Regions

Search Results (4)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI