Search Results (6)

In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an I_on/I_off ratio of more than seven orders of magnitude, with I_on reaching up to 2.56 × 10⁻⁴ A/μm, I_off as low as 3.99 × 10⁻¹² A/μm, and a threshold voltage reduced to −0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future. Full article

In today’s digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices’ critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device’s electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device. Full article

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices. Full article

In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO₂ interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high. Full article

The combined effect of total ionization dose (TID) and time-dependent dielectric breakdown (TDDB) of partially depleted silicon-on-insulator (PDSOI) NMOSFET is investigated. First, the effect of TDDB on the parameter degradation of the devices was investigated by accelerated stress tests. It is found that TDDB stress leads to a decrease in off-state current, a positive drift in threshold voltage, and a reduction of maximum transconductance. Next, the degradation patterns of TID effect on the devices are obtained. The results show that the parameter degradation due to gamma radiation is opposite to the TDDB stress. Finally, the combined effect of TID and TDDB is investigated. It is found that the drift of the devices’ sensitive parameters due to TDDB stress decreases in a total dose of gamma radiation environment. The TDDB lifetime is shortened, but the pattern of gate current change remains unchanged. The failure mechanism of the gate oxide layer under TDDB stress is not changed after irradiation. Full article

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices. Full article