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Open AccessArticle

Design of Robust Fault-Tolerant Finite-State Machines for Unmanned Aerial Vehicles

by Valery Salauyou

Appl. Sci. 2026, 16(9), 4201; https://doi.org/10.3390/app16094201 - 24 Apr 2026

Cited by 1 | Viewed by 387

Enhancing the robustness and fault tolerance of finite-state machines (FSMs) is crucial for safety-critical systems, such as transportation control systems and medical equipment. This issue becomes particularly important when developing control units for unmanned aerial vehicles (UAVs), which are exposed to external disturbances from electronic warfare (EW) systems. Under such conditions, traditional methods for creating fault-tolerant finite-state machines (FTFSMs), initially designed to address the effects of ionizing radiation that cause rare single-event upsets (SEUs), are often ineffective. This paper proposes a novel method for developing FTFSMs that can withstand multi-bit upsets (MBUs) affecting the FSM’s wires and memory cells due to external disturbances. The FTFSM architecture additionally includes an output register and a concurrent error detection (CED) circuit. When a fault is detected, the FTFSM switches to standby mode. Once the external disturbance ceases, the FTFSM resumes normal operation from the point of interruption without altering the control algorithm. In cases of critical errors, the FSM circuit can be reconfigured via the system processor. Experimental studies have shown that the proposed approach incurs exceptionally low overhead costs. Additionally, the paper presents a technique for calculating the probability of fault detection for FTFSMs implemented in field-programmable gate arrays (FPGAs). Full article

(This article belongs to the Special Issue Robust Fault-Tolerant Controllers for Unmanned Aircraft Vehicles)

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20 pages, 2347 KB

Open AccessArticle

Workload-Dependent Vulnerability of SDRAM Multi-Bit Upsets in a LEON3 Soft-Core Processor

by Afef Kchaou, Sehmi Saad and Hatem Garrab

Electronics 2025, 14(24), 4852; https://doi.org/10.3390/electronics14244852 - 10 Dec 2025

Cited by 3 | Viewed by 854

Abstract

Multi-bit upsets (MBUs) are a growing reliability threat in high-density SDRAM, particularly in radiation-prone embedded systems. This paper presents a large-scale FPGA-based fault injection (FI) study targeting external SDRAM in a cache-enabled LEON3 SPARC V8 processor, with over 300,000 dual-bit MBUs injected across three diverse workloads: Fast Fourier transform (FFT), matrix multiplication (MulMatrix), and advanced encryption standard (AES). Our results reveal a profound dependence of MBU manifestation on application semantics: memory-intensive benchmarks (FFT, MulMatrix) exhibit high fault detectability through data store and access exceptions, while the AES workload demonstrates exceptional intrinsic masking, with the vast majority of MBUs producing no observable effect. These results demonstrate that processor vulnerability to MBUs is not uniform but fundamentally shaped by workload characteristics, including memory access patterns, control flow regularity, and algorithmic redundancy. The study provides a hardware-validated foundation for designing workload-aware fault tolerance strategies in space-grade and safety-critical embedded platforms. Full article

(This article belongs to the Special Issue Data Science in Prognostics and Health Management of Industrial Equipment)

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10 pages, 593 KB

Open AccessArticle

Experimental Study on the Space Electrostatic Discharge Effect and the Single Event Effect of SRAM Devices for Satellites

by Xuan Wang, Rui Chen, Runjie Yuan, Qian Chen, Yanan Liang and Jianwei Han

Appl. Sci. 2022, 12(14), 7129; https://doi.org/10.3390/app12147129 - 14 Jul 2022

Cited by 5 | Viewed by 3461

Abstract

Space Electrostatic Discharge Effect (SESD) and Single Event Effect (SEE) are two major space environmental factors that cause spacecraft failure. Previous studies have established that both can lead to soft errors such as upset of memory cells. An ESD generator and a pulsed laser experimental facility were used to test a low-power asynchronous timing monolithic SRAM. The characteristics of soft error number, single/multi-bit upsets, and supply current values were compared for similarities and differences. The test revealed that SEE-induced soft errors were mainly single-bit upsets (SBU), whereas SESD-induced soft errors were predominantly multi-bit upsets (MBU). Additionally, when soft errors occur in the circuits, the current of the power supply drops, which enables the device to be evaluated by monitoring the current value. This study provides experimental support for distinguishing device errors caused by these two effects, as well as references for further accurate identification of in-orbit faults and corresponding protection design. Full article

(This article belongs to the Section Aerospace Science and Engineering)

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