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Keywords = low voltage low power (LVLP)

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16 pages, 5582 KiB  
Article
A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications
by Jorge Pérez-Bailón, Belén Calvo and Nicolás Medrano
Electronics 2021, 10(17), 2108; https://doi.org/10.3390/electronics10172108 - 30 Aug 2021
Cited by 12 | Viewed by 7015
Abstract
This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery [...] Read more.
This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off. Full article
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16 pages, 3082 KiB  
Article
Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design
by Amel Garbaya, Mouna Kotti, Mourad Fakhfakh and Esteban Tlelo-Cuautle
J. Low Power Electron. Appl. 2020, 10(2), 20; https://doi.org/10.3390/jlpea10020020 - 16 Jun 2020
Cited by 8 | Viewed by 4052
Abstract
Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used [...] Read more.
Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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