Search Results (6)

Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the grid by using Power Electronics Converters (PEC). A Phase-Locked Loop (PLL) is one of the most popular synchronization techniques used due to its speed and robustness. A growing issue that results in oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude is the DC-offset in the input of the PLL. This study was developed to eliminate the DC-offset in the single-phase grid synchronization using Delay Signal Cancellation (DSC) and a fixed-length Transfer Delay (TD)-based PLL. Then, the small-signal model, stability analysis, and selection of controller gains were discussed. The proposed PLL was simulated using MATLAB/Simulink. Moreover, to evaluate the proposed method, several scenarios were developed in order to compare it with other powerful PLLs in terms of performance indicators such as settling time, frequency, and phase error. As a result, the proposed PLL has the fastest dynamic response, completely rejects the DC-offset effect, and fully synchronizes with the electrical grid. Full article

Today, and especially with the growing interest in distributed renewable energy sources (DRESs), modern electric power systems are becoming more and more complex. In order to increase DRES penetration, grid side converter (GSC) control techniques require appropriate synchronization algorithms that are able to detect the grid voltage status as fast and accurately as possible. The drawbacks of the published synchronization phase-locked loop (PLL) techniques were structured mainly around the slow dynamic responses, the inaccuracy of extracting the fundamental components of the grid voltages when they contain a DC offset, and the worsening of the imbalance rejection ability facing significant frequency changing. This paper proposes a new synchronization PLL technique ensuring efficient and reliable integration of DRESs under normal, abnormal, and harmonically distorted grid conditions. The proposed PLL uses the mixed second- and third-order generalized integrator (MSTOGI) in the prefiltering stage through its adaptability to power quality and numerous grid conditions and its low sensitivity to input DC and inter-harmonics. Moreover, a modified quasi type-1 PLL (MQT1-PLL), which integrates two compensation blocks for phase and amplitude errors, respectively, has been used in the control loop. The discussion of sizing requirements and the effectiveness of the so-called MSTOGI-MQT1-PLL are tested under grid voltage imbalances and distortions and confirmed through simulation results compared to double second-order generalized integrator PLL (DSOGI-PLL), cascaded delayed signal cancellation PLL (CDSC-PLL), and multiple delayed-signal cancellation PLL (MDSC-PLL). Full article

This research presents a secondary control for a grid-supporting microgrid with photovoltaics sources to guarantee grid code compliance and ancillary services. The secondary control accomplishes the fault ride-through, which implements a delayed signal cancellation (DSC) algorithm for negative sequence detection. Without mode switching, the proposed control strategy meets grid code requirements and ensures voltage regulation at the secondary level, which is active and more salient throughout the transient period of host grid disturbances. This control also ensures a constant supply of the microgrid’s sensitive local load while adhering to grid code requirements. Similarly, active power injection into the main grid is limited by progressively altering the MPPT operating point dependent on the depth of voltage sag to optimize reactive power injection to sustain grid voltage sag. The recommended secondary control is triggered by utilizing the DSC process’s detection algorithm to identify the occurrence of a fault in a tiny fraction of a half-cycle in a grid fault. Consequently, while satisfying microgrid load needs, the devised technique guaranteed that increases in DC-link voltage and AC grid current were controlled. MATLAB Simscape ElectricalTM and OPAL-RT Lab are used to do time-domain simulations of the model using the recommended secondary control systems. Full article

With the increasing penetration of renewable energy, a weak grid with declining inertia and distorted voltage conditions becomes a significant problem for wind and solar energy integration. Grid frequency is prone to deviate from its nominal value. Grid voltages become more easily polluted by unbalanced and harmonic components. Grid synchronization technique, as a significant method used in wind and solar energy grid-connected converters, can easily become ineffective. As probably the most widespread grid synchronization technique, phase-locked loop (PLL) is required to detect the grid frequency and phase rapidly and precisely even under such undesired conditions. While the amount of filtering techniques can remove disturbances, they also deteriorate the dynamic performance of PLL, which may not meet the standard requirements of grid codes. The objective of this paper is to propose an effective PLL to tackle this challenge. The proposed PLL is based on quasi-type-1 PLL (QT1-PLL), which provides a good filtering capability by using a moving average filter (MAF). To accelerate the transient behavior when disturbance occurs, a modified delay signal cancellation (DSC) operator is proposed and incorporated into the filtering stage of QT1-PLL. By using modified DSCs and MAFs in a cascaded way, the settling time of the proposed method is reduced to around one cycle of grid fundamental frequency without degrading any disturbance rejection capability. To verify the performance, several test cases, which usually happen in high renewable penetrated power systems, are carried out to demonstrate the effectiveness of the proposed PLL. Full article

The growing level of grid-connected renewable energy sources in the form of microgrids has made it highly imperative for grid-connected microgrids to contribute to the overall system stability. Consequently, secondary services which include the fault ride-through (FRT) capability are expected to be possessed characteristics by inverter-based microgrids. This enhances the stable operation of the main grid and sustained microgrid grid interconnection during grid faults in conformity with the emerging national grid codes. This paper proposes an effective FRT secondary control strategy to coordinate power injection during balanced and unbalanced fault conditions. This complements the primary control to form a two-layer hierarchical control structure in the microgrids. The primary level is comprised of voltage/power and current inner loops fed by a droop control. The droop control coordinates grid power-sharing amongst the voltage source inverters. When a fault occurs, the participating inverters operate to support the grid voltage, by injecting supplementary reactive power based on their droop gains. Similarly, under unbalanced voltage condition due to asymmetrical faults in the grid, the proposed secondary control ensures the positive sequence component compensation and negative and zero sequence components clearance using a delayed signal cancellation (DSC) algorithm and power electronic switched series impedance placed in-between the point of common coupling (PCC) and the main grid. While ensuring that FRT ancillary service is rendered to the main utility, the strategy proposed ensures relatively interrupted quality power is supplied to the microgrid load. Consequently, this strategy ensures the microgrid ride-through the voltage sag and supports the grid utility voltage during the period of the main utility grid fault. Results of the study are presented and discussed. Full article

Synchronous-reference-frame phase-locked loop (SRF-PLL) is widely used in grid synchronization applications. However, under unbalanced, distorted and DC offset mixed grid conditions, its performance tends to worsen. In order to improve the filtering capability of SRF-PLL, a modified three-order generalized integrator (MTOGI) with DC offset rejection capability based on conventional three order generalized integrator (TOGI) and an enhanced delayed signal cancellation (EDSC) are proposed, then dual modified TOGI (DMTOGI) filtering stage is designed and incorporated into the SRF-PLL control loop with EDSC to form a new hybrid filter-based PLL. The proposed PLL can reject the fundamental frequency negative sequence (FFNS) component, DC offset component, and the rest of harmonic components in SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to the EDSC reducing the number of DSC operators. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameter design guidelines are given. Experimental results are included to validate the effectiveness and robustness of the proposed PLL. Full article