Search Results (2)

Enhancing the robustness and fault tolerance of finite-state machines (FSMs) is crucial for safety-critical systems, such as transportation control systems and medical equipment. This issue becomes particularly important when developing control units for unmanned aerial vehicles (UAVs), which are exposed to external disturbances from electronic warfare (EW) systems. Under such conditions, traditional methods for creating fault-tolerant finite-state machines (FTFSMs), initially designed to address the effects of ionizing radiation that cause rare single-event upsets (SEUs), are often ineffective. This paper proposes a novel method for developing FTFSMs that can withstand multi-bit upsets (MBUs) affecting the FSM’s wires and memory cells due to external disturbances. The FTFSM architecture additionally includes an output register and a concurrent error detection (CED) circuit. When a fault is detected, the FTFSM switches to standby mode. Once the external disturbance ceases, the FTFSM resumes normal operation from the point of interruption without altering the control algorithm. In cases of critical errors, the FSM circuit can be reconfigured via the system processor. Experimental studies have shown that the proposed approach incurs exceptionally low overhead costs. Additionally, the paper presents a technique for calculating the probability of fault detection for FTFSMs implemented in field-programmable gate arrays (FPGAs). Full article

Calculations testing can be effectively used in the construction of discrete self-checking devices. Calculations testing is based on the parity and self-duality of the calculated functions. This can be used for modern blocks and nodes of control systems for responsible technological processes. However, its use has a number of features that must be considered when building concurrent error-detection circuits. The authors used methods of discrete mathematics and Boolean algebra as well as technical diagnostics of discrete systems to investigate the problem of ensuring the testability of the parity encoder. Theorems on the testability of convolution functions modulo 2 are proved. Considering these theorems allowed the authors of the article to propose a method for synthesizing CED circuits. This method increases the testability of the encoder for parity. This method is based on the use of two diagnostic signs at once. The first sign is that the code words belong to the parity code. The second is the self-dual control function in the concurrent error-detection circuit. This method is guaranteed to increase the testability of the parity coder compared to using one of the diagnostic signs for calculations testing. Experiments with testing discrete devices have shown the effectiveness of the organization structure of the concurrent error-detection circuit that we developed. The theorems that we proved form the basis of proof of similar provisions for the use of other linear codes in the synthesis of concurrent error-detection circuits. Our proposed solutions with calculations testing based on two diagnostic signs should be used in the synthesis of discrete systems. Discrete systems should be self-checking and have improved testability indicators. Full article