A Method for Synthesizing Self-Checking Discrete Systems with Calculations Testing Based on Parity and Self-Duality of Calculated Functions

Abstract

Calculations testing can be effectively used in the construction of discrete self-checking devices. Calculations testing is based on the parity and self-duality of the calculated functions. This can be used for modern blocks and nodes of control systems for responsible technological processes. However, its use has a number of features that must be considered when building concurrent error-detection circuits. The authors used methods of discrete mathematics and Boolean algebra as well as technical diagnostics of discrete systems to investigate the problem of ensuring the testability of the parity encoder. Theorems on the testability of convolution functions modulo 2 are proved. Considering these theorems allowed the authors of the article to propose a method for synthesizing CED circuits. This method increases the testability of the encoder for parity. This method is based on the use of two diagnostic signs at once. The first sign is that the code words belong to the parity code. The second is the self-dual control function in the concurrent error-detection circuit. This method is guaranteed to increase the testability of the parity coder compared to using one of the diagnostic signs for calculations testing. Experiments with testing discrete devices have shown the effectiveness of the organization structure of the concurrent error-detection circuit that we developed. The theorems that we proved form the basis of proof of similar provisions for the use of other linear codes in the synthesis of concurrent error-detection circuits. Our proposed solutions with calculations testing based on two diagnostic signs should be used in the synthesis of discrete systems. Discrete systems should be self-checking and have improved testability indicators.

1. Introduction

One of the strategies in constructing highly reliable and low-maintenance discrete control systems is to endow their blocks and nodes with the properties of self-checking and self-testing [1,2,3,4]. Such devices are created considering the possibility of constantly checking the correctness of the values of the functions they calculate and, indirectly, considering the absence of faults in the internal structures. The methods of synthesis of self-checking discrete devices are quite well developed [5,6]. They are based on the use of structural, data, and time redundancy methods for hardware and/or software, as well as the use of sabotage protection [7]. Examples of the use of self-checking discrete systems are control complexes of microelectronic and microprocessor systems for railway signaling and interlocking systems [8,9] or on-board control systems in aviation [10,11].

The very property of self-checking in the construction of discrete systems can be implemented at various levels. These levels can be at the microelectronics level. They can also be at the level of individual blocks and nodes and even entire ready-made functional blocks and systems [12,13]. If we talk about individual devices within discrete systems, then self-checking implementations can be built at the component levels. They can be also for the entire device as a whole. For example, if an automatic model of a discrete device is used, the inputs and outputs of the internal memory elements and the output data can be encoded. They can be encoded in it in any way, for example, binary redundant code. This will make it possible to monitor the correctness of calculations testing in the process of performing their functions. This is due to the use of testers or detectors of these codes. Another way to implement a self-checking device with an automatic model of its description is to retrofit the blocks with concurrent error-detection (CED) circuits [14]. These are also synthesized using the properties of any binary redundant codes or special classes of Boolean functions [15]. This makes it possible, without introducing internal redundancy, to ensure calculations testing at the outputs of the state machine during its operation. Both approaches lead to the use of redundancy and sabotage protection methods. In addition, they are associated with an increase in the complexity of the technical implementation of devices. However, the self-checkability of structures comes at a price, affecting the ability to detect faults and errors in calculations in a timely manner.

This article was written by the authors based on the results of research on methods for synthesizing self-checking discrete devices. It is based on the properties of redundant uniform block codes and self-dual Boolean functions. The authors present the results of research on the implementation and functioning of the CED circuit organization structure for discrete devices as described in [16,17,18]. This structure is based on using a parity compression circuit and converting the parity function into a self-dual Boolean function. The original researchers called this method of organizing calculations testing the method of “self-dual parity”. In their article, the authors show the main advantages of this method of CED circuit synthesis. They also note its important disadvantages and propose a new method for CED circuit synthesis—synthesis of a circuit with calculations testing based on two diagnostic signs—addressing the disadvantages of the known method.

2. General Research Approaches and Methodology

Let us imagine a discrete diagnostic object in the form of a device similar to a “black box”. Let us assume that it is impossible to know its structure. But one can only observe the values at its outputs at any given time. The sets of argument values <X> = <x_t x_t−1 … x₂ x₁> are applied to the device inputs. Their total number is 2^t. The values of the Boolean functions f₁(X), f₂(X), …, f_m−1(X), f_m(X) describing its outputs are calculated on each such set. The device’s response to all sets of argument values and generated Boolean vectors <f_m(X) f_m−1(X) … f₂(X) f₁(X)> is known.

Stuck-at faults and errors occur during the operation of the device in question. They lead to distortion of the values of the functions f₁(X), f₂(X), …, f_m−1(X), f_m(X) when input sets of argument values <X> = <x_t x_t−1 … x₂ x₁>. Moreover, the structure of the diagnostic object is checking, or self-testable. This means that for any fault from a given model, there is at least one set <x_t x_t−1 … x₂ x₁> on which the true values of the functions f₁(X), f₂(X), …, f_m−1(X), f_m(X) are distorted. This allows one to detect faults.

We will use time and structural redundancy to detect faults. To do this, all concurrent signals at the inputs and outputs of the device are in the vectors <x_t x_t−1 … x₂ x₁> and <f_m(X) f_m−1(X) … f₂(X) f₁(X)>. We will make them consistent by using the data inversion method [16,17,18]. This requires the installation of a generator G of straight-angle pulses with a duty cycle of 50%. Its output is connected to the first inputs t of two-input addition gates modulo 2 (XOR). In addition, input variables are supplied to the second inputs of these devices. Thus, binary signals 0 and 1 are transformed into pulse sequences 0101…01 and 1010…10. The vectors <x_t x_t−1 … x₂ x₁> begin to be generated as alternating vectors in a pair of a supplied effective vector and a check vector that is orthogonal to it in all variables. In other words, pairs of inverse combinations arrive at the device’s inputs. This property is precisely used to calculations testing.

The well-known [16,17,18] CED circuit structure of the “self-dual parity” uses a circuit for compressing signals from the diagnostic object by parity. It also uses the correction of the resulting value on each set of argument values to a value belonging to some self-dual function. The self-duality check is carried out due to the property of a self-dual function–on inverse sets it takes on opposite values [19]. It is precisely these opposite values that the self-dual checker examines.

We will further explore the features of the functioning of the CED circuit with signal compression by parity and correction of the resulting set to obtain a self-dual function. We will show the advantages and disadvantages of this structure. In addition, we will propose a way to eliminate these disadvantages.

Figure 1 shows a flow chart of the algorithm demonstrating the research plan. The task is divided into five main blocks. The first process implements the task of analyzing the properties of self-dual functions through an analysis of the schematic implementation of the parity coders. Here, the features of linear Boolean functions are analyzed; they are simultaneously self-dual. The second process is aimed at analyzing the causes of the violation of the self-duality property of the signal though analysis using the signal correction method fixed in the CED circuit. Here, it is important to find a pattern in the conditions under which the faults of the encoder elements are masked. The third process is related to the analysis of error detection features during calculations testing. The calculations testing are monitored using parity code and the self-duality of the signal in the CED circuit. It is established how the faults of the parity code encoder are covered. The fourth process demonstrates experimental research using the example of the simplest diagnostic object. It also confirms the theoretical positions formulated by the authors. The fifth process contains conclusions and recommendations on the practical application of the results obtained by the authors.

3. Calculations Testing Based on Self-Duality with Compression of Signals from the Diagnostic Object by Parity

The structure of the CED circuit organization is shown in Figure 2.

The parallel signals from the inputs x₁, x₂, …, x_t−1, x_t in the structure of Figure 2 are converted into pulse sequences. The conversion takes place using a specialized signal-to-pulse sequence converter (SPSC). It includes a cascade of t two-input XOR gates, the first inputs of which are supplied with variables x₁, x₂, …, x_t−1, x_t, and the second with a sequence of pulses a generated by a generator G. This allows the structure to function in a pulsed mode on pairs of $\left(〈x_t x_{t-1} \dots x_2 x_1〉, 〈\overline{x_t} \overline{x_{t-1}} \dots \overline{x_2} \overline{x_1}〉\right)=\left(X, \overline{X}\right)$ vectors.

The signals f₁(X), f₂(X), …, f_m−1(X), f_m(X) calculated on each set of argument values <x_t x_t−1 … x₂ x₁> by block F(X) are fed to the inputs of the parity code encoder G(F). The value of the function is calculated at the outputs of the encoder:

$$g\left(X\right)=f_1\left(X\right)\oplus f_2\left(X\right)\oplus \dots \oplus f_{m-1}\left(X\right)\oplus f_m\left(X\right).$$

(1)

The resulting function generates a parity bit. However, it is not this sign that is tested in the structure but rather the self-duality of the function formed in the CED circuit. The function g(X) itself is not self-dual in the general case. To obtain a self-dual function g^δ(X) from it, the correction circuit (CC) transforms the value of the function g(X) using the following formula:

$$g^{\delta }\left(X\right)=\delta \left(X\right)\oplus g\left(X\right),$$

(2)

where δ(X) is the signal correction function calculated by the Δ(X) block.

Next, the value of the function g^δ(X) is monitored by the self-dual checker using the SDC device [20]. The self-duality checker also works when using a clock signal from the G generator. This structure is shown in Figure 3.

The SDC captures a two-rail signal <01> or <10> at outputs z⁰(X) and z¹(X) when a self-dual signal is received at the inputs. A violation of non-two-rail indicates either internal SDC faults or a violation of the self-duality of the signals at its inputs. The last event occurs when there are faults or errors in calculations at the outputs of the remaining components of the CED circuit (or the diagnostic object). This is how faults in the described structure are fixed.

As noted above, the structure of Figure 2 functions when pairs of inverse combinations are applied to the inputs, which are formed by sets of argument values. The first combination is an effective one. The second is a check one.

The structure shown in Figure 2 has the following key feature: the difference from the traditional CED circuit with calculations testing of parity [21] is the use of Boolean correction signal (BCS) from the parity signal-compressing circuit. It is possible to build a huge number of blocks for calculating the function δ(X) of signal correction. Among them, one can choose the implementation of the Δ(X) block, which will have the lowest value of complexity for the technical implementation. The number of ways to transform a single parity function g(X) into a self-dual function g^δ(X) on 2^t sets of argument values is equal to $2^{2^{t-1}}$. For this number, the simplest option can be selected.

Any errors at the outputs of the diagnostic object are detected with the described method of organizing calculations testing. It distorts only one function value on the supplied pair of argument value sets. If the error appears immediately on two sets of a pair, it is masked and not detected. In [17], it was shown that the use of the structure makes possible a slight deterioration in detection abilities by an average of 1.7%. This value is calculated in comparison with traditional parity testing. The structure is shown in Figure 2. Experiments were conducted with the MCNC Benchmarks test combination circuit. Structural redundancy is reduced by an average of 60% compared to traditional parity testing. This is a significant advantage of using a computational testing structure based on self-duality with the pre-compression of signals from the diagnostic object using the parity function.

4. Testability Theorems of the Compression Circuit in the Structure of the Concurrent Error-Detection Circuit

The structure of the compression circuit uses a device that converts signals f₁(X), f₂(X), …, f_m−1(X), f_m(X) according to Formula (1). This device is synthesized based on a linear Boolean function.

Theorem 1.

A linear Boolean function will be self-dual if it significantly depends on an odd number of arguments.

Proof.

Consider the function (1) for even and odd values of m. At the same time, we will consider the operating mode of the devices, which assumes the submission of a pair of combinations orthogonal to all arguments. We also consider another property of a self-dual function: on opposite sets of argument values, it takes on opposite values. This is follows from the definition of a self-dual function:

$$f\left(x_1,x_2,\dots ,x_t\right)=\overline{f\left(\overline{x_1},\overline{x_2},\dots ,\overline{x_t}\right)}.$$

(3)

Let m be an even number. We denote by 0 ≤ q ≤ m the number of single arguments in the set of argument values. The number of zero arguments in the set will be m − q. If q is even, then the number m − q is also even if m is even. When substituting a set of argument values with an even value q into function (1), we get g(X) = 0. When substituting a set of argument values with an even value m − q into function (1), we get g(X) = 0. The values of the function are equal, which contradicts Formula (3). If q is odd, then the number m − q is also odd for an even value of m. When substituting a set of argument values with an odd value q into function (1), we obtain g(X) = 1. When substituting a set of argument values with an odd value m − q into function (1), we get g(X) = 1. The function values are also equal, which contradicts Formula (3).

Let m be an odd number. If q is even, then the number m − q is non-even for an odd value of m. When substituting a set of argument values with an even value q into function (1), we obtain g(X) = 0. When substituting a set of values of arguments with an odd value m–q into function (1), we obtain g(X) = 1. The values of the function are opposite, which corresponds to Formula (3). If q is odd, then the number m − q is even with an odd value m. When substituting a set of argument values with an odd value q into function (1), we obtain g(X) = 1. When substituting a set of argument values with an even value m − q into function (1), we get g(X) = 0. The values of the function are also opposite, which is consistent with Formula (3).

All cases of ratios of the number of single and zero arguments for even and odd values of m are considered. Function (1) takes opposite values only for odd values of m, which has to be proved. □

The self-dual checker tests the fulfillment of ratio (3) on each pair of sets of argument values. In this case, the vectors <f_m(X) f_m−1(X) … f₂(X) f₁(X)> formed at the outputs of the diagnostic object are not mutually inverse on each such pair.

Following Theorem 2, it is necessary to formulate another fact.

Theorem 2.

If the signal compression circuit faults, the self-duality of the function g(X) will be violated only in cases of distortion of the function g(X). Distortion of a function is based on only one set of argument values from a pair. This is for a fixed method of conversion to the CED circuit in accordance with expression (2).

Proof.

Let us consider function (2) on two inverse sets of argument values in a well-designed CED circuit. Let us denote these sets by X₁ and X₂. Then, in order for g^δ(X) to be self-dual, it is necessary that g^δ(X₁) ≠ g^δ(X₂).

If g(X₁) = g(X₂), then the values of g^δ(X₁) ≠ g^δ(X₂) at δ(X₁) ≠ δ(X₂). In other words, the first case is δ(X₁) = 0, δ(X₂) = 1, and vice versa, δ(X₁) = 1, δ(X₂) = 0.

If g(X₁) ≠ g(X₂), then the values of g^δ(X₁) ≠ g^δ(X₂) at δ(X₁) = δ(X₂). In other words, the first case is δ(X₁) = 0, δ(X₂) = 0, and vice versa, δ(X₁) = 1, δ(X₂) = 1.

A fault of the compression circuit will not be detected in this way if it causes distortion of the function g(X) on both sets X₁ and X₂. In this case, the parity of the values of g(X₁) and g(X₂) will not change, and the values of g^δ(X₁) and g^δ(X₂) will not be equal: g^δ(X₁) ≠ g^δ(X₂)

The value of g^δ(X₁) = g^δ(X₂) if there is parity of the values of the pair g(X₁) and g(X₂), that is, when the true value is distorted on only one set of argument values. In this case, the self-duality of the function g^δ(X) is violated. □

Theorem 2 allows us to prove the following.

Theorem 3.

In the schematic implementation of the function g(X), faults of the XOR gates are not tested. Faults are not tested when calculations testing is based on self-duality. They are connected by paths with an even number of outputs of the diagnostic object, only if the parity of the single values on the first and second sets of argument values is maintained, which are fed to the inputs of the diagnostic object.

Proof.

An error in the structure of the compression circuit is not detected. Only if the values of g(X) on both sets X₁ and X₂ are simultaneously distorted. This follows from Theorem 2. When is this possible?

Let p be an even number. Let us denote the number of single values among p functions on any set of argument values by p₁, and the number of zeros by p₀. For an even value of p, if p₁ is even, then p₀ is even; if p₁ is odd, then p₀ is odd. It follows that the parity of the numbers p₁ and p₀ does not change. They do not change when submitting the first and second sets X₁ and X₂, which will not allow detection of the stuck-at-0, stuck-at-1 faults when distorting the value of function g(X) on both sets X₁ and X₂ or when masking errors on both of these sets.

In the case of a stuck-at-0 fault at the output of the (p − 1)th XOR gate, masking will occur when the number p₁ is even and if p₁ is odd. In the first case, it will not appear. In the second case, it will appear on both sets X₁ and X₂. This will cause guaranteed changes in the values of the function g(X) on both sets X₁ and X₂. In accordance with the conditions of Theorem 2, such an error will not be detected.

In case of a stuck-at-1 fault at the output of the XOR gate, masking will also occur both at an even value of p₁ and at an odd value of p₁. In the second case, it will not appear. In the first case, it will appear on both sets X₁ and X₂. This will cause guaranteed changes in the values of the function g(X) on both sets X₁ and X₂. In accordance with the conditions of Theorem 2, no such error will be detected.

Now let p be an odd number. It follows that if p₁ is even, then p₀ is odd; if p₁ is odd, then p₀ is even. It is clear that when the first and second sets X₁ and X₂ are applied. The parity of the numbers p₁ and p₀ will change. Which will allow detecting the stuck-at-0 or stuck-at-1 faults when distorting the value of the function g(X) only on one of the sets and masking the error on the other.

The theorem has been proved. □

To complete check the encoder for parity, the existence of at least one pair of sets of argument values (X₁, X₂) is required. This becomes clear from Theorem 3 when synthesizing the CED circuit based on the structure shown in Figure 2. When a pair is fed to the inputs of the diagnostic object, it generates XOR function subsectors with two inputs compressed by an odd number with different parity numbers. Otherwise, it will not be possible to test the faults of such gates when the self-duality of calculations testing.

5. Calculations Testing When Compressing Signals from the Diagnostic Object Based on Two Diagnostic Signs

The proof of Theorem 3 implies a method that will allow detecting errors in the outputs of the elements of the exclusive OR. Which are connected by paths to an even number of outputs of the diagnostic object, if they appear at the outputs of these elements. To do this, it is enough to accurately test the values of the function g(X) on each set of argument values. If an error occurs, it is guaranteed to distort the value of the function g(X). The problem of calculations testing on each set, rather than on pairs, can be solved. An additional, subcircuit is being created to check calculations testing by parity. Figure 4 shows the structure of the organization of calculations testing. It is based on two diagnostic signs at once: parity and whether the calculated function belongs to the class of self-dual Boolean functions.

The value of the parity function g(X) is formed at the output of block G(F). The signal output from it and additional calculations testing based on parity, coupled with check of the self-duality of the function g(X), make it possible to ensure a complete check of the encoder G(F). There are two subcircuits for calculations testing in the CED circuit. The first one, already described above, is a circuit for calculations testing based on whether the function g^δ(X) belongs to the class of self-dual Boolean functions. Its outputs are $z_2^0\left(X\right)$ and $z_2^1\left(X\right)$. The parity calculations testing subcircuit uses the same encoder G(F), the control logic block G(X) and the inverter. The control logic block G(X) is also an encoder of the parity code and generates the check bit g(X) directly from the values received at the inputs of the diagnostic object. This bit is inverted to check the two-rail of the signal at the outputs of blocks G(F) and g(X). The check outputs of this subcircuit are the outputs $z_1^0\left(X\right)$ and $z_1^1\left(X\right)$. The check outputs of both check subcircuits are connected to the inputs of a single elementary two-rail checker module (TRC) [22] to obtain a single check output z⁰(X) and z¹(X).

Blocks G(X) and Δ(X) can be implemented together. Which makes it possible to optimize the indicators of structural redundancy of this part of the CED circuit. The output g^δ(X) can be a subcircuit of the block G(X) under the best implementation options. In this case, the indicators of the structural redundancy of the CED circuit will differ very slightly from the indicators of the structural redundancy of the CED circuit (by the magnitude of the complexity of the SDC and TRC implementation). It is implemented in accordance with the class structure of the parity check.

The described arrangement of the CED circuit by two diagnostic signs makes it possible to increase the error detection rates at the outputs of the diagnostic object and each CED circuit block. It is clear that in this case, the advantage of the computational testing structure is lost. It is based solely on the self-duality of the transformed parity function. This is because the block diagram Δ(X) can be very simple. However, at the same time, the error detection rate in the diagnostic object’s output can be improved by testing calculations based on two diagnostic signs.

6. Simulation and Experiment

Using the example of an arbitrary combinational device, we will show how the testability characteristics for the device G(F) change. The calculations testing based on two diagnostic signs at once. Let’s define the device by the truth table (

Table 1. Description of the device with the CED circuit for the example in question.

№	x4	x3	x2	x1	f6(X)	f5(X)	f4(X)	f3(X)	f2(X)	f1(X)	g(X)	δ(X)	gδ(X)
0	0	0	0	0	0	1	0	1	0	1	1	0	1
1	0	0	0	1	1	1	1	0	1	0	0	0	0
2	0	0	1	0	0	0	1	1	0	0	0	0	0
3	0	0	1	1	1	1	0	0	0	1	1	0	1
4	0	1	0	0	0	0	0	0	1	0	1	0	1
5	0	1	0	1	1	1	1	1	0	0	0	1	1
6	0	1	1	0	0	0	1	0	0	1	0	0	0
7	0	1	1	1	1	1	0	0	0	1	1	1	0
8	1	0	0	0	0	1	0	1	0	1	1	0	1
9	1	0	0	1	0	0	1	1	1	0	1	0	1
10	1	0	1	0	0	0	0	0	0	0	0	0	0
11	1	0	1	1	1	1	1	0	0	1	0	0	0
12	1	1	0	0	0	1	0	0	1	0	0	0	0
13	1	1	0	1	0	0	1	0	1	1	1	0	1
14	1	1	1	0	0	0	0	0	0	1	1	0	1
15	1	1	1	1	1	1	0	1	0	1	0	0	0

).

We obtain the values of the functions g(X), g^δ(X) and δ(X) on each set of argument values.

The values of g(X) are obtained uniquely by substituting each set of argument values into the formula m = 6. The values of the function δ(X) are determined from the formula. The difficulties consist only in obtaining the values of the function g^δ(X) on each set of argument values. There are $2^{2^{4-1}}=2^8=256$ variants of self-dual functions from four arguments. We could iterate through each of them and use the one that gives the least complex function δ(X), partially or completely coinciding with the function g(X). However, we will not do this here, but use one of the methods for calculating the functions g^δ(X). For the second half of the values of the arguments with decimal numbers No. 8–No. 15, that is, for x₄ = 1, we define the function g^δ(X) = g(X). For the first half of the values of the arguments with decimal numbers No. 0–No. 7 (that is for x₄ = 0). We define the values of the function g^δ(X) as inverse to the values of the function on the inverse sets of the second half:

$$g^{\delta }\left(X\right)=x_{t}g\left(X\right)\vee \overline{x_t}\overline{g\left(\overline{X}\right)}.$$

(4)

The last three columns of Table 1 contain the values of the functions g(X), g^δ(X), and δ(X).

Further, the structure shown in Figure 4 is not difficult to synthesize from the data obtained in Table 1.

We obtained a functional description of each of the blocks in the system shown in Figure 4 by performing two-level optimization using the Carnot method [23]. Formulas describing blocks F(X), G(X), and Δ(X) are not given here. We will not evaluate any characteristics other than the testability indicators of block G(F), which has a standard implementation.

Based on the obtained description, we synthesize a structure with calculations testing based on two diagnostic signs. We implement the system model (Figure 5) using Multisim 14.0. In it, the SC1 block is an SPSC block. Block SC2 is the diagnostic object F(X). Block SC3 is the device G(X). Block SC4 is the device Δ(X). Block SC5 is the coder G(F), which is the object of the study. The SC6 and SC7 devices are a self-dual checker and a two-rail signal compression module. The structure of the dual signal tester is shown separately in Figure 6, as it is rarely found in publicly available sources.

The structure of the encoder G(F) is disclosed in Figure 7, where the points A–E are displayed. The authors of the article introduced single stuck-at faults.

We obtained time diagrams of how the structure in Figure 5 operates with each of the faults. Exhaustive testing was performed by sending the full set of argument values. They are shown in Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12. The effects were applied using the built-in XWG1 code word generator. An XLA1 logic analyzer is installed to monitor the signals at the check points.

The structure of the coder G(F) is disclosed in Figure 7, where the points A–E are displayed. The authors of the article introduced single stuck-at faults. Each figure shows a diagram on the left with the stuck-at-0 fault, and on the right with the stuck-at-1 fault. The time diagrams from the testers’ outputs are highlighted. The color shows the clock cycles in which the sets of values of the test arguments are supplied. Outputs z0_1 and z1_1 correspond to the outputs $Z_1^0\left(X\right)$ and $Z_1^1\left(X\right)$ of the CED circuit shown in Figure 5. At this checkpoint, the parity calculations are checked. Outputs z0_2 and z1_2 correspond to the outputs of the CED circuit shown in Figure 5. At this check point, the self-duality of the signal g^δ(X) is checked. Outputs z0 and z1 are the check outputs of the CED circuit by two diagnostic signs.

There are very few test values for coder faults among the sets of argument values when checking the self-duality of the g^δ(X) signal. This can be seen in the diagrams. For some of the faults, they do not exist at all due to the peculiarities of the diagnostic object F(X) itself. The testability of the coder is much higher when calculations testing is performed only by parity. The two methods of calculations testing complement each other, as they allow monitoring different diagnostic signs, which increases the performance of the test structure.

Table 2. Characterization of sets of argument values.

Fault	Parity Check		Self-Duality Check		Check by Two Diagnostic Signs
	Test	Non-Test	Test	Non-Test	Test	Non-Test
A_Stuck-at-0	24	8	0	0	24	8
A_Stuck-at-1	8	24	0	0	8	24
B_Stuck-at-0	20	12	8	24	24	8
B_Stuck-at-1	12	20	8	24	16	16
C_Stuck-at-0	14	18	10	22	19	13
C_Stuck-at-1	18	14	10	22	23	9
D_Stuck-at-0	20	12	8	24	24	8
D_Stuck-at-1	12	20	8	24	16	16
E_Stuck-at-0	16	16	12	20	22	10
E_Stuck-at-1	16	16	12	20	22	10

describes the sets of argument values. They are classified into test and non-test ones. Diagrams showing the proportion of test sets (N_T) among those that were submitted to inputs (N) during exhaustive testing are shown in Figure 13. They are used to see the effect of switching to a computational testing method based on two diagnostic signs:

$$\psi ={\displaystyle \frac{N_T}{N}}\cdot 100 \%.$$

(5)

The testability index was ψ < 40%. The calculations testing was carried out solely on the basis of the self-duality of the g^δ(X) signal. This indicator is higher when calculations testing is based on their affiliation to the parity code. In more than half of the discrepancies, ψ < 50%. The indicator for calculations testing based on two diagnostic signs is 60% for more than half of the faults, and 70% for 40% of faults.

A similar trend of increasing testability indicators is observed when considering other diagnostic objects. The check by two diagnostic signs increases the testability indicators for coders in a structure with calculations testing based on self-duality.

7. Discussion

The method of CED circuit synthesis for combinational discrete devices proposed in [16,17,18] is undoubtedly interesting for practical applications. It allows one to significantly reduce the indicators of structural redundancy. Previous studies have shown that at the same time, the values of the indicators of the number of detected faults at the outputs of diagnostic signs decrease slightly. The issues of testability of a compression circuit implemented in the form of a parity coder are not fully discussed anywhere, except for the present work of the authors. However, this is, in principle, a vulnerable place in the CED circuit.

It is possible to increase the testability indicators not only in terms of detecting faults at the outputs of the diagnostic object (which is demonstrated, for example, in [24]). In addition, it is possible to increase the testability of the coder by using additional parity checks. However, this negates the advantages of the approach to using the parity compression circuit itself, which is associated with a potential gain in terms of the complexity of the CED circuit technical implementation. Despite this, a significant effect is created in increasing the testability of the CED circuit.

It is clear that in the best cases it is possible to ensure that the structures of blocks G(X) and Δ(X) do not exceed the complexity of block G(X). This involves the total complexity of the implementation. However, even with a certain excess of this value, the function g^δ(X) can also be made quite simple. This follows from the possibilities of obtaining $2^{2^t-1}$ different self-dual functions from t arguments. Therefore, an optimization problem can be solved by choosing the best conversion method that provides the minimum amount of redundancy. The option of fully implementing the parity function could be interesting. It may also be interesting to use a correction function using a single logical expression or with the partial matching of expressions. This will allow you to implement a check circuit with minimal redundancy. The simplest structure will be one in which only one parity function is implemented. Therefore, in practice, the structure proposed by the authors will often be somewhat more complex than the classical parity check structure. However, a slight complication of the CED circuit makes it possible to increase the testability indicators. The diagrams in Figure 13 show that the effect can be up to 20% compared to the testability indicators for only one of the methods. Such indicators are not achieved using classical approaches related to duplication and parity.

The encoder testability theorems can be effectively used in the analysis of testability indicators for structures synthesized by two diagnostic signs using any linear codes. For example, the results of the work can be developed [25]. At the same time, it is also interesting to extend the results obtained to a class of structures with calculations testing based on the self-quasi-duality of Boolean functions. It is also interesting to extend the results to structures with calculations testing based on both the self-duality and self-quasi-duality of calculated functions [20].

The structure with calculations testing by two diagnostic signs operates in the mode of the pulse signal in a pair of combinations due to the signals generated when applying each set of argument values. The results of the work can be effective in testing “delay faults” [26,27]. When forming tests for such faults, it is necessary to use an installation kit. In addition, it is necessary to transmit the fault to the output, which is provided during the pulsed operation of the structure. However, the issues related to fault testing of the “time delay” type errors require separate consideration, because there are various types of malfunctions of this type. Nevertheless, if a “time delay” fault test is implemented, it will immediately include pairs of combinations $\left(〈x_t x_{t-1} \dots x_2 x_1〉, 〈\overline{x_t} \overline{x_{t-1}} \dots \overline{x_2} \overline{x_1}〉\right)=\left(X, \overline{X}\right)$.

Methods of organizing the CED circuit with calculations testing based on two or more diagnostic signs can be effective in the construction of self-checking discrete devices with respect to various error models.

8. Conclusions

In the course of the research of the authors of this article, it was possible to establish the conditions for ensuring the testability of faults in compression circuits when conducting calculations testing. They are based on the uniqueness of a single function derived from the parity function. It is shown that certain conditions for the testability of the encoder must be met in the implementation described in [16,17,18]. They are not always respected. Calculations testing based on an additional diagnostic sign is an effective way to increase testability indicators. The structure of the CED circuit organization according to two diagnostic signs is proposed in this article. Previously, this structure has not been studied in the scientific literature.

The indicators of the observability of encoder faults can be significantly improved by calculations testing. This is considered from the point of view of parity and from the point of view of self-duality of the calculations testing. The improvement can reach 20% and in some cases even more. This opens up good prospects for the use of CED circuit synthesis methods for two or more diagnostic signs. For example, such methods can be effectively applied in applications where input effects rarely change. This includes, for example, installations for railway signaling and interlocking systems, air defense complexes, control complexes in the nuclear industry, and many others.

An interesting generalization of calculations testing is the testing by groups of outputs with different parity codes [28]. Calculations testing is based on two diagnostic signs, including control by belonging to the parity code and calculations testing of self-duality. In fact, it makes it possible to consider methods for calculations testing based on two or more diagnostic signs using other linear codes. They can be immediately distinguished by codes with a low density of parity checks [29], polynomial codes [30], and many others. If other systematic codes with greater redundancy are used instead of parity codes, the hardware redundancy of the CED circuit will increase. However, at the same time, the error coverage at the outputs of the diagnostic facility will also increase. The specifics of testing encoders as part of systematic code testers will remain. They will be preserved by calculations testing based on two diagnostic signs. The error rates will increase significantly.

In conclusion, it can be stated that the calculations testing based on the parity and self-duality of the check function is an effective method. This method is based on the organization of totally self-checking discrete structures, with high testability of each component.