Search Results (6)

In this paper, we come up with three secure chaos-based stream ciphers, implemented on an FPGA board, for data confidentiality and integrity. To do so, first, we performed the statistical security and hardware metrics of certain discrete chaotic map models, such as the Logistic, Skew-Tent, PWLCM, 3D-Chebyshev map, and 32-bit LFSR, which are the main components of the proposed chaotic generators. Based on the performance analysis collected from the discrete chaotic maps, we then designed, implemented, and analyzed the performance of three proposed robust pseudo-random number generators of chaotic sequences (PRNGs-CS) and their corresponding stream ciphers. The proposed PRNGs-CS are based on the predefined coupling matrix M. The latter achieves a weak mixing of the chaotic maps and a chaotic multiplexing technique or XOR operator for the output function. Therefore, the randomness of the sequences generated is expanded as well as their lengths, and divide-and-conquer attacks on chaotic systems are avoided. In addition, the proposed PRNGs-CS contain polynomial mappings of at least degree 2 or 3 to make algebraic attacks very difficult. Various experimental results obtained and analysis of performance in opposition to different kinds of numerical and cryptographic attacks determine the high level of security and good hardware metrics achieved by the proposed chaos system. The proposed system outperformed the state-of-the-art works in terms of high-security level and a high throughput which can be considered an alternative to the standard methods. Full article

A random number generator (RNG), a cryptographic technology that plays an important role in security and sensor networks, can be designed using a linear feedback shift register (LFSR). This cryptographic transformation is currently done through CMOS. It has been developed by reducing the size of the gate and increasing the degree of integration, but it has reached the limit of integration due to the quantum tunneling phenomenon. Quantum-dot cellular automata (QCA), one of the quantum circuit design technologies to replace this, has superior performance compared to CMOS in most performance areas, such as space, speed, and power. Most of the LFSRs in QCA are designed as shift registers (SR), and most of the SR circuits proposed based on the existing QCA have a planar structure, so the cell area is large and the signal is unstable when a plane intersection is implemented. Therefore, in this paper, we propose a multilayered 2-to-1 QCA multiplexer and a D-latch, and we make blocks based on D-latch and connect these blocks to make SR. In addition, the LFSR structure is designed by adding an XOR operation to it, and we additionally propose an LFSR capable of dual-edge triggering. The proposed structures were completed with a very meticulous design technique to minimize area and latency using cell interaction, and they achieve high performance compared to many existing circuits. For the proposed structures, the cost and energy dissipation are calculated through simulation using QCADesigner and QCADesigner-E, and their efficiency is verified. Full article

We propose an effective, low complexity and multifaceted scheme for peak-to-average power ratio (PAPR) reduction in the orthogonal frequency division multiplexing (OFDM) system for underwater acoustic (UWA) channels. In UWA OFDM systems, PAPR reduction is a challenging task due to low bandwidth availability along with computational and power limitations. The proposed scheme takes advantage of XOR ciphering and generates ciphered Bose–Chaudhuri–Hocquenghem (BCH) codes that have low PAPR. This scheme is based upon an algorithm that computes several keys offline, such that when the BCH codes are XOR-ciphered with these keys, it lowers the PAPR of BCH-encoded signals. The subsequent low PAPR modified BCH codes produced using the chosen keys are used in transmission. This technique is ideal for UWA systems as it does not require additional computational power at the transceiver during live transmission. The advantage of the proposed scheme is threefold. First, it reduces the PAPR; second, since it uses BCH codes, the bit error rate (BER) of the system improves; and third, a level of encryption is introduced via XOR ciphering, enabling secure communication. Simulations were performed in a realistic UWA channel, and the results demonstrated that the proposed scheme could indeed achieve all three objectives with minimum computational power. Full article

Although conventional global navigation satellite systems (GNSS) receivers were originally designed for single signals, studies on multi-signal receiver design have recently been actively conducted to achieve high accuracy, precision, and reliability. However, in order for a multi-signal receiver to support various codes, the receiver should support the generation of individual codes. Therefore, the resulting problem of increased complexity must be solved. This paper proposes a hardware structure for an area-efficient linear feedback shift register (LFSR)-based multi-frequency universal code generator. Whereas the existing universal code generators were configured so that feedback polynomials, output registers, and initial values can be selected by placing read-only memories (ROMs), multiplexers (MUXs), and exclusive ORs (XORs) by register bit, in the case of the proposed universal code generator; the circuit was implemented by applying the hardwiring technique to those register bits that have fixed values. According to the results of field programmable gate array (FPGA) implementation, the proposed LFSR-based universal code generator can improve look up table (LUT) by up to 37% and register by up to 78% when compared to conventional code generators, and LUT by up to 36% when compared to the previous universal code generator. Therefore, the proposed universal code generator is a good candidate for implementing multi-frequency receivers to achieve high precision and high reliability. Full article

Physical unclonable function (PUF) is a primary hardware security primitive that is suitable for lightweight applications. However, it is found to be vulnerable to modeling attacks using machine learning algorithms. In this paper, multiplexer (MUX)-based Multi-PUF (MMPUF) design is proposed to thwart modeling attacks. The proposed design uses a weak PUF to obfuscate the challenge of a strong PUF. A mathematical model of the proposed design is presented and analyzed. The three most widely used modeling attack techniques are used to evaluate the resistance of the proposed design. Experimental results show that the proposed MMPUF design is more resistant to the machine learning attack than the previously proposed XOR-based Multi-PUF (XMPUF) design. For a large sample size, the prediction rate of the proposed MMPUF is less than the conventional Arbiter PUF (APUF). Compared with existing attack-resistant PUF designs, the proposed MMPUF design demonstrates high resistance. To verify the proposed design, a hardware implementation on Xilinx 7 Series FPGAs is presented. The hardware experimental results show that the proposed MMPUF designs present good results of uniqueness and reliability. Full article

In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing technique. This hardware redundancy technique is based on a numerous duplication of faulty components. We analyze the error distributions of the XOR multiplexing unit and the error distributions of multiple stages of the XOR multiplexing system, then compare them to the NAND multiplexing unit and the NAND multiplexing multiple stages system, respectively. The simulation results show that XOR multiplexing is more reliable than NAND multiplexing. Bifurcation theory is used to analyze the fault-tolerant ability of the system and the results show that XOR multiplexing technique has a high fault-tolerant ability. Similarly to the NAND multiplexing technique, this fault-tolerant technique is a potentially effective fault tolerant technique for future nanoelectronics. Full article