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Single-Event Upset Characterization of a Shift Register in 16 nm FinFET Technology

by Federico D’Aniello, Marcello Tettamanti, Syed Adeel Ali Shah, Serena Mattiazzo, Stefano Bonaldo, Valeria Vadalà and Andrea Baschirotto

Electronics 2025, 14(7), 1421; https://doi.org/10.3390/electronics14071421 - 31 Mar 2025

Cited by 1 | Viewed by 1603

Abstract

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸

N i

and ²⁸

S i

, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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24 pages, 18551 KB

Open AccessArticle

A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog Converter Based on a High-Linearity Resistor String Poly-Matrix

by Cristiano Calligaro and Umberto Gatti

Chips 2024, 3(2), 129-152; https://doi.org/10.3390/chips3020006 - 8 May 2024

Cited by 4 | Viewed by 3853

Abstract

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well. Full article

(This article belongs to the Topic Advances in Microelectronics and Semiconductor Engineering)

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