Search Results (2)

This paper presents a subtractive-dither-assisted background calibration technique for a 2 GS/s 12 bit pipelined analog-to-digital converter (ADC). A large 7 bit pseudo-random dither is injected in both the flash and the multiplying digital-to-analog converter (MDAC) to decorrelate the differential nonlinearity (DNL) errors caused by the inherent quantization error nonlinearity, capacitor mismatching, and inter-stage amplifier nonlinearity from the input signal. Designed in a 28 nm CMOS process with a 1 V supply, post-layout simulations demonstrate a 10.2 dB improvement in spurious-free dynamic range (SFDR), from 73.8 dB to 84.4 dB, with dithering enabled under a close-to-Nyquist input frequency of 985 MHz. Although the injected dither cannot be completely removed in the digital domain, the proposed ADC exhibits only a 0.5 dB degradation in signal-to-noise-and-distortion ratio (SNDR) for full-scale input, achieving an SNDR of 62.3 dB and an effective number of bits (ENOB) of 10.1 bits. Dithering also improves static performance, with DNL and INL optimized to +0.54/−0.53 LSBs and +0.85/−0.88 LSBs, respectively. Moreover, the proposed dither-based calibration technique introduces an additional power consumption of less than 2 mW. Full article

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude. Full article