Search Results (60)

Currently, quantum steganography schemes utilizing the least significant bit (LSB) approach are primarily optimized for fixed-point data processing, yet they encounter precision limitations when handling extended floating-point data structures owing to quantization error accumulation. To overcome precision constraints in quantum data hiding, the EPlsb-MFQS and MVlsb-MFQS quantum steganography algorithms are constructed based on the LSB approach in this study. The multichannel floating-point quantum representation of digital signals (MFQS) model enhances information hiding by augmenting the number of available channels, thereby increasing the embedding capacity of the LSB approach. Firstly, we analyze the limitations of fixed-point signals steganography schemes and propose the conventional quantum steganography scheme based on the LSB approach for the MFQS model, achieving enhanced embedding capacity. Moreover, the enhanced embedding efficiency of the EPlsb-MFQS algorithm primarily stems from the superposition probability adjustment of the LSB approach. Then, to prevent an unauthorized person easily extracting secret messages, we utilize channel qubits and position qubits as novel carriers during quantum message encoding. The secret message is encoded into the signal’s qubits of the transmission using a particular modulo value rather than through sequential embedding, thereby enhancing the security and reducing the time complexity in the MVlsb-MFQS algorithm. However, this algorithm in the spatial domain has low robustness and security. Therefore, an improved method of transferring the steganographic process to the quantum Fourier transformed domain to further enhance security is also proposed. This scheme establishes the essential building blocks for quantum signal processing, paving the way for advanced quantum algorithms. Compared with available quantum steganography schemes, the proposed steganography schemes achieve significant improvements in embedding efficiency and security. Finally, we theoretically delineate, in detail, the quantum circuit design and operation process. Full article

The swift advancement of information and communication technology has made it increasingly difficult to guarantee the security of transmitted data. Traditional encryption techniques, particularly in multimedia applications, frequently fail to defend against sophisticated attacks, such as chosen-plaintext, differential, and statistical analysis attacks. More often than not, traditional cryptographic methods lack proper diffusion and sufficient randomness, which is why they are vulnerable to these types of attacks. By combining multi-level chaotic maps with Least Significant Bit (LSB) steganography and Advanced Encryption Standard (AES) encryption, this study proposes an improved security approach for picture transmission. A hybrid chaotic system dynamically creates the encryption keys, guaranteeing high unpredictability and resistance to brute-force attacks. Next, it incorporates the encrypted images into video frames, making it challenging to find the secret data. The suggested method demonstrates its resilience to statistical attacks by achieving entropy values over 7.99 and number of pixels change rate (NPCR) values above 99.63% in contrast to traditional encryption techniques, showing how resilient it is to statistical attacks. Our hybrid approach improves data secrecy and resistance to various cryptographic attacks. Experimental results confirm the efficiency of the suggested technique by achieving entropy values around 7.99, number of pixels change rate (NPCR) values above 99.63%, and unified average changing intensity (UACI) values over 31.98%, ensuring the secure transmission of sensitive images while maintaining video imperceptibility. Full article

The utilisation of 3D models in low-cost devices, such as the internet of things, virtual reality, and augmented reality, is expanding. The challenge lies in the lack of lightweight solutions for verifying the authenticity of models in the graphics library transmission format (glTF) on devices with limited resources. The glTF standard, which allows storage in glb format, is the leading standard for representing 3D assets. Despite its popularity, research on watermarking glTF models remains limited. This paper proposes a novel method for authenticating 3D models in glb format based on fragile watermarking. Additionally, an analysis was conducted to determine the impact of embedding the watermark in vertex attributes other than position on the integrity and visual quality of the model. The methodology is as follows: (1) embedding the watermark, (2) applying model modification or omitting it, and (3) verifying authenticity based on the recovered watermark. The proposed algorithm attaches a 512-bit hash-based message authentication code (HMAC) to a 3D model using the least significant bits (LSBs) modification method. The use of HMAC and LSBs has resulted in a computationally efficient algorithm that can be implemented in low-cost devices. Full article

With the rapid expansion of digital communication and data sharing, ensuring robust security for sensitive information has become increasingly critical, particularly when data are transmitted over public networks. Traditional encryption techniques are increasingly vulnerable to evolving cyber threats, making single-layer security mechanisms less effective. This study proposes a multi-layered security approach that integrates cryptographic and steganographic techniques to enhance data protection. The framework leverages advanced methods such as encrypted data embedding in images, DNA sequence coding, QR codes, and least significant bit (LSB) steganography. To evaluate its effectiveness, experiments were conducted using text messages, text files, and images, with security assessments based on PSNR, MSE, SNR, and encryption–decryption times for text data. Image security was analyzed through visual inspection, correlation, entropy, standard deviation, key space analysis, randomness, and differential analysis. The proposed method demonstrated strong resilience against differential cryptanalysis, achieving high NPCR values (99.5784%, 99.4292%, and 99.5784%) and UACI values (33.5873%, 33.5149%, and 33.3745%), indicating robust diffusion and confusion properties. These results highlight the reliability and effectiveness of the proposed framework in safeguarding data integrity and confidentiality, providing a promising direction for future cryptographic research. Full article

This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm². The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency. Full article

With the increasing amount of cloud-based speech files, the privacy protection of speech files faces significant challenges. Therefore, integrity authentication of speech files is crucial, and there are two pivotal problems: (1) how to achieve fine-grained and highly accurate tampering detection and (2) how to perform high-quality tampering recovery under high tampering ratios. Tampering detection methods and tampering recovery methods of existing speech integrity authentication are mutually balanced, and most tampering recovery methods are carried out under ideal tampering conditions. This paper proposes an encrypted speech integrity authentication method that can simultaneously address both of problems, and its main contributions are as follows: (1) A 2-least significant bit (2-LSB)-based dual fragile watermarking method is proposed to improve tampering detection performance. This method constructs correlations between encrypted speech sampling points by 2-LSB-based fragile watermarking embedding method and achieves low-error tampering detection of tampered sampling points based on four types of fragile watermarkings. (2) A speech self-recovery model based on residual recovery-based linear interpolation (R2-Lerp) is proposed to achieve tampering recovery under high tampering ratios. This method constructs the model based on the correlation between tampered sampling points and their surrounding sampling points and refines the scenarios of the model according to the tampering situation of the sampling points, with experimental results showing that the recovered speech exhibits improved auditory quality and intelligibility. (3) A scrambling encryption algorithm based on the Lorenz mapping is proposed as the speech encryption method. This method scrambles the speech sampling points several times through 4-dimensional chaotic sequence, with experimental results showing that this method not only ensures security but also slightly improves the effect of tampering recovery. Full article

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively. Full article

To address the vulnerability of existing hiding algorithms to differential attacks and the limitations of single chaotic systems, such as small key space and low security, a novel algorithm combining audio encryption with information hiding is proposed. First, the original audio is divided into blocks to enhance efficiency. A “one-time pad” mechanism is achieved by associating the key with the plaintext, and a new multidimensional sine-coupled chaotic map is designed, which, in conjunction with multiple chaotic systems, generates the key stream. Next, the block-processed audio signals are matrix-converted and then encrypted using cyclic remainder scrambling, an improved Josephus scrambling, XOR diffusion, and bit diffusion. This results in an encrypted audio information matrix. Finally, the GHM multiwavelet transform is used to select embedding channels, and the least significant bit (LSB) method is employed to hide the information within the carrier image. The algorithm is symmetric, and decryption involves simply reversing the encryption process on the stego image. Experimental results demonstrate that the Structural Similarity Index (SSIM) between the carrier image and the stego image is 0.992540, the Peak Signal-to-Noise Ratio (PSNR) is 49.659404 dB, and the Mean Squared Error (MSE) is 0.708044. These metrics indicate high statistical similarity and indistinguishability in visual appearance. The key space of the encryption algorithm is approximately 2⁸⁵⁰, which effectively resists brute-force attacks. The energy distribution of the encrypted audio approximates noise, with information entropy close to 8, uniform histograms, high scrambling degree, strong resistance to differential attacks, and robustness against noise and cropping attacks. Full article

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/−0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond. Full article

In digital image security, the Josephus permutation is widely used in cryptography to enhance randomness. However, its application in steganography is underexplored. This study introduces a novel method integrating the Josephus permutation into the LSB 3-3-2 embedding technique for image steganography. This approach improves the randomness of the keystream generated by the chaotic logistic map, addressing vulnerabilities in basic logistic maps susceptible to steganalysis. Our algorithm is tested on RGB images as secret data, presenting higher complexity compared to grayscale images used in previous studies. Comparative analysis shows that the proposed algorithm offers higher payload capacity while maintaining image quality, outperforming traditional LSB techniques. This research advances the field of image steganography by demonstrating the effectiveness of the Josephus permutation in creating more secure and robust steganographic images. Full article

The growing adoption of telemedicine necessitates robust security measures for medical images during transmission. This paper proposes a novel blind watermarking system for medical images that utilizes both image gradients and the Discrete Wavelet Transform (DWT). Image gradients, acting as spatial derivatives, provide a “topological map” of the image, aiding in the identification of areas susceptible to disruption. The DWT, with its multi-resolution analysis, offers a favorable balance between robustness and imperceptibility. The proposed method embeds the watermark within the low–low band (LL) of the DWT-decomposed image, specifically in 3 × 3 block regions selected based on gradient information. The mathematical relationships between the gradient’s direction and magnitude are employed to extract the corresponding blocks and their codes adequately. These codes are then XORed with the watermark and embedded into the chosen blocks using the least significant bit (LSB) technique. Extensive experimentation on a medical image dataset evaluates the system’s performance against some attacks like filtering, noise, and scaling. The results demonstrate the efficacy of the proposed approach in hiding information while ensuring the security and integrity of watermarked medical images. Full article

In recent years, data hiding techniques have emerged as a prominent area of research due to the increasing demand for information security. Existing data hiding techniques typically do not prioritize the verification of the correctness of the extracted data, nor do they attempt to rectify any erroneous information extracted. This paper presents a simple yet effective method by which a recipient can perform error detection and correction on extracted data. Prior to data embedding, a preprocess is applied to secret data. After converting the secret data to a data stream, a data hider categorizes adjacent and identical bits within the data stream into groups. The number of these bits is then recorded as an indicator to extract information and perform error detection and correction. The number of bits in each group is adjusted to ensure that it is an odd number. Moreover, the collected indicator data stream is encoded using (7,4) Hamming code to compact the recorded information. Finally, the concatenation of the encoded indicator and the encoded secret is embedded into the multiple least significant bits (LSBs) of the original image pixels. As for the receiver, error correction can be applied based on the indicator after the extraction of the encoded data. Experimental results demonstrate that this method allows the data receiver to detect and correct errors while maintaining a certain level of embedding capacity and image quality. In terms of image quality, this method exhibits superior performance compared to existing research when the embedded data volume is relatively small. Full article

In this study, we investigate advances in reversible data hiding (RDH), a critical area in the era of widespread digital data sharing. Recognizing the inherent vulnerabilities such as unauthorized access and data corruption during data transmission, we introduce an innovative dual approach to RDH. We use the EMD (Exploiting Modification Direction) method along with an optimized LSB (Least Significant Bit) replacement strategy. This dual method, applied to grayscale images, has been carefully developed to improve data hiding by focusing on modifying pixel pairs. Our approach sets new standards for achieving a balance between high data embedding rates and the integrity of visual quality. The EMD method ensures that each secret digit in a 5-ary notational system is hidden by 2 cover pixels. Meanwhile, our LSB strategy finely adjusts the pixels selected by EMD to minimize data errors. Despite its simplicity, this approach has been proven to outperform existing technologies. It offers a high embedding rate (ER) while maintaining the high visual quality of the stego images. Moreover, it significantly improves data hiding capacity. This enables the full recovery of the original image without increasing file size or adding unnecessary data, marking a significant breakthrough in data security. Full article

This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The reconfigurability of the ADC is achieved through the control of the reset timing of a 5-bit counter enabled by an external signal. The proposed ADC was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) n-well 1-poly 8-metal process. Experimental measurements revealed that the ADC operates at a speed of 454 kS/s with power consumption of 18.7 μW. The Effective Number of Bits (ENoB) achieved by the ADC is 10.9 bits based on a 14-bit scale or 10.2 bits based on a 12-bit scale. The Figure of Merit (FoM) for the ADC is calculated to be 21.5 fJ/step for the 14-bit scale and 22.1 fJ/step for the 12-bit scale. Full article

This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with reconfigurable SAR logic circuit and 4-bit single-slope digital ramp generator. Measurement results demonstrate the power consumption of 34.0 uW, which includes analog power of 23.8 uW and digital power of 10.2 uW, INL/DNL of ±3.5 LSB and −1.0/+2.5 LSB. The ENOB and FoM are measured to be 10.8 bits and 53 fJ/step, respectively. Full article