A Perspective on Analog and Mixed-Signal IC Design Amid Semiconductor Paradigm Shifts

Abstract

This position paper extends the author’s keynote address from the 2024 IEEE European Solid-State Electronics Research Conference, offering a perspective on effective strategies for the advancement of analog and mixed-signal (AMS) integrated circuit (IC) design. It is argued that traditional methodologies, characterized by their focus on transistor-level optimization within individual sub-blocks, are insufficient for satisfying the stringent performance and power consumption demands of contemporary information and communication technologies (ICT), especially in the context of expanding AI applications. Consequently, a paradigm shift is necessary, emphasizing “full-stack” solutions that prioritize comprehensive system-level analysis and aim to minimize physical resources and reduce complexity by innovating across the established boundaries of design abstraction levels. Building on prior work, this manuscript offers a more thorough justification for the proposed full-stack analog design methodology, supported by broader evidence and more comprehensive discussion. It also identifies key considerations regarding EDA and workforce development as topics for future work.

1. Introduction

1.1. Growing Complexity, Engineering Challenges

For decades, the relentless growth of information and communication technology (ICT) has driven hardware and software innovation [1,2]. Today, the demand for greater data processing, storage, and communication, especially for AI applications, is accelerating at an incredible pace [3,4,5,6]. But the present trends are unsustainable without addressing several technological obstacles [1,2,4], impacting both analog and digital IC design.

For a long time, an integrated system’s processing power was directly tied to its transistor count, a trend fueled by Moore’s Law. But recently, the energy and cost benefits of feature scaling have slowed down [7,8]. “Scaling in” the growing processing capability into a single SoC has reached its limits, since the “reticle limit” constrains a single IC’s area to around 800 mm² [5]. Technologies like wafer-scale and 3D integration, and a multitude of heterogenous integration (HI) options, aim to sustain functional growth by “scaling out” of SoC’s reticle limitations and into systems made of multiple chiplets, while managing costs [2,6,7,8,9,10]. Partitioning functionality over multiple co-packaged chiplets is complex yet promising in terms of containing the issues with limited physical resources, namely, Performance, Power, and Area (PPA), for some time. However, the projected processing power growth rate demanded by several applications largely outpaces the containment capability of physical resources achievable in this manner [2,4]. Not all processing can be segregated into ever-expanding data centers and, while on a gigantically smaller scale, edge processing is subject to a not much less concerning exponential. It is critically important to develop additional new alternatives that make more efficient use of the available physical resources.

1.2. Full-Stack Engineering

It is possible to cope with growing PPA demands by adopting a “full-stack” engineering approach. This is about solving design challenges at each and every hardware abstraction level, from circuits and architecture to signal processing and algorithms, painstakingly surfacing and eliminating redundance, relaxing stringent trade-offs, and overcoming obstacles instead of adding more transistors through device scaling and heterogeneous integration (HI).

An example of “full-stack engineering” in the context of digital processor design is illustrated by a recent breakdown of a 10-year, 1000-fold performance improvement (in tera-ops) in GPUs for AI [11,12]. It showed that such amazing performance gains came from a variety of sources: 2× from pruning neural net sparsity, 12.5× from optimizing complex instructions execution by reducing fetch and decode overhead, 16× from a smarter choice of numeric representation, and only a residual 2.5× from physical scaling from 28 nm to 5 nm.

Similarly, in software engineering, developers have long battled challenges like explosive code size, complexity, and inefficiency [13,14,15]. Many causes have been identified, from software design methodology and sub-optimal information representation to accelerated development schedules and the operation of large design teams [13]. However, systematic methods, at the algorithmic and instructional levels, also involving data structure optimization and leveraging specific hardware architectures, etc., have been developed to achieve orders of magnitudes of improvements without hardware upgrades [15].

AI contributes to increasing hardware and software complexity through expanding machine learning models and training sets [4]. While AI also helps automate and speed up design, the current outcomes often result in bloated, inefficient designs, even with human-driven optimization [16,17].

The conclusion is clear: while there is no “silver bullet” solution, managing complexity requires an all-level effort, with co-design from the device level all the way up to the application level. Taming the obstacles of slowed lithography scaling is possible, but without a full-stack approach, the energy requirements and the number of transistors and chiplets will continue to grow at an unsustainable pace.

1.3. Analog Circuits Are Subject to the Same Driving Forces—What Can Be Done?

These conflicting trends of growing complexity and a slowdown in scaling do not spare crucial classes of Analog and Mixed-Signal (AMS) systems and are often the direct result of trends originating from digital systems. For instance, the rapid rise of distributed computing, whether it is cloud-based (data centers) or decentralized and heterogenous, puts enormous demands on wired [18,19] (including photonics [20]) and wireless infrastructure [21,22], mandating the development of increasingly complex high-performance AMS systems. Moreover, HI requires internal die-to-die/chiplet data links and longer-reach interfaces to the outside of the HI, also requiring more high-performance AMS systems [9]. Not to mention the proliferation of analog-to-digital interfaces in emerging cyber–physical systems [23].

AMS is hence subject to equivalent trends in requirements that, adopting the present design approaches, drive up power consumption, transistor count, and complexity, just like in digital systems, especially when these AMS systems are also directly needed by the latter.

In addition to that, increasing performance demands on individual AMS processing systems are addressed through larger array processing architectures and techniques such as interleaving, multi-path filtering, beamforming, neural nets, etc., where the required end functionality and performance is achieved by parallelizing similar or identical sub-functions and repeated elements. Consequently, every reduction in physical resources in the array’s individual elements (conversely, each waste or redundance) multiplies in line with the array’s size.

Analogous “full-stack” design methods can then be a viable path for addressing the emerging challenges of mixed-signal IC designs. Drawing a parallel somewhat inspired by the example of the GPU’s evolution, where a digital processor represents numeric data in integer form or in floating point, correspondingly, an AMS system processes continuous-value signals, or quantized ones with different degrees of granularity, or in continuous-time versus uniformly sampled or non-uniformly sampled and so on. Where a Tensor Processing Unit (TPU) uses specific architectures to be PPA-optimal compared to a GPU for effective tensor processing, analogously, an AMS data acquisition system in a motion sensing application can be especially architected to wake up from sleep mode to digitize the input when a particular sensed pattern occurs, as opposed to using a traditional but far less efficient architecture that is constantly and uniformly sampling the sensors’ output, deferring the input recognition and corresponding action to a digital back-end processor. Many analogs arise upon deeper observation.

But, unlike the case of digital design, or software engineering, full-stack AMS methods are not nearly as developed and often only superficially pursued. The main thesis of this paper is that this is a rapidly widening design and methodology gap urgently requiring our technical community’s attention. It is imperative to rethink mixed-signal IC design, beyond a focus on transistor-level circuits, often using only standard functions (e.g., an amplifier, a comparator, etc.) and few established architectures. It is necessary to broaden AMS design innovation to include and combine all levels of abstraction and, where it makes sense, to fully adopt ideas and techniques from adjacent disciplines such as signal processing or system theory that are often neglected by analog designers.

Fragmented efforts in this direction exist in the literature and examples of approaches solving analog design challenges at various abstraction levels are emerging. While far from being exhaustive, some of these analog techniques are illustrated below to provide a starting point for further study and support this paper’s views. Combining and adopting these methodologies, and exploring others along the same principles, provides our technical community with a promising way to move forward, similarly to parallels found in modern digital design or software engineering.

Undoubtedly, any methodology shift is accompanied by challenges and needs to be put in the context of other disciplines such as design automation or the organization and operation of design teams.

As an aside, it is important to point out one more practical concern. In the West, the talent pipeline for IC design, particularly analog, is shrinking rapidly. Ironically, as governments in the US, EU, and UK pour incentives into reshoring semiconductor manufacturing, due to a scarcer number of college students pursuing IC design (and, correspondingly, of faculty positions), their current leadership in chip design is declining even more quickly [24].

All of this is fully acknowledged, and some initial thoughts are shared toward the end of this paper, hoping to engage the reader in overcoming such difficulties.

2. Tackling Complexity: A Multi-Level Approach

In digital hardware, complexity is managed by using a hierarchy of abstraction levels, including physical level, transistor/circuit/switch level, timing/gate level, functional/register-transfer level, architecture/behavioral level, system level, etc.

Similar abstractions are commonly extended to complex mixed-signal systems such as data converters, DLLs/PLLs, and SERDESs [25,26,27,28]. But analog designers often place their primary focus on the transistor and physical levels. This is also reflected in higher education, and it facilitates production efficiencies based on re-usable/standard IP development in industry. This alone is no longer optimal [29]. In the following, examples of innovative approaches addressing some of these limitations by operating at, and even blurring the boundaries between, multiple abstraction levels, ultimately reducing redundancy and enhancing efficiency, are presented.

2.1. System Level

A system-level transformation can overcome stringent circuit-level requirements, reduce redundancy, and improve PPA. A classic data acquisition chain is shown in the example of Figure 1, where an analog signal v_in is digitized to produce a corresponding code D. A sample-and-hold (S/H) is clocked by ck at frequency f_s and its capacitive input load requires a low impedance buffer to drive it. Anti-aliasing (AA) is implemented by a cascade of continuous-time (CT) filter cells with transfer function H(s). The N-bit ADC, clocked at frequency f_s, produces D.

A direct transistor-level implementation of individual functions requires careful consideration of noise, linearity, and area budgets for each block to meet combined specifications on D, resulting in total power consumption P. The common practice is to give each block its own set of specs, with a generous margin, and assign it to a different designer. Ideally, once each block is individually optimized and then integrated, minimal refinements should be needed. While common practice often diverges from this ideal strategy, there can be room for deeper methodology improvement. Instead of rushing to size transistors, designers should spend more time and effort on system-level implementation.

2.1.1. Merge and Relocate Functions

Transforming the signal chain by relocating some sensitive blocks and merging functions can lead to significant PPA improvements and design simplifications. For example, it turns out, as described in [30,31] that this chain can be modified and simplified to meet the exact same result on D but relaxing multiple constraints. It is possible to merge the CT AA filtering with the ADC, relaxing their requirements of both, as in the resulting pipelined architecture shown in Figure 2. Moving the S/H from the front to the back of the pipeline relaxes accuracy and impedance requirements, eliminating the need for a buffer [30,31]. Inherent anti-aliasing is obtained by merging filters and ADC and, more importantly, the scheme shown in Figure 2 achieves lower noise, lower area, and better linearity for the same power dissipation P compared to Figure 1. Finally, as demonstrated in [32], the sampling clock’s phase noise requirements of the internal S/H are also relaxed, which in turn reduces the clock generator’s power consumption.

Extensive benchmarking between CT pipelined ADC prototypes and comparable ADCs as well as active filters can be found in [30,32]. While there are a few caveats with respect to what is included or not in these comparisons, a rough estimate of the savings can be ascertained through comparison of common figures of merit normalizing dynamic performance (noise and linearity) and sample rate for power consumption. The CT pipelined ADC prototypes outperforms most classic ADC architectures by as little as 1~2 dB (a 20% to 50% in power savings) and much as 10 dB (nearly 10 times lower power) and all active filters by at least 12 dB (15 times lower power) and up to more than 30 dB (nearly 100 times lower power), while demonstrating >3 dB reduction in sampling jitter sensitivity. When combining the areas of comparable ADCs together with analogous filters, the CT pipelined ADCs also save die area ranging between ~20% to well over 60%. Additionally, the nature of the described block-level transformations suggests that trade-offs should be explored, namely, that area could also be reduced at the expense of dynamic performance and power efficiency.

There are limitations for a CT pipelined ADC. First, it is not amenable to being time-interleaved. Second, while it can be made to work for an oversampling ratio as low as four, it does require a high frequency clock. Therefore, the high-frequency performance of this architecture is ultimately limited by the speed of the process technology.

Generalizing the effectiveness of a system-level transformation is not possible, as the benefits are often context-dependent. In the above example, when merging filter blocks with sub-ADCs, the resulting relaxation in filtering requirements is highly dependent on the stage’s gain (G): a higher gain allows for a greater reduction in the filter’s noise specification and power consumption. Despite disclaimers, such transformations hold significant potential for overcoming critical performance trade-offs and are often overlooked.

There are other ways to alleviate the PPA requirements at this abstraction level, such as the next approach, which relies on the unique characteristics of certain signals.

2.1.2. Specialize the Hardware to Better Fit to the Signal or the Application Characteristics

In a uniformly sampled system, a signal is sampled at fixed, regular intervals, as shown in Figure 3a. Instead, in event-driven analog systems, sampling occurs when specific signal events take place, such as level-crossing (Figure 3b), leading to non-uniform sampling (NUS) [33].

In a standard uniformly sampled system, signal reconstruction of x(t) from x(kT_s) at f_s is based on Nyquist’s theorem. But for reconstructing NUS x(t_i), the sampling instants sequence ${\left(t_i\right)}_{i\in \mathbb{N}}$ must accompany the sampled voltages sequence ${\left(x\left(t_i\right)\right)}_{i\in \mathbb{N}}$. For an “active signal” regularly and often crossing quantization levels, such as modulated communication signals, the sampled points in Figure 3a,b are comparable, so uniform sampling is better. But signals that are sparse in time or frequency, like biomedical signals (e.g., electro-cardiograms, electro-encephalograms, etc.), seismic signals, sonars, or speech, among others, are more efficiently represented with less data points using NUS. This reduction in data volume results in a reduction in system resources like power and area, as demonstrated in several studies. For example, in [34,35], a uniformly sampled data acquisition system, as in Figure 1, is replaced by the NUS architecture shown in abstract form in Figure 4.

First, the continuous-time (CT) input v_in(t) is filtered by a very relaxed CT anti-aliasing (AA) filter, H(s), and digitized by a NUS ADC, which consists of two event-driven blocks: a special N-bit quantizer and a digital AA filter. The quantizer samples the analog input only when it crosses the quantization levels at t = t_i and outputs an N-bit word x(t_i) representing the input level, together with a quantized/digital timestamp ${\widehat{t}}_i$ for that instant t_i. Since the input is unambiguously determined by both input level x(t_i) and time instant ${\widehat{t}}_i$, then NUS does not alias. While quantization introduces nonlinear distortion, this appears as high-frequency harmonics that do not alias back into the signal band [33]. The digital signals x(t_i) and ${\widehat{t}}_i$ are then processed by an event-driven digital AA filter G(s), which suppresses the out-of-band (OOB) harmonics, thus reducing the quantization distortion of (x(t_i)),${\widehat{t}}_i$). Finally, to make this digitized signal compatible with a standard, uniformly sampled Digital Signal Processor (DSP), the NUS ADC’s output is resampled at a fixed rate f_s. This is performed by block P(z), which produces the uniformly clocked output D. The uniform resampling by P(z) does cause aliasing, but because the quantization distortion has already been suppressed by G(s) before resampling, then any remaining residue that aliases into the signal band is minimal. The above system provides two benefits: (a) the CT AA filtering H(s) is substantially relaxed compared to the case of Figure 1 and (b) G(s) reduces the quantization distortion before resampling at f_s, hence increasing the in-band signal-to-quantization ratio (SQNR) of D beyond the theoretical maximum set by the number of bits N of a uniformly sampled quantizer (${SQNR}_{dB}\gg 6.02·N+1.76$).

The main limitations of this approach originate from the special quantizer determining x(t_i) and ${\widehat{t}}_i$. This tracks x(t), determining the time t_i at which it crosses one of the reference levels (x(t_i)), and it requires voltage comparators and a time-to-digital converter (TDC) as the time quantizer. The comparators sensing x(t) cannot employ fast and power-efficient clocked architectures, such the well-known dual-tail strong arm comparator, and are subject to signal-dependent delays, offsets, and other shortcomings [35]. But when a reference level is crossed, a pulse triggers the time quantizer that produces ${\widehat{t}}_i$. Fast switching in fine lithography CMOS allows for the resolution of sub-pico-second events and is one of the strengths of this approach. But the quantization of ${\widehat{t}}_i$ (aggravated by additional time jitter) produces residual quantization noise degradation. An in-depth analysis of the theoretical and practical limitations of the above approach, including the relationship between voltage and time quantization, residual aliasing, and noise degradation, can be found in [34,35].

The power efficiency advantage of NUS over comparable uniform sampling depends entirely on the sparsity of x(t) and it can be between 4 to >10 times better for life-monitoring signals (e.g., ECG, EEG), speech, motion sensing, etc. [33].

NUS is not just useful for sparse signals; in appropriate conditions, it can also be a powerful tool for processing non-sparse signals, offering significant savings in power and area. For instance, a well-known challenge with under-sampling a high-frequency signal is that it causes out-of-band (OOB) signals, blockers, and noise to alias into the desired signal band. To prevent this, traditional systems require a selective band-pass (BP) filter for the input signal before sub-sampling, which can be problematic to implement. A different approach using NUS down-conversion followed by a NUS BP blocker rejection filter has been proposed in [36], enabling a narrowband sub-sampling receiver at low mmWave frequency in 28 nm. The NUS down-converter samples the input RF signal at the carrier frequency, down-converting it to baseband. But this NUS spreads the aliased OOB blockers and noise away from baseband, rather than aliasing them into it. The subsequent NUS FIR BP filter suppresses the OOB spurious content since it has passbands far away from baseband. Its filtered output is then sub-sampled by a low-rate ADC with relaxed specifications [36], which saves power and area (up to five times smaller area compared to a traditional approach [36]).

This may not always be possible due to stringent trade-offs. The effectiveness of spreading the OOB blockers’ power away from baseband depends on the relative range of instantaneous frequency variation in the NU sampling, the filtering characteristics, and the ability of the sub-sampling ADC to process residual spurious signal added to the intended narrowband signal [37,38].

2.1.3. Transform the Signal to Fit or Simplify the Hardware

Returning to sparse signals and taking advantage of a priori knowledge of the signal characteristics, another interesting approach is compressive sampling, which merges signal conditioning, compression, and sampling into one, eliminating redundant hardware resources [39,40,41]. While many compressive sampling schemes have been proposed (some using NUS!) [40,41,42], they all follow a similar principle: the original sparse input signal is transformed into a new one (compressed) that is not sparse by changing its basis but relaxing the hardware system intended for its processing. The goal is to preserve most of the original information while making the new signal easier to process. This analog compression, often using signal bases like binary sequences to simplify hardware implementation, allows for more efficient digitization. For example, the compressed signal can be digitized with a much lower sample-rate ADC or a lower dynamic range, saving power and area [42,43,44,45,46,47]. A disadvantage, however, is that de-compressing/restoring the original signal requires digital post-processing, which adds area, power and introduces latency.

A practical example of compressive sampling is reported in [47] in the context of a brain–computer interface (BCI). By selectively discarding samples from neural signals that carry little information, on average, the output data rate is reduced 146 times. When benchmarked against other BCIs of comparable performance, the prototype yields a greater than 3.5-fold reduction in area per channel and a 16.8-fold reduction in power consumption per channel [47].

2.1.4. Capture the Information, Not the Data

To summarize, substantial reductions in analog power, area, and complexity can be achieved through system-level transformations. This involves, among others:

• Combining separate functions into more efficient hybrid structures.
• Relocating sensitive circuit blocks to resolve PPA bottlenecks.
• Re-framing the entire processing chain by leveraging the signal’s unique characteristics.

Extending the latter concept even further, analog-to-information systems aim to directly extract key features from sensory signals before digitization. Instead of processing a complete ECG waveform, for instance, the system might only extract heartbeat information. Similarly, a radio signal’s power level or direction-of-arrival could be measured, with only this crucial information being digitized. This approach bypasses the need to digitize and process the entire signal, leading to significant efficiency gains [41,44,45].

2.2. Functional Level

Some functional simplifications were already shown in the previous sub-section. As exemplified in the next sub-section, another approach involves using digital assistance to relax the requirements of analog functions. Furthermore, some computational architectures are naturally better implemented in AMS systems.

2.2.1. Analog Versus Digital

For some ICT applications, a high-linearity or high-bandwidth amplifier traditionally needs a power-hungry, large-area Class-A circuit. However, it is possible to increase power and area efficiency by intentionally compromising the circuit’s intrinsic analog linearity. The required linearity can then be restored through linearization, provided the additional PPA needed for the linearization is much smaller than the savings from making the original analog circuit less linear. While analog linearization techniques are suitable for mature processes with higher voltage headroom, the opposite is often the case in modern, finer-lithography processes. For the latter, digital circuits are smaller and more power-efficient, making a complex digital linearization scheme a more resource-efficient solution. Techniques such as digital pre-distortion and post-distortion perform the linearity correction in the digital domain, reducing total system power and area for individual analog functions such as amplifiers, mixers, data converters, and possibly entire analog signal processing chains, such as those in a communication system’s transmitter or a receiver [46,47,48,49,50,51,52].

The practical implementation of digital pre- and post-distortion is far more complex than the concept suggests. Effective cancelation hinges on an accurate mathematical model of the system’s nonlinearity, which may also need to track variations in process, voltage, and temperature (PVT) in real-time to limit spectral regrowth. This creates a critical trade-off: more sophisticated models, particularly those accounting for memory effects, achieve deeper distortion cancelation but demand larger and more power-hungry digital compute engines. Customized implementations using look-up tables can effectively simplify the digital implementation. Alternatively, modeling the nonlinearity with a neural network has been shown to improve both model fitness and circuit implementation [52,53].

Furthermore, the challenge extends to data converters and other analog blocks. Nonlinearity generates both in-band intermodulation products and high-frequency harmonics. The latter requires data converters with exceptionally high sample rates and analog bandwidth to process the full spectrum or, at least, contain aliasing [54,55,56,57].

The effectiveness of power reduction when employing distortion compensation techniques is highly application specific. An example is the high-power base station transmitter, where the power amplifier (PA) consumes most of the power. To maintain the required signal linearity without compensation, these PAs must be operated far below their maximum power (“backing off”). This leads to extremely poor power efficiency, often less than 10%. The implementation of digital pre-distortion (DPD) allows the PA to operate much closer to its efficient saturation region, bringing the PA’s efficiency to approximately 25%. While that may appear modest in relative terms, for a component consuming 80 W or more, this improvement translates into a non-negligible reduction in absolute power consumption. This directly lowers a base station’s operational expenses by reducing both electricity and cooling costs. On the other hand, the absolute power savings are negligible in smaller power transmitters such as those used in small/pico-cell base stations where only traditional analog linearization is used instead of DPD [56,57].

2.2.2. When a Few Neurons Are Better than a Microprocessor

With a completely different functional-level approach, machine learning-based techniques have been explored to improve hardware efficiency. Recent work has shown that embedding small neural networks (NNs) can simplify AMS functions. For example, in [58], a single neuron was embedded in the integral control path of a clock and data recovery (CDR) loop controller. This resulted in smaller overheads, better robustness, and wider-range operations. In a more extensive application, the authors of [59] individually replaced many AMS functions in a high-speed SERDES with simpler alternatives. They used a specific encoding method to replace a multi-tap feed-forward equalizer (FFE) in the transmitter with a more compact two-tap FFE. More significantly, in the receiver, a 7-bit high-speed ADC and its back-end DSP were replaced by simpler AMS feature extraction circuits and a neural classifier. This approach yielded multiple benefits for PPA. The use of machine learning in AMS is also beginning to emerge in other areas. Early examples of machine learning-based calibration for ADCs, as seen in [60,61,62], promise to reduce the physical resources required to replace equivalent but more complex traditional hardware.

2.3. Transistor Level

2.3.1. When Less Is More

Many opportunities to improve implementation efficiency and net performance exist at the transistor level. This is especially true when, instead of implementing individual functions with standard circuits, multiple functions can be merged into more compact implementations. The BJT’s Darlington configuration, or stacking a cascode MOS transistor over the drain of another MOS transistor in a common source amplifier, are undergraduate-level examples of merging two cascaded amplification stages into one. Fewer transistors and less interconnect and biasing strays are merged into hybrid structures, efficiently implementing a combination of functions. These core ideas can be greatly extended.

For example, in the amplifier introduced in [63] and shown in Figure 5, all transistors are actively processing the differential input signal $v_{in}=v_{in+}-v_{in-}$ to create two complementary amplified differential outputs $v_1=v_{1+}-v_{1-}$ and $v_2=v_{2+}-v_{2-}$, virtually doubling the available output voltage headroom. As described in detail in [63], the input voltage is terminated on R_T,I and is simultaneously processed by a common gate (CG) stage M_1NA (respectively, M_1PA, M_1NB and M_1PB) and a common source (CS) stage M_2PA (respectively, M_2NA, M_2PB, M_2NB) combining their individual contributions to the output. Additionally, the bottom and top active halves of this circuit realize a pseudo-differential complementary architecture, doubling the resulting gain while re-using the current flowing through the stack from the top to the bottom supply rails.

Another recent example of a current-reuse pseudo-differential complementary amplifier is shown in Figure 6 [64]. For this, the input signal is composed of a pair of level-shifted differential signals $v_{inl}=v_{inl+}-v_{inl-}$ and $v_{inh}=v_{inh+}-v_{inh-}$ fed to common source pairs, which produce the differential output $v_o=v_{o+}-v_{o-}$ through a cascode stage.

However, while with current-reuse multiple functions are merged into efficient circuits, on the other hand, stacking multiple devices can quickly use up the available voltage headroom [65,66,67]. Some headroom can be recovered through careful level-shifting by means of transformers and/or capacitors, as exemplified in the quadrature VCO presented in [68] or the highly efficient merged VCO, filter, and transimpedance output stage demonstrated in [69].

Based on a survey of various reported implementations, it is possible to estimate an average saving of approximately two-fold in both area and power consumption when comparing different merged topologies to their conventional counterparts.

Recently, a new class of minimalistic circuit topologies has gained prominence in the implementation of ultra-low power (ULP) and ultra-low voltage (ULV) systems, particularly for very-low-frequency applications. Architectures such as dynamic amplifiers and floating inverter amplifiers (FIAs) introduce significant structural changes compared to conventional analog circuits. Most traditional analog active stages operate around a stable quiescent point, which provides well-controlled performance parameters such as gain, bandwidth, noise, and distortion. Conversely, the active cores of dynamic and floating inverter amplifiers are typically basic transconductors made of very few transistors that are either unbiased or self-biased. These active blocks dynamically steer current from the power supply, or from reservoir capacitors employed as floating batteries, into the output load in response to the input signal. While this approach enables processing with very high power efficiency, it is presently limited to low-frequency operation. It also introduces substantial challenges, including significant nonlinearities and sensitivity to process, supply, and temperature (PVT) variations. A growing number of techniques are emerging to manage these impairments and to improve robustness against PVT effects. As for other cases discussed in this section, a minimalistic circuit topology allows for power savings. In some cases, over an order of magnitude in power reduction compared to class A topologies for low-frequency operation have been demonstrated [70,71], and the reader is deferred to excellent references such as [72] for an overview.

Another technique that makes the most of fewer transistors and that is regaining [73] popularity thanks to the availability of fully depleted silicon-on-insulator (FD-SOI) technology uses the MOS transistor’s backgate/bulk as an additional device terminal for memory, control, or direct signal processing. In both FD-SOI and standard planar processes, controlling the back-gate voltage allows for the dynamic modulation of the transistor’s threshold voltage. This, in turn, adjusts the drain current and the device’s bias point, a capability that has spurred a wide variety of compact and creative circuit topologies for analog, RF/mmWave, and even low-power digital implementations [74,75].

Lastly, many elegant ideas of compact and efficient configurations have originally been introduced in Bipolar/BiCMOS circuits in the past. Because, unlike MOS transistors, BJTs are not amenable to scaling and hence progress relied on different principles, particularly keeping the transistor count to a minimum and exploiting the nonlinearity of the devices’ exponential characteristics [76]. That gave rise to many elegant circuits where multiple functions merge into just a handful of transistors [65]. Many BJT architectures were used as a starting point for corresponding MOS architectures when RF MOS technology emerged during the past few decades. But more can be achieved. For instance, while MOS’s square law characteristic cannot match the precision and range of a BJT’s exponential, BJT-inspired circuit primitives have been successfully mapped and extended to compact MOS equivalents, and many additional topologies have been introduced [77]. But these are not well-known because they are not often taught in university courses or widely employed in industry practice. Since today’s MOS scaling faces similar challenges to scaling-adverse BJT circuits, these and other efficient and versatile topologies open many new opportunities and deserve more attention.

2.3.2. Nature Is Frugal: The Brain Is Analog

AMS neural ICs constitute another demonstration of rapidly growing systems where impactful transistor level simplifications are viable, and what is being achieved for these networks can be insightful for similar gains in other classes of analog circuits. First, it has long been acknowledged that neuromorphic systems [78,79] are best implemented using analog circuits thanks to relaxed neuron precision requirements allowing the implemented network’s operation to be robust to physical impairments affecting analog computational accuracy such as noise, mismatch, and nonlinearity [80,81,82]. Second, in digital accelerators, replacing digital MAC (multiply-and-accumulate) functions in convolutional layers with AMS implementations also improves efficiency [83,84,85].

More precisely, in the specific case of Compute-in-Memory (CIM), several examples of Analog CIM (ACIM) and Digital CIM (DCIM) architectures have been published. Low voltage/low power implementation variants abound, with ACIMs performing the MAC functions in current- (or voltage-), time-, and charge-domains, while DCIMs employ at least as many variants of synchronous and asynchronous serial or parallel logic for varying bit-width. And while ACIM’s MAC can be implemented enabling vastly less power and area (orders of magnitude) than the DCIM’s counterpart, particularly for large arrays with multiple layers, delivering the ACIM’s final output to a digital processing system for storage (e.g., SRAM) or further use requires analog-to-digital conversion, which, depending on the circumstances, can be revealed to be the most challenging PPA bottleneck.

A quantitative benchmarking study, based on a unified analytical performance model, can be found in [86]. It provides a detailed assessment of both architectures across various workloads and configurations, outlining how much each approach (ACIM vs. DCIM) theoretically outperforms the other depending on requirements.

2.4. Summary

In summary, this Section has discussed several ingenious analog solutions that span multiple abstraction levels to address growing demands for performance, power, and area (PPA), as well as complexity. It is important to note that these techniques can often be combined, potentially yielding mutual greater benefits.

Table 1. Summary of the main exemplary techniques discussed in Section 2.

Abstraction Level	Representative Techniques	Remarks	Possible Power Savings	Possible Area Savings
System (2.1)	Re-arrange, merge/split functional blocks (2.1.1)	Performance metrics’ trade-offs can enable optimal implementations	From marginal to >10 times	From marginal to 1.5 times
	NUS, compressive sampling, feature extraction and application-specific processing (2.1.2)–(2.1.3)	Highly application dependent. May require post-processing.	From marginal to >100 times	Up to 5 times
Functional (2.2)	Digital Nonlinear Correction (2.2.1)	Highly application dependent.	From marginal to >2 times.	Up to 2 times.
	Neural Approximation (2.2.2)
Transistor (2.3)	Complementary/Current re-use/composite topologies/bulk-driven (2.3.1)	Involves supply/signal swing trade-offs	Up to ~2 times	Up to ~2 times
	Dynamic Amps/Floating Inverters (2.3.1)	PVT sensitive. Low frequency operation.	>>10 times	Marginal

provides a high-level, though not exhaustive, summary of these approaches, indicating some of their limits and anecdotal estimates of power and area savings reported in the literature. Countless more are likely to be discovered.

This table is not intended as a prescriptive list of solutions. Rather, the key takeaway is that designers can overcome seemingly rigid trade-offs by looking beyond established, general purpose transistor-level topologies and pursuing creative solutions that transcend abstraction levels.

3. Conclusive Considerations

3.1. Blur the Disciplinary and Departmental Barriers

Adopting the design methodologies discussed previously holds great promise, but it is far from simple. Success requires strong technical collaboration between integrated circuit (IC) designers (e.g., chip vendors) and system engineers (e.g., OEMs) to ensure that application requirements are consistent with silicon capabilities and cost constraints. It is crucial to focus on defining the core requirements and objectives—the “what”—before diving into the implementation—the “how.” A collaborative approach, where system and circuit designers co-define and specify a system using a high-level model reflective of the strengths and limitations of IC technology, enables them to determine more realistic specifications than is possible with rigid spec sheets. This collaboration eliminates the all-too-common practice of adding extra (excessive) margins to sensitive specifications to make up for an oversimplified system description or to de-risk a project.

3.2. Abstract, Collapse, Repeat

Another key principle is to embrace multiple abstraction levels, not just the transistor level. The goal at every design stage should be to reduce the complexity and size of the implementation. Effective solutions arise from innovating at each abstraction level (i.e., system, functional, circuit) and blurring the boundaries between them. This iterative process of going up and down the abstraction levels, playing with “what if” scenarios, possibly learning from mistakes, continues until the design is fully optimized. The main challenge lies in decomposing the design into blocks in a way that minimizes overall resource usage.

This methodology shift also has significant operational implications. While a rigid block-based top-down design and specification approach can directly be distributed among a large design team, this standard approach is often limited by communication overhead between team members. In contrast, an iterative “full-stack” process requires a small, tightly knit team for efficient development, especially in the early stages. A larger headcount can then be brought in later to finalize and verify the design.

3.3. EDA Considerations

Along with the engineering operation dynamics, Electronic Design Automation (EDA) has always spurred significant changes in AMS design methodology, and the rapid evolution of AI is anticipated to trigger major shifts in the next five to ten years [87]. Currently, AI’s most common application in AMS circuit design is in boosting productivity by automating repetitive tasks of design optimization and verification, particularly at the transistor level and during the physical design. This works when using well-established and extensively studied architectures, akin to analog standardized circuit cells [88,89,90,91]. But, with or without AI, using compartmentalized approaches alongside many EDA systems, opportunities for substantial PPA reduction in the final design are easily hidden by block partitions and rigid abstractions, and hence completely missed. Additionally, there is a trade-off. Just as rapidly creating large software programs by assembling standard code from libraries can lead to bloated, inefficient software, a similar approach in AMS design—building complex signal chains by using only traditional circuits to speed up the development process, even when individually EDA-optimized—can result in overall larger final designs with low PPA efficiency, increasingly inadequate for the growing demands [87]. In other words, extreme operational efficiency, aided by AI, cannot make up for a suboptimal system solution.

Instead, since, inherently, most effective analog designs originate from “visualizing” and choosing solutions among multiple seemingly valid options and require making practical trade-offs as the implementation process progresses, greater benefits may then emerge from future agentic AI assistance [87,92]. While promising, the latter approach is recent and rapidly developing and it is premature to draw assertions on its adoption. Relying on well-defined and established topologies, published experiments report the use of multi-agent frameworks to automate and optimize various stages of circuit design (e.g., specification understanding, iterative circuit optimization by refining the design search space, and test bench validation) based on clearly defined cost functions [93,94,95,96,97]. In contrast with similar AI-based efforts for coding (e.g., “vibe coding”), even powerful reasoning models struggle with inherent analog hardware concepts such as concurrent operation as opposed to sequential execution, or the use of block-box optimization methods missing domain-specific knowledge, and these models have a lack of scalability beyond “scholastic” test cases. Moreover, particularly when relying on deep neural networks, access to large amounts of training data is a fundamental barrier. With that said, with human direction, this kind of AI could aid the designer in exploring and assessing multiple options through ingenious “full-stack” design approaches, such as those exemplified above. While the exact path of this evolution is hard to predict, the AMS designer’s role should increasingly focus on the most creative parts of the engineering problem. Automation can support the rapid exploration of different options [94,95,96], but it is still human creativity and intuition that is needed in order to lead to a thoughtful result.

3.4. Workforce Development Considerations

This shift in focus requires a parallel evolution in workforce development, particularly in higher education: it should concentrate on building a deeper understanding of first principles, while also encouraging and developing intuition, creative skills, and critical thinking, prioritizing the introduction of traditional circuit architectures with the purpose of teaching the core engineering principles they embody. This will open students’ minds to developing unconventional, yet optimal, solutions to new problems.

3.5. Smarter or More Productive?

Analog design should never be reduced to a relentless effort in optimizing the figures of merit [29,97] out of a rigid library of standard functions. A more holistic and creative approach not only helps overcome future technical challenges but also echoes the early innovations that originally spurred this discipline, and it may be the key to re-energizing it once more [98,99].