TDM Test Scheduler and TAM Optimization Toolkit: An Integrated Framework for Test Processes of DVFS-Based SoCs with Multiple Voltage Islands

Abstract

The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities.

1. Introduction

Power consumption remains a critical design constraint in modern electronic systems. To address this challenge, Dynamic Voltage and Frequency Scaling (DVFS) and voltage islands have become key techniques for enhancing energy efficiency in high-performance, low-power SoCs, particularly in mobile and battery-powered devices [1,2]. DVFS is a power management approach that dynamically adjusts the supply voltage and operating frequency based on the system’s workload, reducing power consumption during periods of low-performance demand. Voltage islands, on the other hand, partition the SoC into multiple regions (islands), with each region operating under an independent power supply rail and potentially at a different voltage level. This design flexibility allows each island to function at the voltage and frequency best suited to its performance and power requirements, enabling localized power optimization across the SoC.

The integration of these low-power techniques in SoCs substantially impacts the manufacturing test process and, consequently, test costs. The multi-voltage testing requirement leads to a substantial increase in test data volume and prolonged test application times [3], ultimately driving up test costs. The challenge becomes greater by the need to adapt scan frequencies and TAM configurations to accommodate different voltage levels, introducing additional test scheduling and power constraints during the test process [4,5]. Consequently, specialized design-for-testability (DFT) solutions and test optimization techniques should be used to address the unique challenges posed by DVFS and multi-voltage SoC architectures while minimizing test time and cost.

This work presents a novel integrated framework, implemented as a software toolkit [6], that effectively utilizes the Time-Division Multiplexing (TDM) methodology [4] for testing DVFS-based SoCs with multiple voltage islands. The proposed toolkit generates cost-effective and power-aware test processes tailored for application in the final production stages of the VLSI industry. Overall, the proposed toolkit supports five (5) major functionalities:

• Efficient representation and verification of test processes targeting SoCs that consist of IP cores placed in multiple voltage islands operating at different voltage or frequency settings. A specialized, easy-to-use high-level language (HLL) has been developed to specify the modular SoC under test, the test environment, and its constraints. A verification tool is offered to perform syntactical and logical checks in HLL programs.
• Compilation and execution of test processes written in HLL. The results are optimal test schedules annotated with power- and thermal-related data. It should be noted that thermal data are acquired from the Hotspot tool [7]. It can be integrated into the proposed toolkit via a specialized interface.
• Test Access Mechanism (TAM) Optimization for multi-$V_{dd}$ SoCs. In addition, special mechanisms have been developed to address the high complexity of large SoC designs.
• Visualization of power- and thermal-annotated test schedules generated by the toolkit’s solvers. Animation on SoC’s floorplan is available too.
• Generation of test processes for artificial multi-$V_{dd}$ SoCs that may consist of benchmark cores. They can be used mainly for educational and research activities. A floorplan of the targeted artificial SoC can be created using the hotfloorplan tool [7] according to the user’s needs.

This introduction is followed by Section 2, which provides (a) the motivation underlying the Time-Division Multiplexing (TDM) methodology for testing multi-$V_{dd}$ SoCs and (b) an overview of basic computational techniques integrated into the toolkit. The rationale for developing the proposed toolkit is further elaborated in Section 3. Section 4 provides a detailed overview of the toolkit’s components, while Section 5 outlines its core workflows. In Section 6, the toolkit’s capabilities and results are demonstrated through three exemplary use cases. Finally, Section 7 presents concluding remarks and an outlook on future developments.

2. Background

Testing multi-$V_{dd}$ SoCs is time-intensive due to the need for tests across multiple voltage levels [8,9]. Constraints such as restricted concurrent testing of cores within the same voltage island at different voltages and dependencies introduced by TAM structures further complicate test scheduling. Additionally, lower voltage levels require reduced scan frequencies to prevent timing violations in scan chains, wrappers, and decompression logic, leading to significantly longer test times compared with single-$V_{dd}$ SoCs.

Example 1.

Figure 1a illustrates a SoC comprising cores $C_1$ and $C_2$ within voltage island $L_1$ and core $C_3$ within voltage island $L_2$. Core $C_2$ and core $C_3$ are connected to TAM Bus 1, while core $C_1$ is connected to TAM Bus 2. Both voltage islands support two voltage levels $V_1$ and $V_2$, with corresponding nominal scan frequencies of F and $F/2$, respectively. The tester supplies test data at frequency F for SoC testing. Note that core $C_2$ and core $C_3$ cannot be tested simultaneously as they share TAM Bus 1. Furthermore, this shared bus introduces a dependency between voltage islands $L_1$ and $L_2$, which may impose constraints on test scheduling. Although cores $C_1$ and $C_2$ do not share a bus, they cannot be tested concurrently at different voltage levels because they utilize the same power grid. Figure 1b graphically illustrates the increased complexity of testing a multi-$V_{dd}$ SoC compared with a single-$V_{dd}$ SoC. It highlights the additional constraints introduced by multiple voltage domains, such as test scheduling dependencies, power grid limitations, and varying scan frequencies, which collectively increase the challenges of efficient test execution.

As demonstrated in [4], conventional test scheduling methods are ineffective in reducing test time for multi-$V_{dd}$ SoCs, as they fail to address the unique challenges posed by multiple voltage domains. On the other hand, TDM optimizes test time by enabling parallel testing of cores that share TAM resources [4]. With TDM, test data are transmitted by the tester at a high frequency and then shifted through the wrapper’s parallel port (WPP) into the scan chains of multiple cores at lower frequencies, determined by each core’s voltage level. Hence, TDM manages to exploit the gap between (a) the tester frequency and the shift frequencies of the cores, (b) the different shift frequencies of different cores, and (c) the shift frequencies of the cores at different voltage settings.

Example 2.

Consider a tester supplying test data at frequency F for testing the SoC depicted in Figure 1a. A clock divider, driven by the tester’s clock, provides a shift frequency of F to Core $C_1$ and $F/2$ to Cores $C_2$ and $C_3$. In one possible test scenario, Core $C_1$ fully utilizes TAM Bus 2 to be tested at voltage $V_1$, while Cores $C_2$ and $C_3$ are tested in parallel at $V_1$ and $V_2$, respectively, using a shift frequency of $F/2$. Note that the clock divider’s signals ensure non-overlapping test data loading onto the shared TAM Bus 2 at scan frequency $F/2$.

TDM requires specialized techniques to ensure that each test operates at the most efficient shift frequency, thereby minimizing overall test time. To address this complex optimization problem, a Rectangle Packing-Simulated Annealing (RP-SA) method was proposed in [4]. In the RP-SA approach, each test $\tau$ at a given frequency F is represented as a rectangle, where the width corresponds to the frequency and the height represents the test duration at that frequency. Each bus of TAM is modeled as a virtual bin with unlimited height and a width equal to the maximum frequency supported by the ATE channel. The objective is to pack these rectangles into their respective bins while minimizing the total height, effectively reducing test time.

The simulated annealing (SA) algorithm iterates through different test configurations by randomly selecting shift frequencies before applying the rectangle packing strategy. Its computational cost remains manageable for medium to very large SoCs. However, in scenarios where TAM optimization is required or when computational resources and time are highly constrained, a rapid estimation method becomes essential. To address such cases, the Greedy Rectangle Packing (GRP) approach was developed. Unlike $RP-SA$, the $GRP$ technique executes rectangle packing only once, providing a significantly faster, more resource-efficient, but sometimes inferior test scheduling solution compared with $RP-SA$.

Example 3.

Consider again the artificial SoC depicted in Figure 1a. In this example, cores $C_1,C_2,C_3$ correspond to the IWLS [10,11] benchmark cores $us{b}_{f}unc$, $w{b}_{c}onmax$, and $de{s}_{p}erf$. Each voltage island supports three voltage levels, $V_1,V_2,$ and $V_3$, with nominal scan frequencies of $F_1=400$ MHz, $F_2=200$ MHz, and $F_3=100$ MHz, respectively. The tester provides a 400 MHz clock signal. Test times for each core at $V_1,V_2$, and $V_3$, when using the maximum rated shift frequency per voltage level, can be found in [6], along with required data for replicating the test process using the proposed tool. Now, consider the following set of tests, where each test operates at the maximum rated frequency for its voltage level: $S_a=\{{\tau }_{C_1{V}_1{F}_1}$, ${\tau }_{C_1{V}_2{F}_2}$, ${\tau }_{C_1{V}_3{F}_3}$, ${\tau }_{C_2{V}_1{F}_1}$, ${\tau }_{C_2{V}_2{F}_2}$, ${\tau }_{C_2{V}_3{F}_3}$, ${\tau }_{C_3{V}_1{F}_1}$, ${\tau }_{C_3{V}_2{F}_2}$, ${\tau }_{C_3{V}_3{F}_3}\}$. This set represents a complete test process for the given SoC. Each test is modeled as a rectangle, as explained above. For example, the candidate test ${\tau }_{C_1{V}_1{F}_1}$ is modeled as a rectangle with width of $F_1=400$ MHz and a height of ${\tau }_{C_1{V}_1{F}_1}=95.35us$. Bin $V{B}_1$ corresponds to TAM Bus 1 of Figure 1a, and bin $V{B}_2$ corresponds to TAM Bus 2. Figure 2a illustrates the test schedule generated by the Greedy Rectangle Packing (GRP) method. The x-axis of each bin represents the ATE channel bandwidth, 400 MHz in this case, while the y-axis represents the total test time, which is 1462 µs.

In this test schedule, each test is applied using its maximum rated shift frequency, an intuitive and optimal choice for this simple SoC. However, in more complex cases, $GRP$ and $RP-SA$ can explore lower shift frequencies for individual tests to achieve better ATE channel bandwidth utilization, leading to more efficient test scheduling. This improvement is demonstrated in [4] and also in Section 6. Additionally, when the test process of Example 3 is re-evaluated using the $RP-SA$ method, a more optimized solution is obtained, as shown in Figure 2b (the total test time is 1412 us in this case), highlighting the advantages of this technique. However, this improvement comes at the cost of a 116-fold increase in computational time.

The work presented in [4] clearly demonstrates the significant advantages of the above-mentioned TDM-based scheduling methods over conventional approaches such as Shortest-Job-First (SJF) [12] and Session-Based Scheduling (SBS) [3]. Specifically, the SJF method, originally effective for single-$V_{dd}$ designs, was adapted for multi-$V_{dd}$ scenarios by incorporating relevant constraints and evaluated in both best-case (BC) and worst-case (WC) scenarios. The SBS method was explicitly developed for multi-$V_{dd}$ SoCs. Two industrial systems-on-chip, SoC-A and SoC-B, were used as benchmarks for this comparison. For SoC-A, the TDM-based methods consistently achieved substantial reductions in test times across various bus configurations, outperforming SJF-WC by up to 5.68, SJF-BC by up to 2.21, and SBS by up to 2.07. Likewise, for SoC-B, the TDM approaches again showed significant improvements, achieving near-optimal or optimal test schedules and outperforming SJF-WC by up to 9.94x, SJF-BC by up to 2.34x, and SBS by up to 2.27x. These results clearly illustrate that the TDM-based scheduling methodologies significantly enhance test-time efficiency through improved parallelization, better resource utilization, and effective handling of multi-voltage and frequency constraints compared with traditional scheduling methods. It should be noted that the above comparison includes an ILP-based TDM approach, which is not incorporated into the proposed toolkit due to scalability limitations. Instead, the toolkit utilizes the $RP-SA$ method, as it achieves near-optimal or optimal solutions matching those of the TDM-ILP approach but with substantially lower computational cost, making it significantly more practical for real-world applications.

To fully exploit the benefits of the TDM methodology for testing multi-$V_{dd}$ SoCs, the TAM architecture must be carefully designed to align with TDM’s requirements. To demonstrate the significant impact of TAM configuration on test scheduling efficiency when employing TDM, a case study was conducted on a virtual SoC comprising thirteen (13) cores distributed across three (3) voltage islands, each supporting up to three (3) voltage levels (further details are available in [6]). A total of 10,970 random TAM configurations were generated, all assuming the same total number of ATE channels. These configurations varied in terms of the number of buses, test data lines per bus (bus width), and core-to-bus assignments. The $GRP$ test scheduling method was applied to each configuration to minimize the overall test time.

The resulting test times ranged from 16K to 254K, with an average test time $\mu =61$K and a standard deviation $\sigma =57$K (1K = ${10}^3$). These results, illustrated in Figure 3a, highlight the substantial variation in test time depending on TAM configuration, underscoring the critical role of TAM design in achieving efficient test scheduling when employing TDM.

Identifying an optimal TAM configuration among the millions of possible alternatives is a computationally complex and challenging problem. To address this, a Branch-and-Bound TAM optimization method has been developed [5], specifically aimed at minimizing test time when TDM is employed for test scheduling. This technique exploits a computationally simple and accurate bounding criterion of TDM [5] to prune a vast number of suboptimal TAM configurations early in the search process, thereby significantly reducing computational effort. Furthermore, the fast $GRP$ test-scheduling approach is integrated to evaluate and select promising TAM configurations during the search.

The adoption of the $GRP$ is justified by its demonstrated high correlation with both the highly effective $RP-SA$ method [5] and the lower bound of each TAM configuration, as depicted in Figure 3b. This correlation ensures that the selected greedy evaluation method serves as a reliable and efficient means for assessing the quality of TAM configurations during the optimization process.

For very large SoCs, the complexity of the TAM optimization problem grows significantly. In such cases, exhaustively enumerating and evaluating all possible TAM configurations becomes impractical. However, the search space can often be significantly reduced by considering area and layout constraints. For instance, even if the TAM configuration yielding the minimum test time involves connecting two cores located at opposite corners of the die to the same TAM bus, the routing overhead associated with such a solution would likely render it impractical. Physical design constraints of this nature enable the early elimination of many infeasible TAM configurations, thereby reducing the complexity of the TAM optimization process.

A practical design approach for large SoCs is to partition the floorplan into M adjacent areas $A_1,A_2,\dots ,A_w$ based on design constraints and generate a separate TAM configuration for each one of them. Besides the low routing overhead, this approach also has the benefit of low TAM optimization complexity because (a) of the smaller problem instance that needs to be solved for each area and (b) the parallel nature of the problem where each area can be optimized independently of the other areas. The only question in this case is how to distribute the available tester channels among the M areas in order to minimize the test time for the whole SoC. In [5], one exact and one heuristic optimization method are presented for distributing the TAM lines to the various areas $A_i$ effectively.

3. Motivation for Toolkit

In contemporary semiconductor manufacturing, the testing process for Systems-on-Chip (SoCs) is predominantly governed by proprietary commercial tools. These tools offer robustness, extensive functionality, and high-quality results. However, they are also characterized by significant cost implications, proprietary encryption of intermediate data, and a lack of interfaces for custom extensions. Consequently, the validation and qualification of emerging methodologies and techniques become highly challenging, if not infeasible. As a result, despite their demonstrated efficacy, such tools are unsuitable as foundational platforms for exploratory research and the proof-of-concept validation of novel SoC test techniques and methodologies.

The primary motivation behind this work is to address these limitations and enhance the Technology Readiness Level (TRL) of the Time-Division Multiplexing (TDM)-based test scheduling methodology for multicore, multi-$V_{dd}$ SoCs with multiple voltage islands. The goal is to validate the technical feasibility of this methodology while increasing its investment readiness. To achieve this, a user-friendly and efficient integrated environment for creating, executing, and studying TDM-based test processes has been developed. This environment facilitates the definition of test processes through high-level language (HLL) descriptions, provides structured and accessible procedures for executing customized test processes, and incorporates advanced test scheduling and TAM optimization solvers capable of handling the inherent complexity of modern SoCs. Furthermore, it includes a sophisticated visualization tool that enables strategic analysis and optimized decision-making, offering a single-entry graphical interface for efficiently managing TDM-based test tasks.

The framework of the TDM Test Scheduling and TAM Optimization toolkit may constitute a significant effort towards standardizing the formulation of complex manufacturing test problems, particularly in the context of dynamic voltage and frequency scaling (DVFS)-based SoCs. The complexity of the test process increases with the number of cores in an SoC, the number of voltage levels and voltage islands, the structure of test access mechanisms (TAMs), and the power and thermal constraints imposed on the test procedure.

To the best of the author’s knowledge, the TDM Test Scheduling and TAM Optimization toolkit is the first freely available tool capable of handling TDM-based test planning for multicore, multi-$V_{dd}$ SoCs with voltage islands. Its development aims to inspire further advancements in free tools for manufacturing tests, encouraging their adoption by large research teams and organizations to improve the TRL of innovative test methodologies. In support of this objective, the presented toolkit follows a modular architecture, allowing for the seamless integration of alternative solvers.

The proposed toolkit holds immediate relevance to various user groups, classified as follows:

Professional Users

• Test engineers: The TDM Test Scheduling and TAM Optimization toolkit provides test engineers with access to cost-efficient TDM-based test scheduling methodologies within a user-friendly, integrated framework. Its tailored visualization capabilities facilitate informed decision-making throughout the test planning process.
• Researchers: The toolkit enables researchers to create artificial SoCs using intellectual property (IP) or benchmark cores, apply their methodologies, and compare outcomes against established solutions. Additionally, its visualization features aid in identifying potential issues, strengths, and weaknesses of newly developed methodologies.
• Instructors: The toolkit serves as an educational aid by providing an intuitive environment for students to define and solve test scheduling and TAM optimization problems that consider power and thermal constraints. The visualization tools further support the exploration and presentation of test scheduling results.

Institutes and Organizations

• Public and private research institutes: These entities can leverage the TDM Test Scheduling and TAM Optimization toolkit as an efficient computational framework for modeling complex test processes. The toolkit’s workbench supports the development of novel experiments, models, and methodologies.

Industrial Applications

• VLSI companies: The proposed toolkit offers value to VLSI companies by providing reusable modules for test planning. Its underlying software architecture ensures seamless integration into existing systems, facilitating potential commercialization as a CAD tool or its adaptation for alternative applications.

In conclusion, the TDM Test Scheduling and TAM Optimization toolkit, by providing an accessible, modular, and efficient framework, aims to bridge the gap between academic research and industrial application, fostering the continued evolution of test scheduling and TAM optimization methodologies in semiconductor design and manufacturing.

4. Description of Toolkit

The TDM Test Scheduling and TAM Optimization toolkit consists of six (6) distinct modules that can function independently or collaboratively to achieve its principal objective: the formulation and execution of an optimal test process for a multicore, multi-$V_{dd}$ SoC with multiple voltage islands. These modules include the $High$ $Level$ $Language$ ($HLL$), the $Editor$, the $Console$, the $Visualizer$, the $Graphical$ $User$ $Interface$ ($GUI$), and the $Library$.

The $HLL$ module provides a structured approach for recording technological attributes of intellectual property (IP) or benchmark cores embedded within a targeted SoC. These attributes include technology process, required area, supported voltage and frequency levels, test time per frequency per voltage, average dynamic power per frequency per voltage, static power per voltage, state retention requirements between tests, and wrapper parallel port (WPP) size. A specialized $factor$ parameter facilitates technology process shifts in core data, adjusting area, power, and test time. The textual representation of a core is stored in a designated $core$ $definition$ $file$ ($.cdf$). Additionally, $HLL$ employs $.ptrace$ files to define a core’s power consumption during testing at fixed time intervals, allowing dynamic substitution of average power values. While this enhances power-constrained test processes, it also increases computational overhead.

The $HLL$ module supports an efficient and comprehensible textual representation of the SoC architecture and the formulation of TDM-based test processes. It is assumed that SoCs allow for modular testing, wherein each embedded core is treated as a testable unit through the implementation of a core test wrapper, compliant with standards such as IEEE 1500 [13]. Through $HLL$, users can specify SoC-related parameters, including embedded cores, voltage island configurations, and supported voltage levels per island. Additionally, test process parameters such as the maximum scan-shift frequency supported by Automatic Test Equipment (ATE), supported frequency levels for TDM-based test processes, TAM description, and power constraints during testing can be defined. All these specifications are stored in an initialization file of type $.init2D$.

Given the core definition files and the initialization file of the test process, the toolkit automatically generates TDM-based test process description files, significantly streamlining workflow efficiency. Specifically, two output files are generated: a $TAM-data$ file ($.tam$) and a $SoC-data$ file ($.soc$). The $TAM-data$ file describes a proposed test access mechanism for the targeted SoC, balancing test load distribution across the available test buses. The $SoC-data$ file contains all the necessary information for testing the targeted SoC based on the proposed TAM. Since these files are formatted in $HLL$, users can modify them to evaluate alternative test strategies.

Given a $.soc$ file as input, the toolkit can generate an optimal TAM configuration tailored for testing the targeted SoC. This configuration is stored in a specialized file of type $.t2d$ within the $HLL$ framework. Users can combine such files with a $.soc$ file to automatically generate a new TDM-based test process aligned with the described TAM configuration.

Table 1. Comparison of HLL, STIL, and ATML.

Feature/Aspect	HLL	STIL	ATML
Standardization	Custom-defined (within proposed toolkit)	IEEE 1450	IEEE 1671 family
Primary Purpose	Test planning, TAM optimization, power-aware test process modeling	Test vector, timing, and waveform description	Metadata exchange for test systems
Target Use Case	TDM-based scheduling in multicore SoCs with DVFS and voltage islands	Post-ATPG pattern transfer to ATE	Interoperability in automatic test systems
Support for Modular Testing (e.g., IEEE 1500 cores)	Full and explicit support	Limited; focused on signal and pattern details	Limited; metadata-oriented rather than process definition
User-Friendliness and Readability	Highly readable and user-friendly	Complex and verbose, limited manual readability	Complex XML, primarily machine-readable
TAM/Test Scheduling Support	Fully supported	Not supported	Not supported
Power/Thermal Constraint Modeling	Supported	Not supported	Not supported
Customization and Extensibility	Highly extensible; designed for experimental research	Limited extensibility; standardized	Schema-based extensibility possible, but practically complex
Integration and Tool Support	Integrated within the proposed toolkit	Widely supported in commercial ATPG and ATE tools	Primarily supported by specialized military and aerospace tools
Ease of Use for Research	High; designed for fast prototyping, modification, and experimentation	Moderate to low; steep learning curve and tight industry coupling	Low; mostly used for documentation and logistics

presents a comparison between HLL, Standard Test Interface Language (STIL) [14], and Automatic Test Markup Language (ATML) [15], focusing on their purpose, structure, and suitability for SoC test process modeling and automation.

Overall, HLL is a research-oriented, high-level language specifically designed for power/thermal-aware test process modeling and TAM optimization in multicore SoCs. It prioritizes usability, flexibility, and integration with experimental solvers. STIL is a low-level, production-grade standard used primarily for describing test vectors, timing, and patterns. It is suited for post-ATPG and ATE interfacing but lacks expressiveness for architectural modeling or test planning. ATML, on the other hand, is not a test modeling language per se but rather a metadata and configuration framework used in complex automatic test systems, particularly in the aerospace and defense industries. While STIL and ATML are indispensable in production flows for pattern exchange and test logistics, HLL fills a unique gap by offering a lightweight, modular, and researcher-friendly approach to test planning, TAM design, and test process optimization.

The $Editor$ module offers advanced functionalities for processing files written in $HLL$ format. Supporting multiple tabs for concurrent file editing, it includes a comprehensive suite of text utilities [16]. This feature enables efficient management of test process data within the toolkit without requiring external applications. A notable feature of the $Editor$ is its smart $HLL$ code verification tool, which analyzes $HLL$ code for syntactical and logical errors, providing real-time feedback to optimize test process implementation.

The $Console$ module operates as a standalone console application that also interfaces with external tools. It is responsible for generating the following:

• Test processes using initialization or TAM configuration files.
• An optimized TAM configuration for a given SoC, incorporating or ignoring power constraints.
• A high-quality test schedule for a given test process, ensuring compliance with power constraints.
• Detailed reports on power and thermal effects across the SoC during testing.
• Log files documenting execution processes and results.

The $Console$ module accepts a configuration file as input, along with a verification flag. There are three types of configuration files within the $HLL$ framework, guiding the console application in creating a test process, optimizing TAM for a given SoC, or executing a test process. These files include paths to $HLL$ program files, solver parameters, power constraints, and external tool configurations, such as the $Hotspot$ thermal analysis tool [7]. Additionally, they define parameters affecting output data representation, such as time intervals, intermediate result derivation, and metric units. Configuration files can be automatically generated using the $GUI$ module or manually edited. In verification mode, a syntax analyzer scans input parameters, while a logical analyzer assesses interdependencies within the data, flagging errors or warnings in the console to prevent computational interruptions.

The $Console$ module integrates three main solvers: a Greedy solver and an SA-RP solver, each with specific advantages and limitations [4], along with a cluster-targeting solver for balancing tasks. The solvers in the toolkit incorporate novel solving enhancements, prioritizing large test loads and mitigating infinite loops in the rectangle packing process. The solvers consistently produce optimal results, even for highly variable test loads. Furthermore, the module interfaces with $Hotspot$ to estimate the thermal impact of generated test schedules. The $Console$ module automates $Hotspot$ configuration, input derivation, and execution, ensuring seamless integration of thermal analysis. A log file is generated for each solver execution, documenting solver actions and results.

The $Visualizer$ module is a user-friendly component that generates detailed and interactive graphical representations using the $Oxyplot$ library [17]. It comprises four submodules supporting the following:

• Visualization of test schedules, with optional annotations for power and thermal data.
• Visualization of power graphs at the SoC, voltage island, and core levels.
• Visualization of thermal graphs at the SoC, voltage island, and core levels.
• Visualization of the SoC floorplan, annotated with power and thermal data.

The $GUI$ module consolidates the toolkit’s functionalities into an integrated user interface. It consists of five submodules: $Configuration$, $Host$, $Guide$, $Utility$, and $Generator$. The $Configuration$ submodule enables users to define credentials, select and configure solvers, set test process parameters, and integrate the $Console$ and $Hotspot$ tools. The $Host$ module integrates the $Editor$, $Console$, and $Visualizer$ into a unified workspace. The $Guide$ module provides references to research materials on TDM-based test processes. The $Utility$ submodule supports user profile management, database functionality, remote notifications, and data encryption for security. The $Generator$ submodule automates the creation of $HLL$ program files for test processes.

Finally, the $Library$ module acts as the glue logic and the quiver of the TDM Test Scheduling and TAM Optimization toolkit, where every utility and solving function can be acquired.

Table 2. TDM Test Scheduling and TAM Optimization Toolkit against existing related toolkits.

Feature/Aspect	Proposed Toolkit	Existing Commercial Tools (E.g., Tessent (Siemens) [18], Synopsys DFTMAX [19])	Academic/Research Tools (E.g., ITC’02 Benchmark Suite [20], Fault [21]
Primary Objective	TDM-based test scheduling, optimized TAM configuration, and power/thermal-aware scheduling	General DfT and ATPG pattern generation; limited test scheduling optimization	Benchmarking, DfT, basic test scheduling, and TAM evaluation, typically not power/thermal-aware
Targeted SoC Complexity	Multicore, multi-$V_{dd}$, DVFS-enabled SoCs with multiple voltage islands	Yes	Mostly simplified models and standard benchmark circuits; limited multi-$V_{dd}$ support
Scheduling Algorithms Supported	Simulated annealing, heuristic (greedy), TDM-specific algorithms	Typically proprietary heuristic algorithms, not extensively customizable	Simple heuristics or manual scheduling; ILP in limited academic contexts
Support for Multi-voltage and Frequency Scaling (DVFS)	Explicitly designed for full support	Yes	Generally minimal or no direct support
Power and Thermal Constraints Integration	Explicit and detailed integration (via external tools like Hotspot)	Typically limited or indirect consideration (mostly power constraints)	Usually minimal or no direct power/thermal constraint modeling
Visualization and Analysis Capabilities	Comprehensive visualization (test schedules, power/thermal graphs, floorplans)	Limited visualization of test structures, primarily timing and scan-chain layouts	Minimal visualization; typically textual or basic graphical summaries
Extensibility and Customizability	Highly modular, supports experimentation with new algorithms, constraints, and interfaces	Limited extensibility; tools generally closed-source and proprietary	Moderate extensibility, sometimes open-source but not always easily customizable
User-Friendliness	High; HLL, integrated GUI, guided workflow, and automated generation	Moderate; often complex interfaces designed for professional engineers	Low to moderate; frequently command-line or basic interfaces
Availability and Cost	Freely available for academic and research use	Commercial licensing, high cost	Typically free or open-source, academic use primarily
Educational Applicability	High; designed explicitly for education, research, and industry-relevant experimentation	Low to moderate; steep learning curve, specialized training required	Moderate; designed primarily for benchmarking and basic academic research

presents a comparative analysis highlighting the added value and distinctive features of the TDM Test Scheduling and TAM Optimization Toolkit compared with existing toolkits and software frameworks commonly employed in the test scheduling and TAM optimization domain.

The proposed TDM Test Scheduling and TAM Optimization Toolkit is specifically designed to address the unique complexities associated with testing modern multicore, DVFS-based Systems-on-Chip (SoCs) featuring multiple voltage islands. In contrast to existing commercial tools such as Mentor Tessent and Synopsys DFTMAX, which primarily focus on general Design-for-Test (DfT) tasks and ATPG pattern generation, the TDM Toolkit explicitly integrates advanced optimization methodologies that consider power and thermal constraints. Additionally, commercial solutions are typically limited in their support for multi-voltage/frequency scaling and thermal-aware strategies, and their proprietary nature restricts customization and experimentation. Similarly, while academic and research tools like the ITC’02 Benchmarks and Fault provide valuable benchmarks, DfT, and basic validation capabilities, they typically lack comprehensive support for multi-voltage scenarios and direct integration of power- and thermal-aware optimization. Consequently, the proposed toolkit significantly advances the state-of-the-art by integrating TDM-based test scheduling methods, robust optimization strategies, extensive visualization capabilities, and a user-friendly, modular design. This makes it a highly valuable tool for both academic research and practical applications in industrial test environments.

5. Toolkit’s Workflows

The flowchart in Figure 4a delineates the sequential stages involved in generating a test process, including loading cores, initializing the SoC, creating a floorplan, and finalizing the test process. Specifically, the process begins with the user determining whether to load Intellectual Property (IP) cores or benchmark cores. If IP cores are selected, the user must load them from $.cdf$ files, with the option to select multiple files simultaneously. If benchmark cores are chosen, the flow proceeds without additional file input, as the corresponding $.cdf$ files are pre-embedded within the toolkit’s resources. Subsequently, the user must select a SoC initialization file, $.init2D$ file, to define the SoC architecture and form the test process. If a floorplan is required for the targeted SoC, the $HOTSPOT$ tool is employed to generate it. Finally, the test process is executed, producing the $.soc$ and $.tam$ files, thereby concluding the workflow.

The flowchart in Figure 4b illustrates the workflow for generating optimal test schedules within the TDM Test Scheduling and TAM Optimization Toolkit. The process begins with the user providing a $.soc$ file, which contains structural and functional data of the targeted System-on-Chip.

Following this, a decision is made regarding whether additional test scheduling specifications are required. If additional specifications are needed, they are incorporated into the workflow; otherwise, the process proceeds directly to the Test Access Mechanism (TAM) selection stage. At this stage, the user must select a $.tam$ file that defines the TAM configuration for the SoC. Subsequently, the test scheduling algorithm selection takes place. The user can choose between two distinct scheduling algorithms.

First, a Greedy Algorithm ($GRP$), a heuristic-based approach that efficiently schedules test processes while minimizing computational resource utilization. Second, a Simulated Annealing with Rectangle Packing ($RP-SA$) approach, an advanced optimization-based method designed to iteratively refine the test allocation for enhanced scheduling efficiency. Upon selecting the algorithm, the system processes the $.soc$ and $.tam$ files to generate an optimized test schedule. The outputs of this stage include a $.r2d$ file containing the generated test schedule and metadata files providing additional information related to the test schedule, including power consumption, thermal analysis results from HOTSPOT, execution time, and resource utilization.

At this point, the workflow concludes, marking the finalization of the test scheduling process. This methodology ensures an efficient, systematic, and scalable approach to test schedule generation, incorporating modularity and adaptability to accommodate diverse SoC architectures.

The flowchart in Figure 4c represents the workflow for the optimization of the TAM of a targeted SoC test process. It commences with the loading of SoC data via a $.soc$ file. At this stage, the system determines whether the given SoC is classified as a large-scale design. This distinction is crucial as it dictates subsequent steps related to SoC partitioning and $ATE$ channel allocation.

If the SoC is classified as large, the workflow proceeds with the implementation of the selected partitioning strategy. There are three distinct approaches:

• Simple SoC Partitioning: A fundamental approach where the SoC is divided into smaller units without incorporating additional constraints.
• Island- and Area-Based Partitioning: A more refined clustering technique that partitions the SoC based on a predefined number of voltage islands per partition, taking into account proximity constraints among islands to enhance overall test process efficiency.
• Island-, Area-, and Core-Based Partitioning: This approach clusters voltage islands to form partitions not only based on their number and proximity but also by considering the total number of cores per partition for computational reasons.

Once the partitioning takes place, the available $ATE$ channels are optimally allocated across each partition, following the methodology outlined in [5]. Let $N_i$ represent the number of ATE channels assigned to partition i. To ensure robust TAM optimization, the toolkit systematically evaluates configurations within the range [$N_i$− 0.25$N_i$, $N_i$ + 0.25$N_i$] for each partition i, allowing for adaptive resource distribution that may enhance test efficiency.

The toolkit employs the $Branch$ $and$ $Bound$ technique to optimize the TAM for each partition. The optimization process is repeated for every possible number of ATE channels within the specified range for each partition. Users can choose between two evaluation algorithms for TAM configurations that pass the bounding criterion, namely the computationally efficient $GRP$ and the computationally intensive $RP-SA$. At the end of this process, each partition is assigned a set of optimized TAM configurations. The toolkit then systematically explores all feasible sets of partition-level TAM configurations that satisfy the ATE constraint — i.e., the number of ATE channels used in each SoC’s partition in the set does not exceed the total number of ATE channels. Finally, it selects the most efficient set of partition-level TAM configurations, which is then used to derive the optimized test process for the entire SoC.

If the SoC is not classified as large, the workflow branches into three alternative TAM optimization techniques:

• Branch and bound optimization: a highly reliable and exhaustive search-based method that explores feasible TAM solutions using a bounding criterion to derive optimal TAM configurations (see Section 2).
• Test load balancing: a method focused on distributing core test loads efficiently across the available TAM resources, ensuring an even allocation. Users can specify an acceptable deviation among the test loads received per TAM bus, thereby influencing both the execution speed and quality of the final results.
• Heuristic: a computationally efficient alternative that applies the $Simulated$ $Annealing$ method to explore the solution space of TAM configurations, rapidly deriving an effective, though potentially suboptimal, TAM configuration.

Following the selection of the TAM optimization method, the toolkit produces two essential outputs: a $.t2d$ file encapsulating the generated optimal TAM structure and metadata files with statistical data about the optimization procedure. Finally, the proposed TAM configuration is used to create the optimized test process for the targeted SoC, and the workflow concludes.

6. Scenarios

6.1. Test Engineer’s Scenario

In a VLSI company, the SoC design department is developing a DVFS-based SoC with multiple voltage islands. Collaborating with the test planning department, they are evaluating various Design-for-Testability (DfT) strategies. Their analysis considers RTL implementation, area impact, and overall cost efficiency of the test process. The test planning department strongly advocates for testing the new SoC across multiple voltage levels and proposes a Time-Division Multiplexing (TDM)-based DfT approach. They argue that this solution has minimal area overhead and can reduce test time to nearly the levels of single-$V_{dd}$ testing.

A test engineer (TE) informs the team about a new, freely available toolkit—the $TDM$ Test Scheduler and TAM Optimization toolkit. After experimenting with it, the TE finds that it provides a user-friendly and efficient environment for making strategic decisions in TDM-based test processes. Both departments agree to further explore the feasibility of the TDM-based solution. Consequently, they assign the test engineer to evaluate the toolkit and present findings on its applicability to the new SoC. The test engineer requests information from the design department regarding the structure of the new SoC and its embedded cores. After receiving the necessary data, TE launches the toolkit on a workstation. Upon entering the required user credentials, the $GUI$ appears (Figure 5a), and TE navigates to the $Editor$ tab.

In the $Editor$, TE, using the $HLL$ language offered by the toolkit, writes the required programs that integrate various data sources, including SoC and core-related specifications, test data per core, and information related to the TDM-based test scheme. Examples of such programs are shown in Figure 6a,b. Next, TE selects the first menu button, C, to invoke the test generator, which automatically creates $HLL$ files specifying the test process. Sample output files are shown in Figure 6c,d. Figure 6c shows the program for the SoC TDM-based test process, and Figure 6d corresponds to the TAM program for the targeted SoC. The toolkit creates a dedicated folder to store the results of the test process. Upon reviewing the TAM program, TE notes that the test generator has automatically assigned embedded cores to the TAM buses. Consulting the manual of the toolkit, TE discovers that the tool employs a cluster-based technique that optimally balances the overall test load across the TAM buses.

TE carefully reviews the generated $HLL$ programs within the $Editor$ module. Due to their well-defined structure and the clear syntax of the $HLL$ language, these programs are easy to read, understand, and modify, enabling the TE to efficiently adjust them according to their department’s specific testing requirements. TE then chooses to perform syntactical and logical verification before proceeding to compile the $HLL$ programs via the R menu button. As shown in Figure 5b, the $Console$ displays messages indicating the status of the compiled $HLL$ programs, along with a prompt to visit the $Configuration$ tab. In response, TE selects a solver, configures its parameters, enables power constraints, and requests a thermal emulation of the test process (Figure 5a). Finally, TE executes the test process using the R menu button once again. Once the solver completes its task, the toolkit generates a notification.

TE opens the folder and examines the generated files. Among them is a file of type $.r2d$ containing the optimal test schedule for the SoC, along with files providing statistical, power, thermal, and logging information related to the test process. Next, TE selects the S menu button and clicks to visualize the generated test schedule. The toolkit activates the $Schedule$ tab, displaying the required graph, as shown in Figure 7a (Figure 7c for a larger SoC). TE then chooses to annotate the schedule with power (Figure 8a) and thermal data (Figure 8b) to analyze the impact of the derived test schedule on the SoC.

Next, TE seeks a clearer view of the power and thermal state of the voltage islands and embedded cores during the test process. Using the P menu button, TE first chooses to visualize the power consumption per voltage island. This activates the $Power$ tab, as shown in Figure 9a. To focus on a specific voltage island, TE deactivates the graphs for the others. Afterward, TE proceeds to visualize the power consumption per core. Again, TE selectively deactivates graphs for irrelevant cores and takes notes on the relevant ones (Figure 9b). Finally, to analyze temperature variations during the test process, TE uses the T menu button, which activates the $Thermal$ tab. This allows them to examine temperature fluctuations per island and per core, as depicted in Figure 9c,d.

To finalize the analysis, TE examines the impact of the test process from the SoC’s area perspective. TE knows that the toolkit provides an animated visualization where power consumption and temperature distribution across the SoC floorplan are represented using color gradients. To access this feature, TE selects the F menu button. First, the toolkit displays a static image of the SoC floorplan (Figure 10a). Next, it animates power consumption across each core during testing (Figure 10b), followed by an animation of temperature variations per core throughout the test process (Figure 10c). TE carefully observes the results, takes additional notes, and prepares to incorporate these findings into the final report.

Having thoroughly analyzed the test process, TE is nearly ready to finalize the report. However, TE seeks an alternative perspective in the test process by exploring the toolkit’s TAM optimization capabilities. To access this feature, TE selects the O menu button. TE then loads the previously defined program for the SoC’s TDM-based test process. The $Console$ displays messages indicating the status of the compiled $HLL$ program, along with a prompt to visit the $Configuration$ and $TAM$ tabs (Figure 11). In response, TE selects the branch-and-bound TAM optimization solver, configures the TAM and ATE parameters in the $TAM$ tab, and then, in the $Configuration$ tab, enables power constraints and requests a thermal emulation of the test process (Figure 5a). TE executes the TAM optimization process using the O menu button once again. The toolkit generates an optimized TAM configuration, and TE redefines the overall test process for the targeted SoC using the automated test process generation feature in the O menu. TE uses the toolkit to derive the test schedule for the optimized test process and observe a significant reduction in test time (approximately 50% for the virtual SoC, as shown in Figure 7b, and 32% for the large virtual SoC, as shown in Figure 7d). TE documents the results and finalizes the report accordingly. Before closing the toolkit, TE chooses to encrypt all input and output data in the folder for security purposes.

Finally, the test engineer presents the report, stressing the gained advantages from the followed procedure. Both heads of department finalize their decision to adopt the TDM-based test process. The test planning department is responsible for designing the TDM scheme and the TAM configuration of the targeted SoC. Meanwhile, the Test Engineer (TE) prepares the STIL-based test scripts according to the test scheduling data generated by the toolkit. To obtain accurate timing information for configuring the TDM clock divider, the TE activates the Shift Register Vector option available in the toolkit’s Configuration tab. Additionally, the TE plans to contact the toolkit’s developer to discuss potential collaboration for automating the generation of STIL-based test programs.

6.2. Researcher’s Scenario

A researcher (RES) aims to experiment with a novel test scheduling solver for SoCs. To do so, RES requires an artificial SoC as input, relevant test data, and a tool to visualize experimental results. RES learns about a free toolkit that generates artificial SoCs based on benchmark cores, complete with reliable test data and the corresponding floorplan.

After downloading the toolkit, RES quickly discovers that it can effortlessly generate artificial SoCs, along with their test data and floorplans, using the C menu button (Figure 5a). RES also finds that, with minimal modifications, it can replace the available solvers with an experimental one in the $Configuration$ tab (Figure 5a). Additionally, the toolkit provides built-in visualization tools for analyzing output results.

Recognizing this capability, RES considers comparing a novel solver against existing ones to validate its effectiveness and demonstrate its advantages.

6.3. Instructor’s Scenario

An instructor is preparing a lecture on manufacturing testing and seeks a well-structured, user-friendly tool to introduce and explain fundamental concepts, definitions, and parameters involved in test planning. The instructor learns about a free toolkit that provides such functionality.

After downloading and exploring the toolkit, the instructor finds it useful for both the lecture and an accompanying lab session. To enhance student understanding, the instructor decides to demonstrate an artificial test scheduling process using the toolkit’s integrated environment.

Additionally, the instructor considers assigning a lab exercise based on the toolkit, allowing students to gain hands-on experience with test scheduling and planning.

7. Conclusions

This work introduces the TDM Test Scheduler and TAM Optimization Toolkit, an integrated framework that fully supports TDM-based test processes for multicore, multi-$V_{dd}$ SoCs. The toolkit features a high-level language ($HLL$) and a verification tool, enabling a user-friendly and efficient representation of test processes. It incorporates powerful solvers and a comprehensive visualization environment, facilitating informed decision-making in test planning. The toolkit serves as a valuable testbed for both research on test methodologies and educational activities. It can generate test processes for artificial SoCs, leveraging well-known benchmark cores. Furthermore, its modular architecture allows researchers to integrate their own experimental solvers, utilizing the graphical user interface and $HLL$ to define and execute custom test processes. The results can then be visualized using the built-in graph tool.

Significant effort has been dedicated to developing a robust, integrated, well-structured, user-friendly, and computationally efficient environment capable of producing optimal test processes for multi-$V_{dd}$ SoCs. Test engineers and researchers are encouraged to propose or contribute new functionalities. The TDM Test Scheduler and TAM Optimization Toolkit is free software and is available at [6]. Related information is also available in [22].

Future work includes expanding the computational and visualization environment to effectively support test processes for 3D multi-$V_{dd}$ SoCs.