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Keywords = noise transfer function (NTF)

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15 pages, 2565 KB  
Tutorial
Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
by Zhaoyang Shen, Shiheng Yang and Jiaxin Liu
Chips 2024, 3(4), 296-310; https://doi.org/10.3390/chips3040015 - 1 Oct 2024
Viewed by 2755
Abstract
The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. [...] Read more.
The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC. Full article
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