Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers ^†

Abstract

This paper provides an analysis of existing single-digit binary adders from the point of view of their implementation on fans built based on metal-oxide-semiconductor field-effect transistor—MOSFETs. The synthesis of a single-digit adder with a conditional sum is carried out. The considered adders are compared in terms of speed and hardware complexity (by the number of MOSFETs). Adders perform arithmetic operations on numbers. In combination with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement several different operations; they are an integral part of different processors. The most important parameters of adders are their hardware complexity and performance; therefore, many options for single-bit and multi-bit connectors with serial, parallel and combined transmissions have been developed. In the final part, a scheme of a multi-bit adder with consecutive transfers on adders with a conditional sum is given. An example of performing addition operations is given.

1. Introduction

Adders perform arithmetic addition and subtraction of numbers. Together with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement a number of various operations (multiplication, division, etc.), which are an indispensable part of various processors.

Important parameters of adders are their hardware complexity and performance; therefore, many variants of single-bit and multi-bit adders with serial, parallel and combined transfers have been developed [1].

The listed adders are synthesized based on the truth table. The analytical expressions of the sum (S_i) and transfer functions C_i have the form:

$$\begin{gathered} \mathrm{S}\mathrm{i}=\overline{a_i}\overline{b_i}{C}_{i-1}\vee \overline{a_i}{b}_i\overline{C_{i-1}}\vee a_i\overline{b_i}\overline{C_{i-1}}\vee a_i{b}_i{C}_{i-1}; \\ {C}_i=a_i{b}_i\vee a_i{ C}_{i-1}\vee { b}_i{ C}_{i-1}, \end{gathered}$$

(1)

where $\overline{a_i}$ and $\overline{b_i}$ are the i-th digits of the numbers A and B; $C_{i-1}$—transfer from the junior category.

The formula can be reproduced on various sets of logic elements, such as AND-NOT, OR-NOT, “exclusive OR”, etc. At the same time, the hardware’s complexity and performance may be different.

2. Materials and Methods

The analysis of single-digit adders on elements is discussed below:

• two-stage logic AND-OR-NOT [1];
• two “exclusive OR” valves and OR-NOT and AND-NOT circuits [2];
• three-way valve “exclusive OR” and circuits AND-NOT;
• on valves “exclusive OR” and multiplexers, an adder with a conditional sum (conditional-sum addition_CSA) is implemented. Before determining the hardware complexity (the number of MOSFETs) and performance (the number of logic elements on which the signal is delayed), the circuits of the analyzed adders are depicted as logic gates on the MOSFET. Consider the analysis of an adder built on the basis of the two-stage logic AND-OR-NOT [1,3,4,5].

The circuit of such an adder is shown in Figure 1, and Figure 2 shows the circuit of this adder on the logic circuits of a MOSFET [6,7,8].

Figure 1. Functional diagram of the adder.

Figure 2. Logic circuit of the adder on a MOSFET.

The analytical formula of the analyzed adder has the form:

$$\begin{gathered} \mathrm{C}{\mathrm{i}}_{ }=(a_i{b}_i\vee a_i{C}_{i-1}\vee b_i{C}_{i-1}); \\ {\mathrm{S}}_{\mathrm{i}}=\overline{C_{i-1}}(a_i\vee b_i\vee C_{i-1})\vee a_i{b}_i{C}_{i-1}. \end{gathered}$$

(2)

Figure 1 shows the functional diagram of the adder constructed according to Formula (2).

Figure 2 shows its logic circuit on a MOSFET.

Figure 2 shows that the adder consists of six AND-NOT circuits with two inputs each. To implement them, 6 × 4 = 24 transistors will be required. It has nine circuits of NOT (2 × 9 = 18) transistors and a gate AND-NOT for 3 inputs (6 transistors), a gate OR-NOT for 3 inputs (6 transistors) and a gate OR-NOT for 4 inputs (8 transistors). In total, 62 MOSFETs will be required to implement the adder.

The time of formation of the transfer tci = 4 τ_le.

The time of formation of the sum Si = 7 τ_le.

The second single-digit adder [2,3,9], which is subject to analysis, refers to the following formula:

$$\begin{gathered} {\mathrm{S}}_{\mathrm{i}}=C_{i-1}\oplus a_i\oplus {b;}_i \\ {\mathrm{C}}_{\mathrm{i}}=\overline{a_i{b}_i} \overline{a_i{c}_{i-1}} \overline{b_i{c}_{i-1}}. \end{gathered}$$

(3)

The functional scheme of the C_i transfer is shown in Figure 3, which consists of three two-input and one three-input AND-NOT circuit. To implement them, we will need (4 × 3) + 6 = 18 transistors. The time of transfer formation t_ci = 2 τ_le.

Figure 3. Functional scheme of Ci transfer.

The S_i value in Formula (3) is calculated by adding modulo 2 (S_i¹ = a_i $\oplus$ b_i), then S_i = S_i¹ $\oplus$ C_i−1 is calculated (the first option). Figure 4 shows a functional scheme for calculating S_i based on two addition schemes modulo two.

$$\begin{gathered} {{\mathrm{S}}_{\mathrm{i}}}^1=\overline{a_i}{b}_i\vee a_i\overline{b_i}; \\ {\mathrm{S}}_{\mathrm{i}}=\overline{{ S}_i^1}{C}_{i-1}\vee S_i^1\overline{C_{i-1}}. \end{gathered}$$

(4)

Figure 4. Functional diagram of the S_i calculator based on two addition schemes modulo two.

Figure 4 shows that the implementation of S_i will require four inverters and six two-input AND-NOT circuits, which will require (4 × 2) + (6 × 4) = 30 transistors.

In total, to build an adder on two circuits modulo 2, we will need (18 + 32) = 50 transistors. The second adder can be built on the basis of an adder modulo two of three variables. In our case, a_i, b_i and C_i−1 come in as input variables. Then, the truth table for S_i has the form as shown in Table 1.

Table 1. The truth table for the sum of S_i.

Ci−1	ai	bi	Si
0	0	0	0
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	1

From this table we have:

$${{\mathrm{S}}_{\mathrm{i}}}_{ }=\overline{C_{i-1}}\overline{a_i}{b}_i\vee \overline{C_{i-1}}{a}_i\overline{b_i}\vee C_{i-1}\overline{a_i}\overline{b_i}\vee C_{i-1}{a}_i{b}_i.$$

(5)

To calculate S_i, the Formula (5) is transformed as follows:

$$\begin{gathered} {{\mathrm{S}}_{\mathrm{i}}}_{ }=\stackrel{̿}{\overline{C_{i-1}}\overline{a}{b}_i\vee \overline{C_{i-1}}{a}_i{\overline{b_i}}_i\vee C_{i-1}\overline{a_i}\overline{b_i}\vee C_{i-1}{a}_i{b}_i}= \\ \overline{\overline{\left(\overline{C_{i-1}}\overline{a_i}{b}_i\right)}\left(\overline{\overline{C_{i-1}}{a}_i\overline{b_i})}\right(\overline{C_{i-1}\overline{a_i}\overline{b_i})}(\overline{C_{i-1}{a}_i{b}_i)}}. \end{gathered}$$

(6)

The functional scheme for the sum of S_i constructed according to the Formula (6) is shown in Figure 5.

Figure 5. Functional diagram of the S_i calculator based on two addition schemes modulo two.

According to Figure 5, it is not difficult to calculate that 38 MOSFETs will be required for the implementation of the S_i adder.

According to Figure 3, to calculate C_i, 18 transistors will be required for a total of 56 transistors. For the formation of S_i, a delay on 3 logical elements will be required, i.e., tsi = 3 τ_le.

Recently, the construction of so-called conditional sum adders (conditional-sum addition_ CSA) has been vigorously discussed [10,11,12,13,14].

The adder with a conditional sum is also built according to the truth table. Table 2 shows a modified table of the truth of the adder.

Table 2. Modified adder truth table.

Ci−1	ai	bi	Si0	Si1	Ci0	Ci1
0	0	0	0	-	0	0
0	1	0	1	-	0	-
0	0	1	1	-	0	-
0	1	1	0	-	1	-
1	0	0	-	1	-	0
1	1	0	-	0	-	1
1	0	1	-	0	-	1
1	1	1	-	1	-	1

From the first part of Table 2, where C_i−1 = 0, we have

$${{\mathrm{S}}_{\mathrm{i}}}^0=\overline{a_i}{b}_i\vee a_i\overline{b_i};$$

(7)

$${{\mathrm{C}}_{\mathrm{i}}}^0=a_i{b}_i.$$

(8)

From the second part of Table 2, where C_i−1 = 0, we have

$${\mathrm{S}}_{\mathrm{i}1}=\overline{{\mathrm{a}}_{\mathrm{i}}}\overline{{\mathrm{b}}_{\mathrm{i}}}\vee {\mathrm{a}}_{\mathrm{i}}{\mathrm{b}}_{\mathrm{i}}.$$

(9)

$${\mathrm{C}}_{\mathrm{i}1}=\overline{{\mathrm{a}}_{\mathrm{i}}}{\mathrm{b}}_{\mathrm{i}}\vee {\mathrm{a}}_{\mathrm{i}}\overline{{\mathrm{b}}_{\mathrm{i}}}\vee {\mathrm{a}}_{\mathrm{i}}{\mathrm{b}}_{\mathrm{i}}={\mathrm{a}}_{\mathrm{i}}\vee {\mathrm{b}}_{\mathrm{i}}$$

(10)

From this table it is also easy to see that

$$\mathrm{Si}=\overline{{\mathrm{S}}_{\mathrm{i}}^0}$$

(11)

To construct the sum of S_i⁰ on the fans AND-NOT, OR-NOT and NOT, Formula (7) must be reduced to the form:

$${{\mathrm{S}}_{\mathrm{i}}}^0={(a}_i\vee b_i)\left(\overline{a_i{b}_i}\right)=\overline{\overline{{(a}_i\vee b_i)\left(\overline{a_i{b}_i}\right)}}=\overline{\left(\overline{a_i\vee b_i}\right)+\overline{\overline{{(a}_i\vee b_i)}}}$$

(12)

According to the Formulas (8), (10), (11) and (12) it is possible to put the functional sum of the adder on the conditional sum. At the same time, the functional circuit must be supplemented with multiplexers that are controlled by transferring from the lower digit to a selection of one of C_i⁰ and C_i¹ and one of S_i⁰ and S_i¹, forming a transfer to the next digit C_i and the value of the sum S_i.

Taking into account the above, the functional scheme of the adder has the form as the scheme shown in Figure 6.

Figure 6. Functional diagram of the conditional sum adder.

The adder consists of two circuits, OR-NOT₁ and AND-NOT₂, three inverters, INV₁, INV₂ and INV₃, and a MUX₁ and MUX₂ multiplexer. At the inputs of the circuits OR-NOT₁ and AND-NOT₂, are the i-th digits a_i and b_i of the numbers A and B. At the output of the valve AND-NOT₂, the sum of S_i⁰ is formed, which is fed to the input “0” of the MUX₁ multiplexer and to the input of the inverter INV₂, and at its output, the sum of S_i is formed, which enters the input “1” MUX₁ multiplexer. From the output of the inverter INV₁, transfer C_i⁰ = $\overline{\overline{{\mathrm{a}}_{\mathrm{i}}{\mathrm{b}}_{\mathrm{i}}}}={\mathrm{a}}_{\mathrm{i}}{\mathrm{b}}_{\mathrm{i}}$ enters the input “0” of the MUX₂ multiplexer. From the output of the inverter INV₃ transfer:

$${{\mathrm{C}}_{\mathrm{i}}}^1=\overline{\overline{a_i\vee b_i}}=a_i\vee b_i$$

(13)

It is fed to the input “1” of the MUX₂ multiplexer. The control inputs of the multiplexers are transferred from the lower-order C_i−1.

The adder works as follows. After the bits a_i and b_i are fed to the inputs of the gates OR-NOT₁ and AND-NOT₁, the value of S_i⁰ is formed at the output of the circuit OR-NOT₂, and the value of the sum S_i¹ is formed at the output of the inverter INV₂. At the same time, the transfer value C_i⁰ is formed at the output of the inverter INV₁ and the transfer value C_i¹ is formed at the output of the inverter INV₃.

After feeding the transfers C_i⁰ and C_i¹ and the sums S_i⁰ and S_i¹ at the input of the corresponding multiplexers by transferring C_i−1, which is fed to the control inputs of the multiplexers simultaneously, the value of the sum Si is formed at the output of the MUX₁ multiplexer and at the same time, the transfer C₁ is formed at the output of the MUX₂ multiplexer, which is fed to the inputs of the multiplexers of the next highest digit.

3. Result and Discussion

Figure 7 shows the functional diagram of the MUX₁ multiplexer on the MOSFET and the MUX₁ operation Table 3.

Figure 7. Functional diagram of MUX₁ multiplexer on the MOSFET.

Table 3. Modified adder truth table.

Ci−1	Si0	Si0	Si
0	0	1	0
0	1	0	1
1	0	1	1
1	1	0	1

Figure 8 shows the functional diagram of the MUX₂ multiplexer and its operation table (Figure 8).

Figure 8. MUX₂ multiplexer function diagram.

To build a CSA adder, an AND-NOT gate is required for two inputs (4 transistors), two OR-NOT gates for 2 inputs (2 × 4 = 8 transistors), 3 inverters INV₁/INV3 (3 × 2 = 6 transistors) and 2 multiplexers (2 × 6 = 12 transistors). Everything will be required for a total of 30 transistors (4 + 8 + 6 + 12 = 30 transistors). The S_i formation time is 4 τ_le and the delay time on multiplexers is 2 τ_le.

Table 4 shows an example of a truth table for MUX2, which is shown in Figure 8.

Table 4. MUX₂ multiplexer truth table.

Ci−1	ai	bi	Ci0	Ci1	Ci
0	0	0	0	0	0
0	0	1	0	1	0
0	1	0	0	1	0
0	1	1	1	1	1
1	0	0	0	0	0
1	0	1	0	1	1
1	1	0	0	1	1
1	1	1	1	1	1

The order of operation of the bit adder with a conditional sum is given in Table 5.

Table 5. The order of operation of the adder with a conditional sum.

№	Ci−1	ai	bi	Si0	Si1	Ci0	Ci1	Si	Ci
1	0	0	0	0	1	0	0	0	0
2	0	0	1	1	0	0	1	1	0
3	0	1	0	1	0	0	1	1	0
4	0	1	1	0	1	1	1	0	1
5	1	0	0	0	1	0	0	1	0
6	1	0	1	1	0	0	1	0	1
7	1	1	0	1	0	0	1	0	1
8	1	1	1	0	1	1	1	1	1

From Figure 8, it is not difficult to calculate the number of transistors. To form the transfers of C_i⁰ and C_i¹ and the sums of S_i⁰ and S_i¹, 18 transistors are required. To build two multiplexers, 12 transistors are required.

Total Vtr = 18 + 12 = 30 transistors.

(14)

The maximum delay time for the formation of S_i⁰ and S_i¹ = 4τ_le, the delay time on parallel functioning multiplexers is −2τ_l7. A summary table of the main parameters for the considered adders is given in Table 6.

Table 6. The order.

Adders	Number of Transistors (N)	Time of Transfer Formation	Multiplexer Delay	Time of Sum Formation on n-bit Adder
Adder on two-stage logic (CM-1)	62	4 τle	-	7 nτle
Adder on two schemes “Excluding OR” (CM-3)	50	2 τle	-	6 nτle
Adder on a three-input circuit “Excluding OR” (CM-3)	56	2 τle	-	3 nτle
Conditional sum adder (CSA) (CM-4)	30	2 τle	2 τle	4 τle + nτMUX

Table 6 shows that for the construction of a single-digit adder, the minimum number of transistors has an adder with a conditional sum. The same adder has a minimal delay in the formation of inter-bit transfers. An example of adding numbers to four-digit (N = 4) adders with a conditional sum is shown in Figure 9.

$$\begin{array}{l}\mathrm{Let}\hspace{1em}\mathrm{A} = {\mathrm{a}}_3{\mathrm{a}}_2{\mathrm{a}}_1 = 1\hspace{1em}1\hspace{1em}0\hspace{1em}{0}_2\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}+\\ \hspace{1em}\hspace{1em}\hspace{1em}\mathrm{B} = {\mathrm{b}}_3{\mathrm{b}}_2{\mathrm{b}}_1\hspace{1em} 0\hspace{1em}1\hspace{1em}0\hspace{1em}{1}_2\\ \hspace{1em}\hspace{1em}\hspace{1em}{\mathrm{C}}_0 = 1\hspace{1em}\hspace{1em}\underset{¯}{\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}{1}_2}\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} 1\hspace{1em}0\hspace{1em}0\hspace{1em}1\hspace{1em}{0}_2.\end{array}$$

(15)

Figure 9. Functional diagram of a multi–bit adder based on a single-bit conditional sum adder.

Using Table 3, let us consider the operation of adding numbers A and B:

  a₀ = 0   b₀ = 1   C₀ = 1.

According to the line 7  S₀⁰ = 1 S₀¹ = 0 and C₀⁰ = 0 C₀¹ = 1.

At the same time S₀ = 0 and C₁ = 1

1.

a₀ = 0   b₀ = 1   C₀ = 1

According to the line 7  S₀⁰ = 1 S₀¹ = 0 and C₀⁰ = 0 C₀¹ = 1

At the same time S₀ = 0 and C₁ = 1

2.

a₁ = 0   b₁ = 1   C₁ = 1

According to the line 5  S₁⁰ = 0 S₁¹ = 1 and C₁⁰ = 0 C₀¹ = 0

At the same time S₁ = 1 and C₂ = 0

3.

a₂ = 1   b₂ = 1   C₂ = 0

According to the line 4  S₂⁰ = 0 S₂¹ = 1 and C₂^p = 1 C₂¹ = 1

At the same time S₂ = 0 and C₂ = 1

4.

a₃ = 1   b₃ = 0   C₂ = 1

According to the line 7  S₃⁰ = 1 S₃¹ = 0 and C₃⁰ = 0 C₃¹ = 1

At the same time S₃ = 0 and C₄ = S₅ = 1

  S_A+B = 10010₂ = 18₁₀

For N bit adders, T_sm = T_sm = nτ_MUX + 4τ_l.7.

By τ_MUX = 2τ_l7

T_sm = (2n + 4)τ_l7.

(16)

4. Conclusions

This paper analyzes adders built on the basis of the two-stage logic AND-OR-NOT and on the two- and three-input “exclusive OR” circuits, synthesizing a conditional sum adder. The main parameters (the number of MOSFETs and the speed of adders) are determined. It is shown that from the point of view of the number of transistors and the time of formation of inter-bit transfers, the conditional sum adder is advantageous. The efficiency of the adder is shown by an example. The final part shows a functional diagram of a four-digit adder with consecutive transfers.