Inkjet Printing of a Gate Insulator: Towards Fully Printable Organic Field Effect Transistor

Abstract

In this work, a gate insulator poly (4-vinylphenol) (PVP) of an organic field effect transistor (OFET) was deposited using an inkjet printing technique, realized via a high printing resolution. Various parameters, including the molecular weight of PVP, printing direction, printing voltage, and drop frequency, were investigated to optimize OFET performance. Consequently, PVP with a smaller molecular weight of 11 k and a printing direction parallel to the channel, a printing voltage of 18 V, and a drop frequency of 10 kHz showed the best OFET performance. With a direct ink writing-printed organic semiconductor, this work paves the way for fully inkjet-printed OFETs.

1. Introduction

While numerous techniques have been applied to organic field effect transistor (OFET) fabrication, the most promising approach for leveraging the unique features of organic electronics is additive manufacturing technology. This is due to its solution-based nature and reduced process complexity compared to substrative manufacturing methods. Various additive manufacturing methods, such as transfer printing, gravure printing [1,2], offset printing [3], screen printing [4,5], and transfer printing [6], have been investigated. Among them, gravure printing is known for its good geometric and planarity accuracy. The ink is applied directly onto the engraved cylinder using a doctor blade and then transferred to the substrate during printing. The engraved cylinder can be precisely controlled, providing good geometric accuracy, and the blade ensures uniform ink deposition onto the substrate, leading to good planarity. However, a drawback is that gravure printing is not “programmable” as it requires a physical printing plate to be created for each design, making customization more costly and time-consuming, especially during testing stages.

In contrast, inkjet printing stands out as being highly programmable because it uses digital information to control the placement of ink droplets with good geometric accuracy. It also allows for thinner film thicknesses, which are conducive to achieving OFETs with lower operational voltages. Inkjet printing offers excellent printing resolution due to its droplet volume, which can reach the femtoliter range, reducing the destructive effect of solvents. In addition, inkjet printing features drop-on-demand direct patterning with a non-contact mode and is compatible with large-area flexible substrates, all of which are highly desirable for low-cost and high-throughput OFETs and other organic electronics [7]. Furthermore, inkjet printing can further lower the cost as patterns can be directly created by dropping ink onto the desired area without generating waste during the process. Moreover, the deposition during inkjet printing is not limited to a specific area since the layer-by-layer deposition process allows materials to be printed over a large area [7,8,9]. Therefore, inkjet printing emerges as a suitable technology for fabricating gate insulators.

For a gate insulator, several polymer insulator materials, including poly (4-vinylphenol) (PVP) [10], poly (vinyl alcohol) (PVA) [11], poly (methyl methacrylate) (PMMA) [12], and polystyrene (PS) [13], can be used as OFET dielectrics and have been extensively studied. Among these, PVP has garnered more attention due to its relatively high dielectric constant of about 4–5, low cost of processing technology, and the ability to cross-link with appropriate cross-linking agents [14]. In addition to the common benefits of polymer dielectrics, such as solution processability and good mechanical flexibility, cross-linked PVP also offers superior dielectric properties, including chemical resistance, low leakage current, low cross-linking temperature, and compatibility with a range of organic semiconductors [15,16].

Here, the gate insulator, PVP, was printed using the inkjet printing method in the bottom gate–bottom contact (BGBC) OFET configuration on rigid (glass) and flexible (polymer) substrates. The organic semiconductor was also additively manufactured via direct ink writing, while all of the electrodes (gate and source/drain) were thermally evaporated. To achieve the optimal performance of the printed OFETs, various printing parameters required optimization. This work discusses optimizing the printing process of the dielectric PVP. Different parameters, including ink formulation and printing conditions, were thoroughly investigated to obtain films with an acceptable leakage current.

2. Methods

In the first step, 25 mm × 25 mm glass or PET (polyethylene terephthalate) slides were cleaned in an ultrasonic bath with deionized (DI) water for 10 min, followed by acetone and IPA for 10 min, respectively. Then, a bilayer gate of chromium (Cr) and silver (Ag) was deposited on the substrate via thermal evaporation (Integrated Physical Vapor Deposition and Glovebox, Lesker Nano 36, Lesker, Pittsburgh, PA, USA) through a shadow mask with a thickness of 5 nm and 50 nm, respectively (Cr provides for good adhesion to substrates while Ag offers low electrical impedance).

The PVP was dissolved in propylene glycol monomethyl ether acetate (PGMEA) with a concentration of 60 mg/mL. Subsequently, the cross-linking reagent poly (melamine-co-formaldehyde) (PMF) was mixed into the solution at a mass ratio of 1:2 with PVP. The mixed solution was then used as an ink for the dielectric layer. PVP was deposited via inkjet printing (Fujifilm Dimatix DMP-2850, Fujifilm, Santa Clara, CA, USA) with the SAMBA cartridge, with a bed temperature of 45 °C and cartridge temperature of 35 °C, to a thickness of about 1.5 µm (printing produces a rough film with a great variation of the total thickness), as shown in Figure 1.

After dielectric deposition, the TIPS-pentacene/PS blend ink was extruded using direct ink writing (DIW Hyrel 3D, Hyrel, Norcross, GA, USA) onto a tilted (~5°) substrate, followed by covering it with a Petri dish to slow down solvent evaporation for up to 6 h [17]. Finally, gold (Au), which acted as the source and drain electrodes, was deposited via thermal evaporation through a shadow mask with a thickness of 50 nm, as displayed in Figure 1. The channel length and width were 100 µm and 0.7 mm, respectively.

All electrical performance was characterized using a semiconductor parameter analyzer (HP 4155A and HP 4156A, Hewlett and Packard, Palo Alto, CA, USA). The polarized optical microscopic images were obtained using an optical microscope (Zeiss axioscope 5, Zeiss, San Diego, CA, USA).

3. Results and Discussion

By controlling the molecular weight of the gate insulator, it is possible to adjust the electrical properties of the resulting device, such as charge carrier mobility and threshold voltage. This optimization capability allows us to tailor the device performance to meet specific application requirements, making materials with smaller molecular weights more versatile for OFET applications. Therefore, two different PVP molecular weights were investigated. It was observed that the leakage current of an OFET with a molecular weight of 11 k was over 10-fold smaller (~10⁻⁹ A) than that of an OFET with a molecular weight of 25 k (~10⁻⁸ A), as depicted in Figure 2a. This difference can be attributed to the better uniformity of the PVP layer with a lower molecular weight, as smaller molecules can pack more densely and form a smoother surface with fewer pinholes. This smoothness is essential to ensure consistent electrical characteristics of the active channel in the transistor, thereby improving the leakage current. Figure 2b further confirms that lower-molecular-weight PVP enhances charge transport within the semiconductor of OFET devices. This enhancement is due to reduced structural defects and improved molecular ordering in the low molecular weight polymer films, leading to improved charge carrier mobility and device performance.

The dielectric layer serves as the insulator between the gate and the semiconductor channel in OFETs. The quality of this insulating layer is crucial for minimizing leakage currents and ensuring effective modulation of charge carriers in the semiconductor and dielectric. Inkjet printing parameters, such as printing direction and printing voltage, play significant roles in gate insulator deposition for OFET, as they control thickness, surface roughness, and interface quality. Figure 3a displays the transfer curves of OFETs with different printing directions; “X” represents the direction parallel to the channel, while “Y” represents the direction perpendicular to the channel. Here, “1 × 1Y” indicates printing the pattern initially in the direction parallel to the channel, followed by printing in the perpendicular direction. It was observed that the device with the printed dielectric parallel to the channel exhibited the best electrical performance. This is attributed to reduced charge hopping across the boundaries between adjacent printed lines. Conversely, printing the dielectric perpendicular to the channel leads to greater non-uniformity of the printed pattern, resulting in the discontinuity of the semiconductor and the formation of charge traps at the dielectric and semiconductor interface, thereby reducing carrier mobility (channel length was 100 µm, drop space was 5 µm).

Figure 3b demonstrates OFETs with different printing voltages, indicating the optimum printing voltage of 18 V. In inkjet printing, higher voltages lead to better coverage and densification of the dielectric material, thereby improving insulation properties and enhancing device performance. However, increasing voltages can also promote the spreading and coalescence of droplets upon substrate contact, resulting in thicker films and, ultimately, a higher device operating voltage. This explains why the ON current increases when the print voltage is increased from 16 V to 18 V but decreases with further voltage increases.

Optimizing inkjet drop frequency parameters is crucial for achieving desired dielectric properties and ensuring high-performance OFET devices. The drop frequency represents the rate at which ink droplets are ejected from the printhead during inkjet printing, which can influence the morphology of the deposited dielectric layer and impact the deposition rate of the dielectric material onto the substrate. As shown in Figure 4, the electrical performance of the OFET improves as the droplet frequency increases from 5 kHz to 10 kHz. This improvement is attributed to higher droplet frequencies, typically resulting in smaller droplet sizes and shorter distances between droplets, leading to denser packing and better coverage of the printed dielectric film. However, when the drop frequency is further increased, the ON current starts to decrease. This can be explained by observing that higher drop frequencies result in more ink droplets being deposited per unit time, potentially leading to thicker dielectric layers. Additionally, higher frequency implies a fast deposition rate, which can cause droplets to merge before fully spreading. This can result in a rough surface or the formation of defects in the film.

4. Conclusions

The current integration of electronics and structures relies on separately fabricated electronics and structures that are integrated at a later assembly stage. Additive manufacturing has revolutionized prototyping and the customization of fabricated structures. Similarly, organic electronics offer low-cost, large-area, and customizable fabrication realized via additive printing technologies. Our goal is to combine additive manufacturing of structures with additively fabricated electronics to realize a new generation of co-designed robotic meta-materials with embedded sensing, actuation, and electronic cognition.

In order to optimize the performance of a printed OFET, the printed materials and inkjet printing parameters, such as the printing direction, printing voltage, and drop frequency, were investigated. Consequently, the smaller molecular weight of the dielectric and printing parallel to the channel, with a printing voltage of 18 V and drop frequency of 10 kHz, showed the best OFET performance. This work paves the way for future all-printed OFETs towards the integration of printed electronics and printed structures.