FPGA Implementation and Performance Evaluation of Classic PID, IMC and DTC for BLDC Motor Control

Abstract

Brushless DC (BLDC) motors are widely used in mobile robotics and off-road vehicles due to their high efficiency, reliability, and compactness. However, achieving robust, high-performance speed control in embedded environments remains challenging due to nonlinearities, dead-time effects, parameter uncertainties, and strict real-time constraints. This paper presents a comprehensive experimental study of classical and robust control strategies for BLDC motor speed control, fully implemented on an FPGA platform. Classical PI and PID controllers tuned using Ziegler–Nichols, Cohen–Coon, and Chien–Hrones–Reswick methods are first investigated and discretized using both Zero-Order Hold (ZOH) and Tustin (bilinear) approximations. Model-based approaches, including IMC-based PID controllers, are then introduced to enhance robustness. In addition, a robust two-degree-of-freedom dead-time compensator (DTC) is implemented to explicitly address dead-time uncertainties inherent to inverter-based motor drives. All controllers are implemented using fixed-point arithmetic on a Xilinx Nexys A7 FPGA and validated experimentally on a BLDC motor test bench representative of semi-autonomous robotic applications. Performance is evaluated through time-domain responses and quantitative indices, including ISE, ITAE, I, control effort, and FPGA resource utilization. Experimental tests under controlled DC bus voltage disturbances are conducted to assess disturbance rejection capability and robustness under realistic operating conditions. Experimental results demonstrate that Tustin discretization consistently improves tracking performance, while IMC-PID and DTC strategies provide superior robustness against dead-time and modeling uncertainties, making them particularly suitable for embedded FPGA-based motor control.

1. Introduction

The digital and energy transition is accelerating automation in key sectors such as transportation, healthcare, and agriculture. At the heart of these systems, electric motors play a fundamental role by converting electrical energy into mechanical energy to perform functions such as traction, motion, or positioning. Owing to their high efficiency, power density, and modularity, electric motors have become the most widespread energy conversion machines worldwide, with efficiencies exceeding 95% [1,2]. Their deployment contributes significantly to the reduction in greenhouse gas emissions, while improving the execution of repetitive or labor-intensive tasks in fields such as robotics, automotive systems, and agriculture [2,3,4]. These applications require actuators with high and repeatable performance, including fast torque response, satisfactory speed and position accuracy, and low torque ripple [5,6].

Among the different types of electric motors, brushed DC motors and brushless DC (BLDC) motors are widely used in electromechanical systems. Brushed DC motors are characterized by their simple design and low cost; however, they suffer from mechanical wear due to brushes and commutators, which limits their lifetime and requires regular maintenance. In contrast, BLDC motors rely on electronic commutation ensured by a power converter and a dedicated controller, eliminating mechanical contacts. As a result, BLDC motors offer higher reliability, extended lifetime, greater power density, and improved efficiency. These characteristics make BLDC motors particularly suitable for embedded and mobile applications subject to strict energy, reliability, and compactness constraints, such as mobile robots, drones, and electric transportation systems.

In this context, this work focuses exclusively on the control of BLDC motors due to their growing relevance in modern robotic and embedded systems. As dynamic actuators subjected to variable loads, external disturbances, and energy and safety constraints, BLDC motors require efficient control strategies to ensure motion accuracy and stability, energy optimization, and overall system robustness [7].

However, achieving high, repeatable performance is challenged by several factors, including nonlinearities (saturation and friction), parametric variations, measurement noise, computation and sampling delays, and load uncertainties. Among these limitations, dead time resulting from physical phenomena, sensors, power converters, and digital processing is one of the most detrimental factors affecting dynamic performance and control system stability.

Numerous control approaches have been proposed in the literature to address these challenges. Proportional–integral (PI) and proportional–integral–derivative (PID) controllers remain industrial benchmarks due to their simplicity, ease of implementation, and compatibility with real-time constraints, although their performance strongly depends on the tuning method employed (Ziegler–Nichols, Cohen–Coon, and Chien–Hrones–Reswick). Model-based approaches, such as Internal Model Control (IMC), have also been introduced to explicitly enhance robustness against parametric uncertainties and disturbances.

For dead-time compensation, specific strategies have been developed. Among them, the robust dead-time compensator (DTC), notably proposed by Normey-Rico, stands out for its ability to maintain satisfactory performance in the presence of dead-time estimation errors. Unlike ideal compensators that require precise knowledge of the delay, the DTC provides a robust formulation that guarantees stability and acceptable performance across a range of delay uncertainties.

In this work, we present an experimental study of the control of a BLDC motor implemented on an FPGA platform, with particular emphasis on control strategies compatible with embedded computational constraints and real-time requirements. Specifically, we propose FPGA implementations of classical PI/PID controllers, IMC-based PI/PID controllers, and a control architecture integrating a robust dead-time compensator (DTC). All control strategies are implemented using fixed-point arithmetic and include the quantization effects, saturation, PWM generation, and digital delays.

The performance of the different strategies is evaluated under a unified experimental protocol including reference variations and operating conditions representative of embedded applications. The comparison is based on relevant performance indicators for mobile and real-time systems, such as response time, tracking error, stability, energy efficiency, and embedded computation cost in terms of FPGA resource utilization [7,8]. The novelty and main contributions of this paper are summarized as follows:

• a detailed methodology for real-time FPGA implementation, using fixed-point arithmetic, of a classical PI and PID, IMC-based PID and robust two-degree-of-freedom dead-time compensator (DTC–2DOF) for BLDC motor speed control;
• an in-depth experimental comparison of classical PI, PID, IMC-based PID, and robust DTC strategies under identical hardware conditions, with particular attention to the impact of discretization methods (Zero-Order Hold versus bilinear Tustin method) on control performance and robustness;
• a quantitative analysis of FPGA resource utilization associated with the different control strategies and discretization methods, highlighting the trade-off between control performance and embedded computational cost;
• a comprehensive experimental validation on a realistic BLDC motor test bench representative of low-speed traction and embedded robotic applications, explicitly accounting for digital delays, quantization effects, and hardware constraints;
• an experimental robustness assessment under controlled DC bus voltage disturbances, enabling a comparative evaluation of disturbance rejection capability and robustness–performance trade-offs among the proposed control strategies.

2. Traction for Semi-Autonomous Robots and Off-Road Vehicles

Semi-autonomous robots and off-road vehicles are often characterized by low speed and low power; these vehicles typically use electric traction systems based on PMDC or BLDC motors. The use of DC or BLDC motors mainly depends on power and expected frequency of use, with BLDC preferred for more intensive use and higher power. The main advantages of BLDC motors are their efficiency and reliability, which ultimately offer economic benefits [9,10].

2.1. BLDC Motors

The BLDC motor family can be classified according to two complementary dimensions: the electromagnetic topology and the back-EMF shape, the latter defining the control strategy.

2.1.1. Electromagnetic Topologies

Electromagnetic topology characterizes the physical arrangement of the three key components, the configuration of the stator windings, the arrangement of the magnets on the rotor [10,11,12], and the structure of the magnetic circuit [13], which ensures their interaction, thus determining the organization of the poles and phases.

The stator windings are the active heart of the BLDC motor. Their configuration determines the shape of the rotating magnetic field, the torque and speed, the Joule losses and efficiency, and the harmonics and magnetic noise. Therefore, it describes how the windings are arranged in the stator slots, how they are distributed across the phases, and with what connections [10]. It also conditions the shape of the back-EMF, the torque ripple, the copper efficiency, the noise/vibrations, and even the control requirements (six-step or FOC).

The arrangement of the magnets on the rotor conditions the shape of the back-EMF, the torque and the field-weakening range; therefore, it directly influences their performance, their magnetic behavior and their application domain. The most common configuration, called “Surface-Mounted Magnets” (SPMs), has the magnets directly glued onto the rotor periphery; next is the “Interior Permanent Magnet” (IPM) configuration, where the magnets are inserted into internal cavities of the iron rotor; and finally, the “V-shaped magnet” configuration represents an optimized variant of IPM, where the magnets are arranged at an angle forming a V.

The magnetic circuit brings together a laminated stator (teeth/slots and yoke) and a magnetized rotor, separated by a regular air gap, which conditions torque density, noise and tolerances. Two main magnetic circuit architectures are distinguished: The radial topology, the most widespread, where the flux circulates radially between a central rotor and an external stator. The axial topology (or axial flux), where the flux circulates parallel to the axis of rotation [10].

2.1.2. Back-EMF Shape

The second dimension concerns the shape of the back-EMF. It characterizes the waveform of the voltage induced in the stator windings during rotor rotation; it also determines the control strategy and performance. Two main categories are identified: trapezoidal back-EMF or sinusoidal back-EMF. The trapezoidal shape is optimized for a control method called “six-step” or 60° conduction by injecting rectangular currents into two of the three phases simultaneously using 120° Hall effect sensors for position detection [14,15,16]. Field-Oriented Control is suitable for motors with a sinusoidal back-EMF [17]. It relies on transforming three-phase currents into Park coordinates (d-q) and generating sinusoidal currents via PWM modulation.

2.2. Process Modeling and Control

Control consists of applying a set of control laws (PI regulators, decision logic, and compensators) that allow the system to track a reference while rejecting disturbances, even when operating conditions vary within certain limits. A major difficulty arises when the system parameters are not accurately known: some processes have a complete and precise model, while others exhibit partial or even total uncertainty about their internal dynamics.

In this context, two fundamental approaches enable robust, high-performance control: the Internal Model Principle [18,19] and robust control design [20]. The Internal Model Principle states that the controller must contain an internal representation of the dynamics of the signals to be tracked (reference) or rejected (disturbances). When the internal model is employed, the controller can guarantee zero steady-state error, provided that the real system does not deviate excessively from the nominal model. In contrast, robust control aims to ensure stability and acceptable performance even under structural uncertainties, parameter variations, or significant disturbances.

For complex electromechanical systems or industrial processes with substantial uncertainty, obtaining an accurate model can be difficult. A practical approach consists in performing open-loop tests to derive a simple approximate model, which is then used for control design and tuning. Step-response experiments typically lead to standard approximate models such as the first-order plus dead time (FOPTD), Integrating Process with Dead Time (IPDT), or Second-Order Plus Dead Time (SOPTD) [21].

To obtain an initial estimation of the system dynamics, a step input is applied. The input is defined as follows:

$$u\left(t\right)=U_{0}H\left(t\right),$$

(1)

where $U_0$ is the step amplitude and $H\left(t\right)$ is the Heaviside function. Observing the output allows identification of the static gain, time delay, time constant, and overall dynamics speed.

In the simplest case, the system can be represented by a first-order model:

$$G_m\left(s\right)={\displaystyle \frac{K}{\tau s+1}},$$

(2)

whose step response is

$$y\left(t\right)=U_{0}K\left(1-e^{-t/\tau }\right).$$

(3)

The time constant $\tau$ characterizes the speed of the dynamics, while the static gain K corresponds to the final steady-state value:

$$y(\infty )=U_{0}K.$$

(4)

If the system exhibits a pure delay, a common phenomenon due to transport delays, actuator delays, or internal processing time, the model becomes

$$G\left(s\right)={\displaystyle \frac{K}{\tau s+1}}{e}^{-Ls},$$

(5)

Meanwhile dead time L represents the time interval between the application of the step input and the beginning of a significant response of the system. This representation has the following time-domain response:

$$y\left(t\right)=\left\{\begin{array}{cc}0,\hfill & t<L,\hfill \\ U_{0}K\left(1-e^{-(t-L)/\tau }\right),\hfill & t\ge L.\hfill \end{array}\right.$$

(6)

These approximate models, obtained from the step response, form a fundamental basis for controller synthesis, tuning, and stability analysis in many automation and process control applications [21].

3. Control Methods

3.1. Classical PID Controller Tuning Approaches

PID controller tuning methods aim to systematically determine the proportional, integral, and derivative gains in order to achieve a satisfactory compromise between response speed, accuracy, and robustness. Historically, empirical approaches such as those proposed by Ziegler–Nichols [22], Chien–Hrones–Reswick (CHR) [23], and Cohen–Coon [24] have relied on the process step response or the ultimate frequency to provide simple formulas for computing the PID controller parameters.

Two classical PID controller formulations are widely used in the literature: the independent and the dependent forms.

The independent form is expressed as

$$G_{PID}\left(s\right)=k_p+k_i{\displaystyle \frac{1}{s}}+k_{d}s,$$

(7)

where $k_p$, $k_i$, and $k_d$ denote the proportional, integral, and derivative gains, respectively.

The dependent (or ideal) form of the PID controller is defined as

$$G_{PID}\left(s\right)=k_c\left(1+{\displaystyle \frac{1}{t_{i}s}}+t_{d}s\right),$$

(8)

where $k_c$ is the proportional gain and $t_i$ and $t_d$ are the integral and derivative time constants.

The conversion between the two forms is given by

$$k_c=k_p,t_i={\displaystyle \frac{k_p}{k_i}},t_d={\displaystyle \frac{k_d}{k_p}},$$

which allows either formulation to be used depending on synthesis or implementation requirements.

In practical implementations, the ideal derivative action is rarely used due to its high sensitivity to measurement noise. To overcome this limitation, a first-order low-pass filter is commonly applied to the derivative term, leading to the so-called filtered PID controller formulation.

In its independent form, the filtered PID controller is expressed as

$$G_{PID}\left(s\right)=k_p+{\displaystyle \frac{k_i}{s}}+k_d{\displaystyle \frac{Ns}{1+Ns}},$$

(9)

where N denotes the derivative filter coefficient, which defines the cutoff frequency of the filter.

In its dependent form, the filtered PID controller can be written as

$$G_{PID}\left(s\right)=k_c\left(1+{\displaystyle \frac{1}{t_{i}s}}+t_d{\displaystyle \frac{Ns}{1+Ns}}\right),$$

(10)

where $k_c$ is the proportional gain and $t_i$ and $t_d$ are the integral and derivative time constants, respectively.

The introduction of the derivative filter significantly reduces the amplification of high-frequency measurement noise while preserving the benefits of derivative action. This structure corresponds to the standard PID formulation adopted in industrial control systems and is particularly well suited for real-time digital and FPGA-based implementations.

3.1.1. Ziegler–Nichols Method

The Ziegler–Nichols tuning rules are based on the step response [22]. The rules lead to the following expressions defined respectively by (11) and (12) for PI and PID forms.

$$k_c={\displaystyle \frac{0.9\tau }{KL}},t_i={\displaystyle \frac{L}{0.3}},$$

(11)

$$k_c={\displaystyle \frac{1.2\tau }{KL}},t_i=2L,t_d={\displaystyle \frac{L}{2}}.$$

(12)

3.1.2. Chien–Hrones–Reswick (CHR) Method

The Chien—Hrones—Reswick method provides two sets of tuning parameters depending on the desired overshoot [23]. The gains for a 20% overshoot response for PI and PID are computed using (13) and (14) respectively.

$$k_p={\displaystyle \frac{0.6\tau }{KL}},k_i={\displaystyle \frac{0.6}{KL}},$$

(13)

$$k_p={\displaystyle \frac{0.95\tau }{KL}},k_i={\displaystyle \frac{0.7}{KL}},k_d=0.45{\displaystyle \frac{\tau }{KL}}.$$

(14)

When reduced overshoot is required, the gains for the PI and PID can be obtained using (15) and (16) respectively.

$$k_p={\displaystyle \frac{0.35\tau }{KL}},k_i={\displaystyle \frac{0.30}{KL}},$$

(15)

$$k_p={\displaystyle \frac{0.6\tau }{KL}},k_i={\displaystyle \frac{0.6}{KL}},k_d=0.3{\displaystyle \frac{\tau }{KL}}.$$

(16)

The Chien—Hrones—Reswick rules provide gains corresponding to the independent form of the PID controller.

3.1.3. Cohen–Coon Method

The Cohen–Coon method is particularly effective when the dead time L is small compared to the process time constant $\tau$ [24]. The gains for the PI and PID can be obtained using (17) and (18) respectively.

$$k_c={\displaystyle \frac{\tau }{KL}}\left(0.9+{\displaystyle \frac{L}{12\tau }}\right),t_i={\displaystyle \frac{L\left(30+\frac{3L}{\tau }\right)}{9+\frac{20L}{\tau }}},$$

(17)

$$k_c={\displaystyle \frac{\tau }{KL}}\left({\displaystyle \frac{4}{3}}+{\displaystyle \frac{L}{4\tau }}\right),t_i={\displaystyle \frac{L\left(32+\frac{6L}{\tau }\right)}{13+\frac{8L}{\tau }}},t_d={\displaystyle \frac{4L}{11+\frac{2L}{\tau }}},$$

(18)

The Cohen–Coon formulas are directly adapted to the dependent form of the PID controller defined by (8). When the dead time becomes significant ($L>\tau /2$), a PI controller generally provides improved robustness and performance.

3.2. IMC-Based Control Methods

Over the past decades, numerous robust control methods have been developed to improve the stability and performance of systems subject to model uncertainties or external disturbances. One of the earliest and most influential contributions is the Smith Predictor, introduced in 1959 [25], whose objective is to explicitly compensate the effect of time delay in control systems. This approach forms the foundation of a family of modern strategies for handling processes with significant dead time. The dead-time compensator (DTC) was introduced to specifically address systems with large input-to-output delays, which are common in industrial processes [21,26].

The evolution of these methods has also led to improvements of the classical PID controller, resulting in the formulation of IMC–PID, which combines the practical simplicity of PID control with the robustness features of IMC. This approach provides good transient performance while maintaining strong robustness against model variations [27,28].

3.2.1. Robust Two-Degree-of-Freedom Dead-Time Compensator (DTC–2DOF)

The DTC–2DOF, proposed by Normey-Rico in 2002 [29], is a robust extension of classical dead-time compensation techniques such as the Smith Predictor [30]. Unlike the standard Smith Predictor, which is highly sensitive to model inaccuracies, the DTC–2DOF is explicitly designed to guarantee stability and performance even in the presence of model uncertainties [29].

The block diagram of the DTC–2DOF structure is shown in Figure 1.

This structure includes two compensators: a robustness-enhancing filter $F\left(s\right)$ and a PI regulator $C\left(s\right)$ responsible for the main control action. The filter is defined as

$$F\left(s\right)={\displaystyle \frac{T_{0}s+1}{T_{1}s+1}},$$

(19)

and the PI compensator as

$$C\left(s\right)={\displaystyle \frac{\tau }{K{T}_0}}\left(1+{\displaystyle \frac{1}{\tau s}}\right).$$

(20)

The parameters $T_0$, $T_1$, $D_m$, and $T_e$ determine stability, robustness, and closed-loop speed. Their roles are summarized in

Table 1. Role and tuning guidelines of the DTC–2DOF parameters.

Parameter	Description and Tuning Guidelines
$T_0$	Adjusts the delay margin $D_m$ to ensure stability and influence overshoot in the closed-loop response.
	Recommended values:
	$T_0=1.54D_m$ for robust performance;
	$T_0=0.69D_m$ for robust stability.
$T_1$	Defines the time constant of the filter $F\left(s\right)$, with $T_1=T_e+2D_m$. Proper tuning of $T_1$ helps control overshoot.
$T_e$	Equivalent closed-loop time constant. It can be chosen as a fraction of the open-loop time constant ${\displaystyle \frac{\tau }{\sigma }}$ or ${\displaystyle \frac{(\tau +L)}{\sigma }}$, with $\sigma >1$. The latter is preferred when the delay L is significant.
$D_m$	Delay margin estimated from the delay uncertainty: $D_m=\mathrm{\Delta }{L}_m$, where $L_m$ represents the estimated delay error.

.

3.2.2. Internal Model Control-Based PID Design (IMC–PID)

The first IMC–PID structure was proposed by Garcia and Morari in 1982 [19]. It establishes a direct correspondence between IMC parameters and the equivalent PID controller, facilitating practical implementation while preserving the robustness properties inherent to IMC. Several enhancements have since been proposed to improve performance and widen the applicability of IMC–PID. The study by Shamsuzzoha and Lee (2012) introduced an improved IMC–PID design offering better performance than previous methods, particularly for systems approximated by a first-order plus dead time (FOPTD) model [27].

The tuning equations of the improved IMC–PID controller are defined by (21)–(23).

$$K_c={\displaystyle \frac{t_i}{K(3{\tau }_c-2\beta +L)}},$$

(21)

$$t_i=\tau +2\beta -{\displaystyle \frac{3{\tau }_c^2-\frac{L^2}{2}+2\beta L-{\beta }^2}{3{\tau }_c-2\beta +L}},$$

(22)

$$t_d={\displaystyle \frac{2\tau \beta +{\beta }^2-\frac{{\tau }_c^3+\frac{L^3}{6}-\beta L^2+{\beta }^{2}L}{3{\tau }_c-2\beta +L}}{t_i}}-{\displaystyle \frac{3{\tau }_c^2-\frac{L^2}{2}+2\beta L-{\beta }^2}{3{\tau }_c-2\beta +L}},$$

(23)

with

$$\beta =\tau {\left[1-{\left(1-{\displaystyle \frac{{\tau }_c}{\tau }}\right)}^3{e}^{-{\displaystyle \frac{L}{\tau }}}\right]}^{1/2}.$$

(24)

The controller time constant ${\tau }_c$ modulates closed-loop speed and is the primary tuning parameter in IMC–PID design. It is typically chosen as

$${\tau }_c={\displaystyle \frac{\tau }{\lambda }},$$

(25)

with $\lambda$ ranging between 1 and 3 to provide a satisfactory compromise between fast response and robustness.

When the delay L becomes significant (comparable to or greater than $\tau$), it is preferable to define the controller time constant as

$${\tau }_c={\displaystyle \frac{\tau +L}{\lambda }},$$

(26)

which properly accounts for the influence of the dead time on the IMC–PID controller design.

4. Controller Discretization Methods

However, the control of the systems considered in this work is implemented on an FPGA, that is, in discrete time. Therefore, the continuous PID controllers must be converted into digital PID controllers. This is achieved using discretization methods, among which the most common are the Zero-Order Hold (ZOH) method and the Tustin (bilinear) method.

In continuous time, a signal is described as a function of time $u\left(t\right)$, whereas in discrete time the controller operates only on sampled values. A sampling period $T_s$ is thus introduced. The sampling instants are defined as

$$t_k=k{T}_s,k=0,1,2,\dots$$

(27)

and the corresponding discrete-time signal is written as

$$u\left[k\right]=u\left(t_k\right)=u\left(k{T}_s\right).$$

(28)

4.1. Zero-Order Hold (ZOH) Discretization

As previously mentioned, the Zero-Order Hold (ZOH) method converts a continuous PID controller into a discrete-time controller by assuming that the digital control signal is held constant between sampling instants. Applying the ZOH method to the three components of the PID controller yields the expressions defined by (29)–(31).

$$u_P\left[k\right]=K_{p}e\left[k\right].$$

(29)

$$u_I\left[k\right]=K_i{T}_{s}e[k-1]+K_i{T}_{s}e\left[k\right].$$

(30)

$$u_D\left[k\right]=K_d{\displaystyle \frac{e\left[k\right]-e[k-1]}{T_s}}+u_D[k-1].$$

(31)

By combining the three contributions, the ZOH-based discrete PID controller becomes

$$u\left[k\right]=K_{p}e\left[k\right]+K_i{T}_{s}e[k-1]+K_i{T}_{s}e\left[k\right]+K_d{\displaystyle \frac{e\left[k\right]-e[k-1]}{T_s}}+u_D[k-1].$$

(32)

The implementation of the robust dead-time compensator (DTC) requires the discretization of the compensator defined by (33).

$$F\left(s\right)={\displaystyle \frac{T_{0}s+1}{T_{1}s+1}},$$

(33)

where $T_0$ and $T_1$ denote the zero and pole time constants, respectively. Using the ZOH discretization method, this transfert function can be written using (34).

$$F\left(z\right)={\displaystyle \frac{k_1+k_2{z}^{-1}}{1-k_3{z}^{-1}}},$$

(34)

with the coefficients

$$k_3={\displaystyle \frac{T_1}{T_s+T_1}},k_1={\displaystyle \frac{T_s+T_0}{T_s+T_1}},k_2=-{\displaystyle \frac{T_0}{T_s+T_1}}.$$

(35)

The corresponding difference equation is defined by (36).

$$y\left[k\right]=k_{3}y[k-1]+k_{1}u\left[k\right]+k_{2}u[k-1].$$

(36)

4.2. Tustin (Bilinear) Discretization

The Tustin method provides a more accurate discretization of the continuous-time PID controller by applying the substitution defined by (37).

$$s\approx {\displaystyle \frac{2}{T_s}}{\displaystyle \frac{1-z^{-1}}{1+z^{-1}}}.$$

(37)

Applying the Tustin method to the three components of the PID controller yields the discrete-time expressions defined by (38)–(40).

$$u_P\left[k\right]=K_{p}e\left[k\right].$$

(38)

$$u_I\left[k\right]=u_I[k-1]+K_i{\displaystyle \frac{T_s}{2}}\left(e\left[k\right]+e[k-1]\right).$$

(39)

$$u_D\left[k\right]=K_d{\displaystyle \frac{e\left[k\right]-e[k-1]}{T_s}}+u_D[k-1].$$

(40)

By combining the three contributions, the discrete PID controller obtained using the Tustin method can be written as (41).

$$\begin{array}{cc}\hfill u\left[k\right]=& u[k-1]+K_p\left(e\left[k\right]-e[k-1]\right)\hfill \\ \hfill & + K_i{\displaystyle \frac{T_s}{2}}\left(e\left[k\right]+e[k-1]\right)+K_d{\displaystyle \frac{e\left[k\right]-e[k-1]}{T_s}}-u_D[k-1].\hfill \end{array}$$

(41)

Similarly, to implement the robust dead-time compensator (DTC), the compensator $F\left(s\right)$, defined by (33), can be presented in its discrete form using (42).

$$F\left(z\right)={\displaystyle \frac{b_0+b_1{z}^{-1}}{a_0+a_1{z}^{-1}}},$$

(42)

with coefficients defined by (43)–(46).

$$b_0=1+{\displaystyle \frac{2T_0}{T_s}},$$

(43)

$$b_1=1-{\displaystyle \frac{2T_0}{T_s}},$$

(44)

$$a_0=1+{\displaystyle \frac{2T_1}{T_s}},$$

(45)

$$a_1=1-{\displaystyle \frac{2T_1}{T_s}}.$$

(46)

To obtain the standard normalized form suitable for digital implementation, the transfer function is divided by $a_0$, yielding the expression (47).

$$F\left(z\right)={\displaystyle \frac{k_1+k_2{z}^{-1}}{1+k_3{z}^{-1}}},$$

(47)

where the discrete-time coefficients are defined using (48)–(50).

$$k_1={\displaystyle \frac{T_s+2T_0}{T_s+2T_1}},$$

(48)

$$k_2={\displaystyle \frac{T_s-2T_0}{T_s+2T_1}}.$$

(49)

$$k_3={\displaystyle \frac{T_s-2T_1}{T_s+2T_1}},$$

(50)

Accordingly, the resulting difference equation used for the digital implementation is given by (51).

$$y\left[k\right]=-k_{3}y[k-1]+k_{1}u\left[k\right]+k_{2}u[k-1].$$

(51)

This formulation corresponds to the digital implementation commonly used in microcontrollers and FPGA architectures.

5. Experimental Validation

5.1. Experimental Test Bench Description

The experimental test bench developed in this study is dedicated to validating control strategies applied to a three-phase brushless DC (BLDC) motor. It has been designed to reproduce a realistic traction architecture representative of embedded and robotic applications, while enabling a complete hardware implementation of the control algorithms using the Xilinx-AMD FPGA platform.

Figure 2 presents the global block diagram of the experimental test bench. The architecture is based on a DC energy source provided by a LiPO battery, a three-phase DC–AC inverter supplying the BLDC motor, and the FPGA platform responsible for generating the control signals, and a Raspberry Pi 5 interfaced with the FPGA board using SPI (Serial Peripheral Interface) is used to provide data gateway functions. Galvanic isolation between the digital and power sections ensures system safety and signal integrity.

The DC–AC power circuit converts the DC voltage into three-phase AC voltages required for the electronic commutation of the BLDC motor. The inverter was specifically designed for this test bench in order to ensure optimal compatibility with the digital control architecture and the required power levels and to meet the motor operating constraints. The inverter is controlled by an FPGA platform, which generates the Pulse Width Modulation (PWM) signals required to drive the power switches. The control algorithms (PI/PID, IMC-based controllers, and a robust dead-time compensator) are implemented on the FPGA using Xilinx Vivado System Generator (Version 2023.2, Xilinx Inc., San Jose, CA, USA), enabling deterministic execution and fixed-point arithmetic.

Dedicated galvanic isolation boards have been integrated into the test bench to ensure electrical isolation between the low-voltage control stage and the high-power stage. These boards rely on opto-couplers to transmit the PWM signals from the FPGA to the inverter, while protecting the control electronics from electromagnetic disturbances and overvoltage conditions generated by power switching. The three-phase BLDC motor is equipped with Hall effect sensors and an encoder, providing rotor position and speed information, respectively. These feedback signals are transmitted to the FPGA via a second galvanic isolation interface, ensuring reliable, safe measurement of mechanical quantities. This information is used for closed-loop control and for evaluating the dynamic performance of the overall system.

Overall, this experimental test bench constitutes a complete and flexible platform for the realistic validation of the proposed control strategies, taking into account practical hardware constraints such as computation delays, switching phenomena, isolation effects, and limitations of FPGA-based digital implementation.

5.1.1. Three-Phase DC–AC Inverter Design

The three-phase DC–AC inverter developed in this work constitutes the power interface supplying the BLDC motor. It operates within a DC voltage range of 12 V to 48 V, with a maximum current of 30 A, and is implemented on a four-layer printed circuit board to reduce parasitic inductances, improve ground return paths, and ensure reliable high-frequency switching operation. The board integrates six IKP20N60T (from Infineon Technologies, Neubiberg, Germany) power IGBTs arranged in a three-phase bridge topology, providing DC–AC conversion to the three motor phases, which are accessible through the power output connector. The DC bus is stabilized by an electrolytic DC-link capacitor 100YXG220MEFC16X20 (from Rubycon Corporation, Nagano, Japan), placed in close proximity to the switching devices to minimize voltage ripple and current spikes during commutation. The IGBTs are driven by isolated gate driver circuits based on the 1EDI20N12AFXUMA1 (from Infineon Technologies, Neubiberg, Germany) device, each associated with dedicated gate resistor–capacitor networks to adjust rise and fall times, control overvoltages, and mitigate electromagnetic interference. The isolated supply for the gate drivers is provided by a PQME1-S15-S15-S DC–DC converter (from Bel Power Solutions, Northridge, CA, USA), ensuring galvanic isolation between the low-voltage control stage and the power stage. The PWM control signals generated by the FPGA are applied through dedicated control connectors, while the main power supply is connected via the power input interface. The entire board has been designed for direct integration with FPGA-based digital control, taking into account dead-time constraints, switching effects, electromagnetic robustness, and electrical safety and isolation requirements, making it a suitable platform for the experimental validation of BLDC motor control strategies. A 3D view of the design is illustrated in Figure 3.

The isolation board developed for this experimental setup, illustrated in Figure 4, fulfills a dual and essential role: providing galvanic isolation between the FPGA-based control platform and the electromechanical subsystems and ensuring voltage level and impedance adaptation between the different system blocks. The FPGA operates with 3.3 V logic levels, whereas the BLDC motor sensors, including Hall effect sensors and the encoder, generate digital signals at 5 V. To guarantee safe and reliable electrical compatibility, the board integrates digital isolators IL711–3E (NVE Corporation, Eden Prairie, MN, USA), which enable bidirectional signal transmission while ensuring effective galvanic isolation between the low-voltage control domain and the motor-related subsystems. The isolated power supply of the board is provided by a CC3–1205SF–E DC–DC converter (Bel Power Solutions, Northridge, CA, USA), which generates an isolated 5 V supply from the input voltage. This isolated voltage is used to power the isolated logic circuits as well as the sensor interfaces. Such an architecture enables proper voltage level translation between 3.3 V and 5 V, limits loading effects and return currents, and effectively protects the FPGA against electromagnetic interference, ground loops, and overvoltage disturbances originating from the motor environment. Consequently, the isolation board plays a key role in enhancing the reliability, electrical safety, and overall robustness of the BLDC motor control system.

5.1.2. BLDC Motor

The BLDC motor used in this study is the BL23E33–01D-Y20–ES1000–B12F model from Lin Engineering (Morgan hill, CA, USA). It is a three-phase NEMA 23 motor powered from 12 to 24 VDC, capable of delivering up to 120 W of mechanical power with a nominal speed of 4000 rpm. It is equipped with a 1000 CPR optical encoder and a 20:1 planetary gearbox, enabling high torque output while ensuring accurate positioning. This motor belongs to the family of BLDC machines with trapezoidal back–EMF, which requires a six–step (trapezoidal) commutation strategy. Figure 5 shows the BLDC motor model BL23E33-01D-Y20-ES1000-B12F used in this study. The electrical and mechanical parameters of the motor are provided by the manufacturer, Lin Engineering, and are summarized in

Table 2. BLDC Motor Specifications.

Parameter	Value
Number of phases	3
Frame size	56 mm
NEMA size	NEMA 23
Body length (Dimension A)	83.5 mm
Rated voltage	24 VDC
Rated output power	120 W
Rated speed	4000 RPM
Maximum speed (motor only)	5000 RPM
Maximum speed (with gearbox)	250 RPM
Rated torque (motor only)	0.29 Nm
Rated torque (with gearbox)	4.93 Nm
Rated current	6.9 A
Maximum torque	0.58 Nm
Phase resistance	0.18 $\mathrm{\Omega }$
Terminal inductance	0.18 mH
Torque constant	0.042 Nm/A
Rotor inertia	279 g·cm2
Weight (motor only)	1.08 kg
Weight (with configured parts)	2.08 kg
Electrical time constant	1 ms
Mechanical time constant	3 ms

.

Figure 6 shows the experimental test bench designed to validate and compare the various controllers proposed in this work, applied to a BLDC motor drive system under real operating conditions.

5.1.3. Open-Loop Experiments

Based on the modeling principles presented before, we develop approximate dynamic models of the motor investigated in this work, namely the brushless DC (BLDC) motor. These models serve as the foundation for subsequent stages of controller design, discretization, and performance evaluation.

In this study, the identification experiments were conducted in an open loop. The analyzed system corresponds to the complete chain composed of the power supply, inverter, sensors, and BLDC motor, which is considered as a single functional block. Consequently, the identified dynamics represent the global behavior of the electromechanical conversion chain, including inverter switching delays, the electromechanical characteristics of the motor, and inherent system nonlinearities.

It is important to note that the proper operation of a BLDC system requires the prior definition of an appropriate commutation strategy. In this work, a six-step commutation strategy was implemented to ensure motor rotation. The commutation process relies on signals from Hall effect sensors, which determine at each instant which inverter switches must be activated to energize the motor phases.

Table 3. Commutation sequence for the BLDC motor.

Hall-Effect Sensor				Phase U		Phase V		Phase W
Ph-U	Ph-V	Ph-W	Step	H	L	H	L	H	L
1	0	0	1	PWM	None	None	None	None	PWM
1	1	0	2	None	None	PWM	None	None	PWM
0	1	0	3	None	PWM	PWM	None	None	None
0	1	1	4	None	PWM	None	None	PWM	None
0	0	1	5	None	None	None	PWM	PWM	None
1	0	1	6	PWM	None	None	PWM	None	None

presents the correspondence between the Hall effect sensor patterns and the associated commutation sequence of the BLDC motor. For each phase, the control signals are separated into high-side (H) and low-side (L) switches. The notation PWM indicates that the corresponding switch is driven by a PWM signal, while None means that the switch is inactive. This representation explicitly distinguishes the conduction path of each phase and facilitates the implementation of the commutation logic in digital control hardware.

Figure 7 shows the three Hall sensor signals and the corresponding phase currents in real time. The Hall waveforms follow exactly the commutation sequence defined in Table 3, which confirms that the decoding of the rotor position is consistent with the intended six-step pattern. The phase currents present a trapezoidal waveform that is characteristic of six-step (trapezoidal) commutation, with each phase conducting for 120 electrical degrees and the current transitions synchronised with the Hall edges.

To identify the parameters of the dynamic model, a sequence of steps corresponding to variations in the duty cycle applied to the inverter was imposed in an open loop. The resulting motor speed was measured for each operating point. Since the BLDC motor and its power electronic interface do not exhibit perfectly linear behavior, each increment of the duty cycle produces a slightly different speed variation. This observation justifies adopting an identification approach based on approximate dynamic models. Figure 8 illustrates the experimental motor speed response to successive PWM duty-cycle steps in open-loop operation.

The identification procedure yielded the following parameters:

$$K=0.00185,\tau =0.125 \mathrm{s},L=0.0717\mathrm{s}.$$

The overall dynamic behavior of the system (inverter + BLDC motor) can therefore be represented by a first-order plus dead-time (FOPDT) model (5), which provides a sufficiently accurate approximation for controller design and performance analysis in the following sections. Using the identified FOPDT model, PI, PID, and IMC–PID controllers were tuned according to classical and IMC-based methods, and the corresponding parameters are reported in

Table 4. PI controller parameters obtained using different tuning methods.

Controller	Tuning Method	${\mathit{k}}_{\mathit{p}}$	${\mathit{t}}_{\mathit{i}}$
PI	Ziegler–Nichols (ZN)	848.1285	0.239
	Cohen–Coon (CC)	893.1735	0.1111
	Chien–Hrones (CH)	329.8277	0.1458
	Chien–Hrones–Reswick (CHR)	565.419	0.125

,

Table 5. PID controller parameters obtained using different tuning methods.

Controller	Tuning Method	${\mathit{k}}_{\mathit{p}}$	${\mathit{t}}_{\mathit{i}}$	${\mathit{t}}_{\mathit{d}}$
PID	Ziegler–Nichols (ZN)	1130.8	0.1434	0.0359
	Cohen–Coon (CC)	1391.6	0.1445	0.0236
	Chien–Hrones (CH)	565.419	0.125	0.5
	Chien–Hrones–Reswick (CHR)	895.2467	0.1696	0.4737

,

Table 6. IMC–PID controller parameters for different values of the IMC tuning parameter ${\tau }_c$.

Controller	IMC Parameter	${\mathit{k}}_{\mathit{p}}$	${\mathit{t}}_{\mathit{i}}$	${\mathit{t}}_{\mathit{d}}$
IMC–PID	${\tau }_c=\tau /1=0.1250$	379.4167	0.1381	0.0108
	${\tau }_c=\tau /2=0.0625$	893.451	0.1249	0.0211
	${\tau }_c=\tau /3=0.0417$	$1.26\times {10}^3$	0.1137	0.0252

and

Table 7. Parameters of the robust dead-time compensator (DTC) for different values of the equivalent delay $T_e$.

Controller	Equivalent Delay ${\mathit{T}}_{\mathit{e}}$	${\mathit{D}}_{\mathit{m}}$	${\mathit{T}}_0$	${\mathit{T}}_1$
DTC	$T_e=(\tau +L)/1$	0.0072	0.011	0.2110
	$T_e=(\tau +L)/3$	0.0072	0.011	0.0799
	$T_e=(\tau +L)/10$	0.0072	0.011	0.034

.

6. FPGA Implementation and Validation of Control Strategies

The digital control algorithms were implemented on a Xilinx Nexys A7 FPGA board (XC7A100T-1CSG324C, Xilinx, Inc., San Jose, CA, USA), clocked by a main system clock of 100 MHz. All computations are carried out using fixed-point arithmetic, which requires appropriate signal scaling in order to ensure sufficient numerical precision, avoid overflow, and maintain consistency between the physical quantities and their internal digital representation.

The PWM signal used to drive the inverter is generated by means of a synchronous counter based on the FPGA clock. The PWM switching frequency was set to 2 kHz. Consequently, the number of clock cycles corresponding to one PWM period is given by

$$N_{\mathrm{PWM}}={\displaystyle \frac{100\mathrm{MHz}}{2\mathrm{kHz}}}=\mathrm{50,000}.$$

In practice, the PWM counter is limited to a maximum value of approximately 49,000 in order to account for internal margins and synchronization constraints. The duty cycle is obtained by comparing the control command generated by the controller with this counter. The sampling period used for the implementation of the controllers is fixed at $T_s=0.5\mathrm{ms}$, which corresponds to 50,000 FPGA clock cycles at 100 MHz. An enable signal, generated by dividing the main clock, is used to strictly synchronize the execution of the control laws. As a result, the proportional, integral, and derivative computations are performed only at the sampling instants, ensuring a behavior consistent with the discrete-time model and preventing any undesired accumulation at the FPGA clock frequency.

To interface the physical variables with the digital controller, scaling gains were introduced upstream of the reinterpret blocks. The maximum reference speed is set to 120 rpm. This reference is converted into an internal fixed-point representation by applying the gain $G_r=512=2^9$. This choice provides a good numerical resolution while simplifying the hardware implementation, since powers of two are naturally well suited to FPGA architectures through simple binary shifts.

The measured speed is obtained from an encoder mounted on the motor shaft. Due to the presence of a mechanical gearbox with a ratio of 20, the measured speed is first scaled down to the load-side speed by a factor of $1/20$. It is then scaled using the same gain $G_r=512$, ensuring that both the reference and the measured speed are expressed in the same numerical domain during the error computation.

Finally, the controller output is converted into a PWM duty cycle. Since the PWM counter spans values up to approximately 49,000, the control command is normalized and expressed as a percentage using the gain

$$G_d={\displaystyle \frac{100}{\mathrm{49,000}}}\approx 0.002.$$

This scaling facilitates the observation and analysis of the duty cycle in percentage form, while the raw controller output is directly used for PWM signal generation.

Overall, this scaling strategy ensures numerical robustness, efficient utilization of FPGA resources, and a faithful correspondence between physical variables and their digital representation, while guaranteeing real-time operation compatible with embedded control constraints.

6.1. Implementation of PI Controller

6.1.1. PI Controller Discretized Using the Tustin Method

Figure 9 illustrates the complete architecture of the PI controller discretized using the Tustin (bilinear) method and implemented on an FPGA using Xilinx System Generator (Version 2023.2, Xilinx Inc., San Jose, CA, USA). The diagram is structured into several clearly identified functional blocks. The reference (Ref) and measurement (Mes) signals are first scaled and converted into a numerical format suitable for fixed-point arithmetic and are then used to compute the control error.

The proportional and integral contributions are implemented in separate branches. The proportional branch computes the difference between the current error and the delayed error, weighted by the proportional gain, while the integral branch relies on a recursive accumulation based on the sum of the current and previous errors, in accordance with the Tustin approximation. Delay blocks ($z^{-1}$) are used to store past values of the error and the control signal, enabling an efficient sequential realization of the controller on the FPGA.

The update of the PI controller is strictly synchronized by enable signals generated at the sampling period $T_s$. These enable blocks ensure that the arithmetic operations and register updates are performed only at the defined sampling instants, thereby guaranteeing a discrete-time behavior consistent with the Tustin-based formulation and preventing any unintended accumulation at the internal FPGA clock frequency.

The proportional and integral contributions are then summed to generate the discrete control command. This command is subjected to saturation blocks in order to respect the physical limits of the system and to prevent integrator windup. The discrete control command constitutes the first output of the controller. It is subsequently used to generate a PWM signal by comparison with a synchronized periodic counter, providing the second output of the system, which is directly applied to drive the three-phase inverter in real time.

6.1.2. PI Controller Discretized Using the Zero-Order Hold (ZOH)

Figure 10 illustrates the complete architecture of the PI controller discretized using the Zero-Order Hold (ZOH) method and implemented on an FPGA using Xilinx System Generator. The diagram is structured into several clearly identified functional blocks. The reference (Ref) and measurement (Mes) signals are first scaled and converted into a numerical format suitable for fixed-point arithmetic and are then used to compute the control error.

The proportional and integral contributions are implemented in separate branches. The proportional branch applies a gain to the instantaneous error, while the integral branch relies on a discrete accumulator implemented using registers and delay blocks ($z^{-1}$). The enable blocks ensure that the computations and register updates are performed only at the defined sampling period, thereby guaranteeing a behavior consistent with the ZOH discrete-time model and preventing any unintended accumulation at the internal FPGA clock rate.

The two contributions are then summed to generate the discrete control command. This command is subjected to saturation blocks in order to respect the physical limits of the system. The discrete control command constitutes the first output of the controller. It is subsequently used to generate a PWM signal by comparison with a synchronized periodic counter, providing the second output of the system, which is directly applied to drive the three-phase inverter.

The performance of the PI controller implemented on the FPGA was evaluated through both simulation studies and experimental validations using several classical tuning methods, namely Ziegler–Nichols, Chien–Hrones–Reswick (CHR) with 20% overshoot, CHR without overshoot (CH), and Cohen–Coon. For each tuning method, two discretization techniques were compared: the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. The results presented in Figure 11 highlight a good overall agreement between simulated and experimental responses, thereby confirming the validity of the FPGA-based hardware implementation.

The Ziegler–Nichols tuning is characterized by a fast dynamic response; however, it introduces significant overshoot and pronounced oscillations, particularly in the experimental results, with these effects being more evident when the ZOH discretization is used. The CHR method with 20% overshoot improves the response speed at the expense of increased control effort and larger transient oscillations. In contrast, the CHR tuning without overshoot (CH) provides a more damped behavior, with a significant reduction in oscillations and improved stability, making it more suitable for applications requiring more conservative dynamic performance. The Cohen–Coon method results in a more aggressive control action, characterized by larger duty-cycle variations and increased sensitivity to discretization effects.

Across all the investigated tuning methods, the PI controller discretized using the Tustin approximation consistently outperforms the implementation based on the ZOH method. In particular, the Tustin discretization leads to smoother responses, better agreement between simulation and experimental results, and reduced steady-state oscillations. These findings confirm the relevance of the Tustin method for FPGA-based digital control, especially in terms of fidelity to the continuous-time controller and robustness against discretization effects.

6.1.3. Performance Analysis of the PI Controller

The performance of the PI controller was quantitatively evaluated using three classical performance indices: the Integral of Squared Error (ISE), the Integral of Time-weighted Absolute Error (ITAE), and the control effort index (I). These criteria were computed for different tuning methods and for both discretization techniques, namely the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. As reported in

Table 8. Performance indices of the PI controller for different tuning methods and discretization techniques.

Controller	ISE		ITAE		I
	ZOH	Tustin	ZOH	Tustin	ZOH	Tustin
PI–ZN	45.81	44.49	166.47	162.45	57,080.08	56,977.39
PI–CC	59.28	51.50	209.08	197.18	52,402.74	58,240.81
PI–CH	62.20	61.69	164.28	165.03	57,088.17	57,471.26
PI–CHR	49.51	56.32	164.33	162.43	57,200.58	56,895.72

, the Ziegler–Nichols tuning combined with the Tustin discretization slightly improves both the ISE and ITAE indices compared to the ZOH implementation. This indicates a more accurate tracking performance and a faster attenuation of the tracking error, while maintaining a comparable control effort.

The Cohen–Coon tuning method exhibits higher values of ISE and ITAE, reflecting a more aggressive control strategy. Although the Tustin approximation significantly reduces the time-weighted error compared to ZOH, it leads to an increased control effort, which may be less suitable for embedded applications with actuator or power constraints.

For the Chien–Hrones (CH) tuning, relatively large ISE values are observed, particularly with the ZOH discretization, confirming a slower dynamic response and reduced tracking accuracy. In contrast, the Chien–Hrones–Reswick (CHR) tuning provides a better compromise between tracking performance and control effort. As shown in Table 8, the CHR method combined with the Tustin discretization yields lower ITAE values and reduced steady-state oscillations.

Overall, the results presented in Table 8 demonstrate that the Tustin discretization consistently enhances the performance of the PI controller compared to the ZOH method. In particular, it leads to improved transient behavior and reduced time-weighted error, confirming the suitability of the Tustin-based PI implementation for FPGA-based motor control applications requiring high accuracy and robustness.

6.1.4. Experimental Analysis Under DC Bus Voltage Disturbance

The robustness of the controllers was evaluated based on experimental curves obtained during a DC bus voltage disturbance generated using a programmable DC power supply (HPT5K0TS200-L, XP Power, Singapore). The supply voltage was increased from $12.60$ $\mathrm{V}$ to $15.60$ $\mathrm{V}$, with the disturbance applied for a duration of 10 $\mathrm{s}$ after steady-state operation was reached, as illustrated in Figure 12.

After the comparative analysis of the PI tuning methods, the Chien–Hrones–Reswick without overshoot (CH) and Ziegler–Nichols tunings, both implemented using the Tustin discretization method, were selected for these tests. As shown in Figure 12, the CH-based PI controller exhibits a small transient deviation and a stable control action, indicating good disturbance rejection capability. In contrast, the Ziegler–Nichols-based PI controller shows higher sensitivity to the supply voltage variation, with larger speed deviations and more pronounced variations in the control signal.

These results confirm that a more aggressive tuning may perform well under nominal conditions but becomes more sensitive in the presence of disturbances. Conversely, a more damped tuning provides better robustness against DC bus voltage variations.

6.1.5. FPGA Resource Utilization Analysis of the PI Controller

Table 9. Worst-case FPGA resource utilization of the PI controller for ZOH and Tustin discretization methods (XC7A100T-1CSG324C, Xilinx Inc., San Jose, CA, USA).

Controller	Discretization	Slice LUTs (%)	Slice Registers (%)
PI	ZOH	501 (0.79%)	292 (0.23%)
PI	Tustin	580 (0.91%)	339 (0.27%)

summarizes the worst-case FPGA resource utilization of the PI controller for the ZOH and Tustin discretization methods. The Tustin-based implementation exhibits higher resource consumption due to its increased arithmetic complexity. However, in both cases, the utilization remains below 1% of the available FPGA resources, demonstrating that the proposed PI controller implementations are well suited for real-time embedded motor control applications.

6.2. Implementation of PID Controller

6.2.1. PID Controller Discretized Using the Tustin Method

Figure 13 illustrates the complete architecture of the PID controller discretized using the Tustin (bilinear) method and implemented on an FPGA using Xilinx System Generator. The diagram is structured into several clearly identified functional blocks. The reference (Ref) and measurement (Mes) signals are first scaled and converted into a numerical format compatible with fixed-point arithmetic and are then used to compute the control error.

The proportional, integral, and derivative contributions are implemented in separate branches according to the Tustin discretization. The proportional branch computes the difference between the current error and the delayed error, weighted by the proportional gain. The integral branch performs a recursive accumulation based on the sum of the current and previous errors, while the derivative branch computes the variation in the error between two consecutive sampling instants. Delay blocks ($z^{-1}$) are used to store past values of the error and internal states, enabling an efficient sequential realization of the Tustin-based discrete PID model on the FPGA.

The update of the PID controller is strictly synchronized by enable signals generated at the sampling period $T_s$. These enable blocks ensure that the arithmetic operations and register updates are executed only at the defined sampling instants, guaranteeing a discrete-time behavior consistent with the Tustin formulation and preventing any unintended accumulation at the internal FPGA clock frequency.

The proportional, integral, and derivative contributions are then summed to generate the discrete control command. This command is subjected to saturation blocks in order to respect the physical limits of the system and to prevent integrator windup. The discrete control command constitutes the first output of the controller. It is subsequently used to generate the second output through a synchronized comparison process, which is applied to the power stage for closed-loop control of the system.

6.2.2. PID Controller Discretized Using the the Zero-Order Hold (ZOH)

Figure 14 illustrates the complete architecture of the PID controller discretized using the Zero-Order Hold (ZOH) method and implemented on an FPGA using Xilinx System Generator. The diagram is structured into several clearly identified functional blocks. The reference (Ref) and measurement (Mes) signals are first scaled and converted into a numerical format suitable for fixed-point arithmetic and are then used to compute the control error.

The proportional, integral, and derivative contributions are implemented in separate branches. The proportional branch applies a gain to the instantaneous error, while the integral branch uses a discrete accumulator implemented with registers and delay blocks ($z^{-1}$). The derivative branch computes the variation in the error between two consecutive sampling instants. The enable blocks ensure that the computations and register updates are performed only at the defined sampling period, thereby guaranteeing a behavior consistent with the ZOH discrete-time model.

The three contributions are then summed to generate the discrete control command. This command is subjected to saturation blocks in order to respect the physical limits of the system and to prevent integrator windup. The discrete control command constitutes the first output of the controller. It is subsequently used to generate a PWM signal by comparison with a synchronized periodic counter, providing the second output of the system, which is directly applied to drive the three-phase inverter.

The performance of the PID controller implemented on the FPGA was evaluated through both simulation studies and experimental validations using several classical tuning methods, namely Ziegler–Nichols, Chien–Hrones–Reswick (CHR) with 20% overshoot, CHR without overshoot, and Cohen–Coon. For each tuning method, two discretization techniques were compared: the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. The results of Figure 15 show good overall agreement between simulated and experimental responses, thereby confirming the validity and reliability of the FPGA-based PID controller implementation.

The Ziegler–Nichols tuning is characterized by a fast dynamic response; however, it introduces significant overshoot and pronounced oscillations, particularly in the experimental results. These effects are more evident when the ZOH discretization is used due to the increased sensitivity of the derivative action to discretization effects and measurement noise. The CHR method with 20% overshoot improves the transient response speed at the cost of higher control effort and larger transient oscillations. In contrast, the CHR tuning without overshoot leads to a more damped behavior, with a noticeable reduction in oscillations and improved closed-loop stability, making it more suitable for applications requiring conservative and robust dynamic performance. The Cohen–Coon method results in a more aggressive control action, characterized by large duty-cycle variations and increased sensitivity to discretization effects, especially in experimental tests.

Across all the investigated tuning methods, the PID controller discretized using the Tustin approximation consistently outperforms the implementation based on the ZOH method. In particular, the Tustin discretization yields smoother responses, reduced oscillations in both transient and steady-state regimes, and better agreement between simulation and experimental results. This behavior can be explained by the ability of the bilinear transformation to better preserve the dynamics of the continuous-time PID controller, especially in the presence of the derivative term. These results confirm the relevance of the Tustin method for FPGA-based digital PID control, particularly in terms of robustness and fidelity with respect to the continuous-time model, compared to the ZOH discretization.

6.2.3. Performance Analysis of the PID Controller

The performance of the PID controller was evaluated using three standard performance indices: the Integral of Squared Error (ISE), the Integral of Time-weighted Absolute Error (ITAE), and the control effort index (I). These metrics were computed for different classical tuning methods and for both discretization techniques, namely the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. As shown in

Table 10. Performance indices of the PID controller for different tuning methods and discretization techniques.

Controller	ISE		ITAE		Control Effort (I)
	ZOH	Tustin	ZOH	Tustin	ZOH	Tustin
PID–ZN	58.07	82.24	223.23	232.25	57,096.44	56,655.65
PID–CC	168.86	123.79	390.99	353.65	56,894.09	57,554.53
PID–CH	57.64	47.06	161.50	155.08	56,441.95	56,308.64
PID–CHR	42.72	42.39	165.56	170.07	57,143.00	56,729.20

, the Ziegler–Nichols tuning applied to the PID controller results in relatively high ITAE values and increased oscillatory behavior, particularly when combined with the Tustin discretization. Although the ZOH implementation provides a slightly lower ISE, both discretization methods lead to a significant transient overshoot, confirming the aggressive nature of the Ziegler–Nichols tuning for PID control.

The Cohen–Coon tuning exhibits the highest ISE and ITAE values among all tested methods, indicating poor tracking accuracy and slow error attenuation. While the Tustin discretization significantly improves the ISE and ITAE compared to ZOH, this improvement is achieved at the cost of a higher control effort, which may be undesirable for embedded motor drive applications.

In contrast, the Chien–Hrones (CH) tuning provides a noticeable improvement in performance. As reported in Table 10, the PID controller discretized using the Tustin method yields lower ISE and ITAE values compared to the ZOH implementation, indicating smoother responses and better tracking performance. Moreover, the associated control effort remains moderate, making this tuning approach suitable for practical implementation.

The best overall performance is achieved with the Chien–Hrones–Reswick (CHR) tuning. This method yields the lowest ISE values for both discretization techniques and maintains relatively low ITAE and control effort indices. The Tustin-based implementation slightly improves the ISE, while preserving a comparable control effort, confirming its robustness and efficiency.

Overall, the results summarized in Table 10 demonstrate that the Tustin discretization generally enhances the dynamic performance of the PID controller, particularly when combined with CH and CHR tuning methods. These findings confirm the relevance of Tustin-based PID implementations for FPGA-based motor control systems, where a compromise between fast response, robustness, and limited control effort is required.

6.2.4. Experimental Analysis of the PID Controller Under DC Bus Voltage Disturbance

The robustness of the PID controllers was evaluated under the same disturbance conditions, as shown in Figure 16.

Following the prior comparative analysis, the Chien–Hrones–Reswick tuning without overshoot (CH) and the Ziegler–Nichols tuning, both implemented using the Tustin discretization method, were selected for these tests. The CH-based PID controller exhibits a limited transient speed deviation and a smooth control action, indicating good disturbance rejection capability. In contrast, the Ziegler–Nichols-based PID controller shows higher sensitivity to the supply voltage variation, characterized by larger speed deviations and more pronounced fluctuations in the control signal.

6.2.5. FPGA Resource Utilization Analysis for the PID Controller

Table 11. Worst-case FPGA resource utilization of the PID controller for ZOH and Tustin discretization methods (XC7A100T-1CSG324C).

Controller	Discretization	Slice LUTs (%)	Slice Registers (%)
PID	ZOH	944 (1.49%)	434 (0.34%)
PID	Tustin	1032 (1.63%)	474 (0.37%)

reports the worst-case FPGA resource utilization of the PID controller for the ZOH and Tustin discretization methods. As expected, the Tustin-based implementation requires more logic and registers due to the increased computational complexity of the bilinear transformation. Nevertheless, the overall resource usage remains below 2% of the available FPGA resources, confirming that the proposed PID controller can be efficiently implemented on low-cost FPGA platforms for real-time motor control.

6.3. Implementation of PID Controller Tuned Using the IMC Approach (PID-IMC)

6.3.1. PID Controller Tuned Using the IMC Approach (PID-IMC)

After the implementation and validation of the PID controllers discretized using the Tustin and Zero-Order Hold (ZOH) methods, the PID controller tuned according to the Internal Model Control (IMC) approach (PID-IMC) was also evaluated for different values of the robustness parameter $\lambda$ ranging from 1 to 3. Figure 17 shows the time-domain results. The simulation and experimental results show that the parameter $\lambda$ directly influences the trade-off between response speed and control effort. For $\lambda =1$, the system exhibits a well-damped and robust response, but with relatively slow dynamics. When $\lambda$ is increased to intermediate values, the system response becomes faster while maintaining stable behavior and limited oscillations, thus providing a satisfactory compromise for embedded implementation. In contrast, for higher values of $\lambda$ (greater than 3), the control action becomes more aggressive, with a noticeable increase in duty-cycle variations and higher sensitivity to discretization effects and measurement noise. These results confirm that the choice of the parameter $\lambda$ is a key factor in PID-IMC control and that a moderate value ensures a good balance between dynamic performance, robustness, and control effort in an FPGA-based implementation.

6.3.2. Performance Analysis of the PID–IMC Controller

The performance of the PID controller tuned according to the Internal Model Control (IMC) approach was evaluated using three standard performance indices: the Integral of Squared Error (ISE), the Integral of Time-weighted Absolute Error (ITAE), and the control effort index (I). These indices were computed for different values of the IMC robustness parameter $\lambda$ and for both discretization techniques, namely the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. As reported in

Table 12. Performance indices of the PID–IMC controller for different values of the IMC tuning parameter $\lambda$, comparing ZOH and Tustin discretization methods.

Controller	ISE		ITAE		Control Effort (I)
	ZOH	Tustin	ZOH	Tustin	ZOH	Tustin
IMC–PID ($\lambda =1$)	51.49	57.80	161.09	158.65	56,489.09	57,041.18
IMC–PID ($\lambda =2$)	52.73	61.34	189.51	202.81	56,809.90	57,172.55
IMC–PID ($\lambda =3$)	118.62	124.55	364.63	285.63	57,950.35	56,863.52

, the PID–IMC controller tuned with $\lambda =1$ provides the best overall compromise between tracking performance and control effort. Both ISE and ITAE values remain relatively low for the two discretization methods, indicating accurate reference tracking and satisfactory transient behavior. In addition, the control effort index remains moderate, which is particularly desirable for FPGA-based implementations and power electronic actuators subject to saturation constraints.

When the robustness parameter is increased to $\lambda =2$, a degradation in the performance indices is observed. The ISE and ITAE values increase compared to the case $\lambda =1$, especially for the ZOH discretization. Although the system remains stable, the increased control effort reflects a more demanding control action, which may reduce robustness margins in practical embedded applications.

For higher values of the IMC parameter $\lambda =3$, the deterioration in performance becomes more pronounced. As shown in Table 12, both ISE and ITAE increase significantly, particularly for the ZOH-based implementation, indicating slower error attenuation and increased oscillatory behavior. Moreover, the control effort index rises noticeably, confirming that the control action becomes overly aggressive and more sensitive to discretization effects and measurement noise.

For all tested values of $\lambda$, the Tustin discretization consistently outperforms the ZOH approach. The Tustin-based implementation yields lower ISE and ITAE values, as well as smoother control signals, especially for intermediate and higher values of $\lambda$. This highlights the superior ability of the Tustin approximation to preserve the continuous-time PID–IMC dynamics in the discrete domain.

Overall, the results presented in Table 12 demonstrate that the performance of the PID–IMC controller is strongly influenced by the choice of the robustness parameter $\lambda$. A moderate value of $\lambda$ (close to 1) provides an effective balance between dynamic performance, robustness, and control effort. These findings confirm the suitability of PID–IMC controllers discretized using the Tustin method for FPGA-based motor control applications requiring reliable and robust real-time performance.

6.3.3. Experimental Analysis of the PID–IMC Controller Under DC Bus Voltage Disturbance

The PID–IMC controller was evaluated under the same disturbance conditions described previously, namely a DC bus voltage variation from 12.60 V to 15.60 V applied for 10 s after steady-state operation was reached, as shown in Figure 18.

For the tested robustness parameters, the PID–IMC controller exhibits a limited transient speed deviation and a smooth adaptation of the duty cycle during the disturbance interval. Increasing the robustness parameter $\lambda$ leads to a more damped response and reduced sensitivity to the supply voltage variation.

These results confirm that the PID–IMC strategy ensures stable operation and effective disturbance rejection under DC bus voltage variations, while allowing a controlled trade-off between dynamic performance and robustness through the tuning of $\lambda$.

6.3.4. FPGA Resource Utilization Analysis for the PID–IMC Controller

The FPGA resource utilization of the PID–IMC controller follows the same trend as that of the classical PID controller. This behavior is expected, since the PID–IMC structure does not introduce any additional arithmetic blocks, internal states, or dynamic elements compared to a standard PID implementation. The difference between the PID and PID–IMC controllers lies exclusively in the tuning methodology, which affects only the numerical values of the controller gains. As a result, the overall hardware architecture remains unchanged, and the logic resources required for proportional, integral, and derivative computations are identical. Consequently, the Slice LUT and Slice Register utilization of the PID–IMC controller is comparable to that of the conventional PID controller for a given discretization method (ZOH or Tustin). These results confirm that the IMC-based tuning approach does not increase the FPGA implementation cost, while offering additional flexibility through the robustness parameter. This makes the PID–IMC controller particularly attractive for embedded FPGA-based motor control applications, where improved robustness can be achieved without any penalty in hardware resource consumption.

6.4. Implementation of Robust Dead-Time Compensator (DTC)

6.4.1. Robust Dead-Time Compensator (DTC) Discretized Using the Tustin Method

Figure 19 illustrates the complete architecture of the robust dead-time compensator (DTC) discretized using the Tustin (bilinear) transformation and implemented on an FPGA using Xilinx System Generator. This approach aims to improve the accuracy of the discrete-time representation of the continuous-time compensator while preserving stability and robustness properties in the presence of dead-time effects introduced by the power inverter.

The reference (Ref) and measured speed (Mes) signals are first scaled and converted into a fixed-point numerical format compatible with FPGA implementation. These signals are then used to compute the speed error, which constitutes the main input of the DTC structure. The compensator is based on a two-degree-of-freedom architecture, combining a feedforward filtering action with a feedback compensation loop.

The discrete filter $F\left[z\right]$, obtained using the Tustin discretization method, is employed to shape the reference signal in order to enhance robustness against modeling uncertainties and dead-time effects. In parallel, the discrete internal model of the process $G_m\left[z\right]$ and the discrete model of the actual system $G\left[z\right]$ are used to estimate the disturbance induced by the dead time. The difference between the estimated model output and the real system response generates a corrective action that effectively compensates for the dead-time phenomenon.

The Tustin method introduces a dependence on both current and past signal values. Accordingly, several gain blocks ($K_1$ to $K_5$) and delay elements ($z^{-1}$) are used to implement the discrete-time equations of the DTC in a sequential and hardware-efficient manner. The delay blocks ensure the storage of past internal states, which is essential for accurately reproducing the bilinear transformation in the discrete domain.

The update of the Tustin-discretized DTC is strictly synchronized by enable signals generated at the sampling period $T_s$. These signals guarantee that arithmetic operations and register updates are performed only at the sampling instants, thereby preventing any unintended accumulation at the FPGA clock frequency and ensuring behavior consistent with the theoretical discrete-time model.

The output of the DTC corresponds to a discrete control command that is subjected to saturation blocks to respect the physical constraints of the system and to ensure safe operation. This command is then used to generate the control signal applied to the power stage. The proposed Tustin-based DTC implementation thus provides a more accurate compensation of dead-time effects, improved agreement between simulation and experimental results, and robust real-time operation with efficient utilization of FPGA resources.

6.4.2. Robust Dead-Time Compensator (DTC) Discretized Using the ZOH Method

Figure 20 presents the complete FPGA implementation of the robust dead-time compensator (DTC) discretized using the Zero-Order Hold (ZOH) method and realized with Xilinx System Generator. The proposed architecture is designed to compensate for the dead-time effects introduced by the power inverter, which are particularly detrimental in low-speed and high-precision motor control applications.

The reference (Ref) and measured speed (Mes) signals are first scaled and converted into a fixed-point numerical format compatible with FPGA arithmetic. These signals are then processed to compute the speed error, which serves as the main input to the DTC structure. The compensator is implemented using a two-degree-of-freedom architecture, combining feedforward filtering and a feedback compensation loop.

The discrete-time filter $F\left[z\right]$ is implemented using the ZOH approximation and is responsible for shaping the reference signal in order to improve robustness against modeling uncertainties and dead-time effects. In parallel, the internal model of the process $G_m\left[z\right]$ and the discrete plant model $G\left[z\right]$ are used to estimate the dead-time-induced disturbance. The difference between the estimated model output and the actual plant response is exploited to generate a corrective action that compensates for the dead time.

Multiple gain blocks ($K_1$ to $K_5$) and delay elements ($z^{-1}$) are employed to implement the discrete equations of the DTC controller in a sequential and resource-efficient manner. The use of delay blocks allows the storage of past input and output samples, which is essential for accurate dead-time compensation in the discrete domain.

The update of the DTC algorithm is strictly synchronized using enable signals generated at the sampling period $T_s$. These signals ensure that all arithmetic operations and register updates occur only at the sampling instants, thereby guaranteeing a correct ZOH-based discrete-time behavior and preventing unintended accumulation at the FPGA clock frequency.

The DTC block output is a discrete control command, limited by saturation blocks to respect the system’s physical constraints and ensure safe operation. This command is then compared with a synchronized PWM counter to generate the final PWM signal, which is applied to the inverter power stage. The proposed DTC implementation effectively compensates for dead-time effects while maintaining numerical robustness, real-time operation, and efficient FPGA resource utilization.

As shown in Figure 21 the performance of the robust bead-time compensator (DTC) was evaluated through both simulation and experimental tests for different values of the tuning parameter $\sigma$, namely $\sigma =1$, $\sigma =3$, and $\sigma =10$. The obtained results clearly highlight the influence of this parameter on the trade-off between dynamic response, robustness, and control effort.

For $\sigma =1$, the system exhibits a relatively slow response, characterized by a longer rise time and a gradual attenuation of the error. This configuration prioritizes robustness against dead-time effects and model uncertainties, but at the expense of overall dynamic performance. The control effort remains moderate, resulting in limited variations in the duty cycle.

When $\sigma$ is increased to an intermediate value ($\sigma =3$), a significant improvement in system dynamics is observed. The response becomes faster while maintaining a stable and well-damped behavior. Transient oscillations remain limited, and a good agreement between simulation and experimental results is achieved, indicating a favorable balance between dynamic performance and robustness. This configuration appears to be the most suitable for embedded implementation.

In contrast, for a higher value of $\sigma =10$, the system response becomes noticeably more aggressive. Although the reference tracking is faster, more pronounced oscillations appear, particularly in the control signal. The duty cycle exhibits larger variations, reflecting a significant increase in control effort and a higher sensitivity to noise and discretization effects. While this setting enhances response speed, it may negatively impact the robustness of the system and the lifetime of power components.

Overall, these results confirm the effectiveness of the DTC controller in compensating dead-time effects in the inverter–motor drive system. They also demonstrate that the choice of the tuning parameter $\sigma$ is critical: an intermediate value provides a satisfactory compromise between response speed, stability, and control effort, while ensuring good consistency between simulation and experimental validation in an FPGA-based implementation.

6.4.3. Performance Analysis of the DTC Controller

The performance of the robust dead-time compensator (DTC) was evaluated using three standard performance indices: the Integral of Squared Error (ISE), the Integral of Time-weighted Absolute Error (ITAE), and the control effort index (I). The analysis was conducted for different values of the DTC design parameter $T_e$, corresponding to $T_e=(\tau +L)/(\sigma =1)$, $T_e=(\tau +L)/(\sigma =3)$, and $T_e=(\tau +L)/(\sigma =10)$, and for both discretization techniques, namely the Zero-Order Hold (ZOH) method and the Tustin (bilinear) approximation. As shown in

Table 13. Performance indices of the DTC controller for different values of $T_e$ using ZOH and Tustin discretizations.

Controller	ISE		ITAE		I
	ZOH	Tustin	ZOH	Tustin	ZOH	Tustin
DTC ($T_e=(\tau +L)/1$)	230.37	150.83	423.71	289.64	54,771.73	56,403.50
DTC ($T_e=(\tau +L)/3$)	45.69	55.15	189.90	191.41	61,026.12	61,332.70
DTC ($T_e=(\tau +L)/10$)	31.67	25.49	125.29	98.88	58,390.60	60,042.57

, the DTC configuration with $T_e=(\tau +L)/(\sigma =1)$ exhibits the poorest performance among the tested cases. This configuration leads to very high ISE and ITAE values for both discretization methods, indicating slow error attenuation and weak transient performance. Although the control effort remains moderate, the overall tracking quality is unsatisfactory, making this setting unsuitable for practical motor control applications.

When the parameter is reduced to $T_e=(\tau +L)/(\sigma =3$), a significant improvement in performance is observed. The ISE and ITAE values decrease substantially compared to the previous case, reflecting faster convergence and improved dynamic behavior. However, this improvement is accompanied by an increase in the control effort index, indicating a more demanding control action. Both ZOH and Tustin discretizations exhibit comparable performance, with slightly smoother responses obtained using the Tustin approximation.

The best overall performance is achieved with the most aggressive configuration, $T_e=(\tau +L)/(\sigma =10)$. In this case, the DTC controller yields the lowest ISE and ITAE values for both discretization techniques, demonstrating excellent tracking accuracy and rapid transient response. The Tustin-based implementation further enhances performance by significantly reducing the ITAE index compared to the ZOH method. Although the control effort increases relative to the less aggressive configurations, it remains within acceptable limits for FPGA-based implementations.

Overall, the results summarized in Table 13 confirm that the performance of the DTC controller is highly sensitive to the choice of the design parameter $T_e$. Smaller values of $T_e$ lead to improved dynamic performance at the expense of increased control effort. In addition, the Tustin discretization consistently provides superior performance compared to the ZOH method, particularly in terms of error attenuation and smoothness of the control signal. These findings highlight the effectiveness of the DTC strategy for compensating dead-time effects in FPGA-based motor control systems when properly tuned.

6.4.4. Experimental Analysis of the DTC Controller Under DC Bus Voltage Disturbance

The DTC controller was evaluated under the same disturbance conditions described previously, as illustrated in Figure 22.

For $\sigma =1$, the speed response shows a moderate transient deviation and noticeable oscillations in the control signal during the disturbance interval. Increasing the robustness parameter to $\sigma =3$ results in a more damped response and reduced sensitivity to the supply voltage variation.

These results confirm that the DTC strategy maintains stable operation under DC bus voltage perturbations and that increasing $\sigma$ enhances disturbance rejection while reducing oscillatory behavior, consistent with the robustness–performance trade-off inherent to the DTC design.

6.4.5. FPGA Resource Utilization Analysis of the DTC Controller

Table 14. Worst-case FPGA resource utilization of the DTC controller for ZOH and Tustin discretization methods (XC7A100T-1CSG324C).

Controller	Discretization	Slice LUTs (%)	Slice Registers (%)
DTC	ZOH	2453 (3.87%)	941 (0.74%)
	Tustin	2063 (3.25%)	1155 (0.91%)

reports the worst-case FPGA resource utilization of the robust dead-time compensator (DTC) implemented using the ZOH and Tustin discretization methods. The results highlight the relatively high hardware cost associated with the DTC structure, which stems from its two-degree-of-freedom architecture and the explicit inclusion of internal models for dead-time estimation and compensation.

The ZOH-based DTC implementation requires 2453 Slice LUTs (3.87%) and 941 Slice Registers (0.74%). This higher LUT utilization reflects the significant number of arithmetic operations, gain blocks, and delay elements required to implement the dead-time compensation mechanism in the discrete domain.

When the Tustin discretization is employed, the LUT utilization is reduced to 2063 Slice LUTs (3.25%), corresponding to a decrease of approximately 16% compared to the ZOH implementation. This reduction is achieved at the expense of an increased number of Slice Registers, which rises to 1155 (0.91%). This behavior is consistent with the bilinear transformation, which introduces additional internal states and storage requirements.

Overall, the results demonstrate a clear trade-off between logic utilization and register usage depending on the chosen discretization method. Despite its higher computational complexity, the DTC remains well within the available resources of the XC7A100T FPGA, confirming that robust dead-time compensation can be effectively implemented on an FPGA while maintaining real-time operation and numerical robustness.

6.5. Fixed-Point Implementation and Quantization Effects

The fixed-point formats were selected to ensure a suitable trade-off between numerical precision and hardware complexity. As shown in

Table 15. Worst-case fixed-point arithmetic resource requirements (without DSP blocks) for PI/PID and DTC controllers under ZOH and Tustin discretizations.

Controller	Operation	Fixed-Point Format	Word Length (bits)
PI/PID	Adders	Fix_25_7	25
PI/PID	Multipliers	Fix_25_7	25
DTC	Adders	Fix_25_7	25
DTC	Multipliers	Fix_26_7	26

, for the PI/PID controllers, a Fix_25_7 format was adopted for both addition and constant multiplication operations, providing sufficient dynamic range to accommodate the maximum duty-cycle variations without overflow.

For the DTC controller, a slightly larger format (Fix_26_7) was used for constant multiplication operations due to the additional compensation terms involved in dead-time handling. This increase by one bit enhances numerical robustness while keeping hardware overhead minimal.

Quantization effects were evaluated experimentally by comparing fixed-point and floating-point simulations. The results show negligible deviation in steady-state error and transient response, confirming that the selected word lengths provide adequate resolution for the implemented controller structure.

Overflow prevention was ensured by appropriately scaling intermediate variables and saturation blocks in the digital implementation. All arithmetic operations were verified to remain within the representable range during worst-case disturbance tests.

These results in Table 15 confirm that the selected fixed-point design guarantees numerical stability, avoids overflow, and maintains control performance while ensuring efficient FPGA resource utilization.

7. Discussion

This study provides a comprehensive comparison of several digital control strategies for BLDC motor drives, considering not only control performance but also implementation aspects on FPGA hardware. Classical PI and PID controllers tuned using Ziegler–Nichols, Cohen–Coon, and Chien–Hrones–Reswick methods were first analyzed. The results highlight the well-known trade-offs associated with these tuning rules. Ziegler–Nichols tuning leads to fast responses but induces significant overshoot and oscillations, whereas CH and CHR tunings yield more damped responses and improved stability. Cohen–Coon tuning generally results in aggressive control actions and increased sensitivity to discretization effects.

A systematic comparison between ZOH and Tustin discretization techniques reveals that the Tustin method consistently provides smoother responses, lower ISE and ITAE values, and better agreement between simulation and experimental results. This improvement is mainly attributed to the superior frequency-domain characteristics of the bilinear transformation, which preserves stability margins and better approximates the continuous-time controller dynamics.

The PID–IMC approach introduces an additional degree of freedom through the tuning parameter ${\tau }_c$, allowing direct adjustment of the compromise between robustness and speed of response. Experimental results confirm that moderate values of ${\tau }_c$ provide a satisfactory balance between fast transient response, limited oscillations, and reasonable control effort. Very small values of ${\tau }_c$ lead to sluggish behavior, whereas large values result in aggressive control actions and increased sensitivity to noise and discretization effects.

The robust dead-time compensator (DTC) further improves system performance by explicitly addressing delay-related effects inherent to inverter-based motor drives. Although the DTC introduces additional computational blocks and delay elements, it significantly reduces performance degradation due to dead time, especially under varying operating conditions.

From a hardware perspective, all control strategies were successfully implemented on a Nexys A7 FPGA using fixed-point arithmetic. Classical PI and PID controllers exhibit the lowest hardware cost, while Tustin-based implementations require a modest increase in registers and arithmetic units due to the use of additional delay elements. IMC–PID and DTC controllers introduce higher complexity; however, their resource utilization remains well within the available FPGA capacity and does not compromise real-time operation. These results demonstrate that advanced control strategies can be implemented efficiently on FPGA platforms without prohibitive hardware overhead.

In addition to nominal reference tracking, the experimental tests under DC bus voltage disturbance clearly highlight the differences in robustness among the evaluated strategies. Although all controllers maintain closed-loop stability in the presence of supply perturbations, robustness-oriented approaches consistently provide superior disturbance rejection capability. Chien–Hrones–Reswick tunings without overshoot (CH) and PID–IMC with an increased robustness parameter exhibit smoother control action and reduced sensitivity to input variations. In contrast, Ziegler–Nichols tunings, although effective under nominal conditions, show higher sensitivity to supply disturbances. These results indicate that disturbance robustness is improved when the control strategy is less aggressive and more damped.

8. Conclusions

This paper presented a detailed study of FPGA-based digital control strategies for BLDC motor drives, including classical PI and PID controllers, IMC-tuned PID controllers, and a robust dead-time compensator. The complete system, encompassing the power source, inverter, sensors, and motor, was modeled and identified in an open loop, providing a realistic basis for controller design and validation.

Both ZOH and Tustin discretization methods were investigated, and the results clearly indicate the superiority of the Tustin approximation in terms of tracking accuracy, robustness, and consistency between simulation and experimental measurements. Among the classical tuning methods, CH and CHR provided the best compromise between dynamic performance and stability, while Ziegler–Nichols and Cohen–Coon exhibited more aggressive behavior.

Advanced strategies such as PID–IMC and DTC further enhanced performance, particularly in terms of robustness to delays and operating variations. Importantly, these improvements were achieved with limited additional hardware cost. All controllers were implemented in real time on an FPGA using fixed-point arithmetic, meeting strict timing constraints and demonstrating efficient resource utilization.

The fixed-point analysis further confirmed that the selected word lengths (Fix_25_7 and Fix_26_7) provide sufficient numerical precision while preventing overflow and ensuring numerical stability under worst-case operating and disturbance conditions. The slight increase in arithmetic word length required by the DTC remains marginal and does not significantly impact FPGA resource utilization, confirming the efficiency of the proposed implementation strategy.

In addition to nominal reference tracking, experimental disturbance tests under DC bus voltage variations were conducted to evaluate controller robustness under realistic operating conditions. The results confirm that while all control strategies maintain closed-loop stability under supply perturbations, robustness-oriented designs consistently provide superior disturbance rejection. Control tunings based on the Chien–Hrones–Reswick method, as well as PID–IMC with the robustness parameter set to $\lambda =1$, resulted in a smoother control action and improved robustness against disturbances. In contrast, more aggressive tuning strategies exhibited increased sensitivity to disturbances, leading to a noticeable degradation in the system’s dynamic performance.

The proposed FPGA-based control framework is a flexible solution for evaluating high-performance BLDC motor control. The results confirm that sophisticated control strategies can be successfully deployed on embedded FPGA platforms, offering an effective balance between performance, robustness, and implementation efficiency. Future work will focus on extending the proposed approach to sensorless control and adaptive tuning techniques.