Unveiling the Roles of Bulk and Interface Defects of a High-K Dielectric TiO₂-Based Charge-Trapping Layer in the Device Failure of Non-Volatile Charge-Trapping Memory

Abstract

Charge-trapping memory (CTM) exhibits significant potential in high-density memory, yet reliability degradation resulting from the coupling of program/erase (P/E) cycles and electrical stress remains a key bottleneck for large-scale commercialization. This study focuses on a Au/Al₂O₃/TiO₂/p-Si CTM device, systematically investigating the device failure mechanism under continuously operating P/E cycles and constant voltage stress (CVS), with emphasis on elucidating the synergistic effect of bulk and interface defects on performance decay. Mechanistically, oxygen vacancies in TiO₂ serve as defect precursors, which form Frenkel pairs under electric field stress and further promote the formation of new defect precursors, thereby driving a self-sustaining defect evolution process. Interface traps, by contrast, arise from the cleavage of interfacial Si-H bonds triggered by electric field stress, resulting in a net elevation of the interface state density. The passive effects from the bulk and interface defects may give rise to issues, such as threshold voltage drift and decreased P/E speed. This work provides in-depth insights into the device failure mechanism of CTM, offering critical theoretical support for optimizing fabrication processes and enhancing long-term reliability.

1. Introduction

The escalating demand for low-power, high-density, and low-cost memory in emerging electronics has driven the rapid expansion of the flash memory market, with charge-trapping memory (CTM) emerging as a core candidate for next-generation non-volatile memory (NVM) [1]. Compared with conventional dynamic random-access memory (DRAM), which is volatile, suffers from high leakage currents, and faces integration challenges at advanced nodes, or emerging magnetoresistive random-access memory (MRAM), which involves high fabrication costs and immature scalability for ultra-high density, CTM combines the advantages of non-volatility, high storage density, simple fabrication, and low cost. This makes CTM a promising solution for high-density memory applications in industrial control, automotive electronics, and consumer electronics. However, as CTM technology advances toward ultra-high integration and nano-scale device dimensions, severe reliability bottlenecks have become the primary obstacle to its large-scale commercialization. Repeated program/erase (P/E) cycles and sustained electrical stress induce irreversible changes in the device’s internal physical and chemical structure, leading to significant performance degradation, including threshold voltage drift, P/E speed attenuation, erase saturation, deteriorated data retention, and reduced cycling endurance [2,3,4]. These issues severely restrict the long-term reliability of CTM devices and limit their deployment in high-reliability application scenarios.

Among the various degradation mechanisms, device failure induced by tunnel-oxide-layer damage has become a research hotspot [5,6,7,8]. Such damage not only prolongs the P/E operation time but also significantly impairs long-term data retention after cycling [9,10,11]. Some studies attribute this to charge leakage caused by stress-induced leakage current (SILC) [12,13,14], while others point out that the generation and evolution of defect states are the core causes of threshold voltage instability [15,16]. However, due to the complexity of CTM device structures and the diversity of physicochemical behaviors during P/E cycles, the focus of research varies across studies, leading to significant discrepancies in observed degradation phenomena and controversies regarding the proposed mechanisms [7,16]. Notably, systematic studies on the evolution law of internal defects in charge-trapping layers remain scarce. The coupling mechanism between various degradation pathways has not been fully clarified, and the physical essence of the failure mechanism still requires verification through more systematic experimental characterization and theoretical modeling.

Herein, we focus on studying defect evolution in the charge-trapping layer. To eliminate tunnel-oxide damage interference on performance degradation, we fabricated tunnel-layer-free Au/Al₂O₃/TiO₂/p-Si memory devices, designed targeted P/E cycling protocols, and innovatively applied constant voltage stress (CVS) to the TiO₂ oxide layer. This protocol efficiently accelerates and simulates device aging under complex stress coupling. By analyzing variations in the storage window and slope of the C-V curves before and after aging, we reveal that device degradation induces changes in the concentrations of bulk defects and interface defects. Through a series of analyses and simulations, we further verify that these defects are the root cause of device degradation and elucidate the synergistic role of bulk and interface defects in the charge-trapping layer in mediating performance degradation. This work provides a solid theoretical foundation and critical technical support for the reliability optimization of CTM devices.

2. Experimental Section

2.1. Fabrication of Devices

The experiment used p-type (100) crystal orientation silicon wafers (resistivity 1~10 Ω·cm, Kejing, Hefei, China) as substrates. The 4 inch wafers were cut into 4 cm² squares, fixed on a dedicated holder, and the native oxide layer on the silicon surface was removed by immersion in 5% dilute hydrofluoric acid (HF, Aladdin, Shanghai, China) for 30 s prior to subsequent cleaning steps, followed by rinsing with deionized water for 1 min to remove residual HF. The wafers were then ultrasonically cleaned sequentially with acetone, ethanol, and deionized water (30 min each), then dried at 60 °C for 6 h. A 5-millimeter-wide polyimide tape was attached to the surface to reserve electrode areas.TiO₂ thin films were fabricated by spin-coating. Reagent bottles were ultrasonically cleaned with deionized water and ethanol, then dried at 60 °C for 5 h. A 0.2 M TiO₂ precursor was prepared by dissolving 1.702 mL of tetrabutyl titanate (Aladdin, Shanghai, China) in 10 mL of 2-methoxyethanol (Aladdin, Shanghai, China), adding 0.514 mL of acetylacetone (Aladdin, Shanghai, China) and 0.4 mL of glycerol (Aladdin, Shanghai, China), followed by magnetic stirring at room temperature for 3 h. The precursor was dropped onto the substrate, spin-coated at 3000 rpm for 30 s, immediately pre-annealed on a hot plate at 100 °C for 10 min, and finally annealed in a muffle furnace (Kejing, Hefei, China) at 600 °C for 2 h before natural cooling to room temperature. For the preparation of the 0.2 M Al₂O₃ blocking-layer precursor, 4.08 g of aluminum isopropoxide (Aladdin, Shanghai, China) was mixed with 100 mL of anhydrous ethanol (Aladdin, Shanghai, China), added with 4 mL of concentrated nitric acid (Aladdin, Shanghai, China) and 2.5 mL of acetylacetone (Aladdin, Shanghai, China), and stirred in a 70~80 °C constant-temperature oil bath for 1 h. The same spin-coating process as TiO₂ was adopted, followed by annealing at 500 °C for 5 min and natural cooling to room temperature.

The top electrode was thermally evaporated using a thermal evaporator (Jiashuo, Wuhu, China), and the bottom electrode was prepared by blade-coating conductive silver paste (Kingston, Zhuhai, China), ultimately forming the Au/Al₂O₃/TiO₂/P-Si device.

2.2. Evaluation of Device Characteristics

To investigate the performance degradation of CTM devices induced by the coupling effect of electrical stress and long-term P/E cycles, C-V curve characterization was performed via bidirectional forward-and-reverse scanning at room temperature with a frequency of 100 kHz. During the forward scan, electrons are trapped in the charge-trapping layer, resulting in a positive shift of the flat-band voltage (V_FB), which corresponds to the programmed state of the device. During the reverse scan, holes are trapped while electrons are detrapped, leading to a negative shift of V_FB, i.e., the erased state of the device.

The flat-band voltage shift is defined as the difference between the V_FB values of the device in the programmed and erased states, and it also serves as the memory window characterizing the storage capacity of the device. The magnitude of this shift increases monotonically with the increase in scanning voltage. When ∆V_FB reaches a saturated state, the interface-trap charge-storage density per unit area (N_it) can be calculated using the following Equation (1). N_it is regarded as a key performance indicator for evaluating the trapping capability of the charge-trapping layer [17].

$$N_{it}={\displaystyle \frac{C_{ox}\Delta V_{FB}}{qA}}$$

(1)

where C_ox is the capacitance of the accumulation region; q is the elementary charge of an electron; A is the effective area of the top electrode; and ∆V_FB is the flat-band voltage shift.

2.3. Physical Characterization

The crystalline phase of the materials was recorded by X-ray diffraction (XRD, Philips X’ pert Pro, Philips, Eindhoven, The Netherlands; Cu Kα, λ = 0.1541 nm), and the detailed microstructures were inspected by field-emission scanning electron microscopy (FESEM, JEOL JSM-7100F, JEOL Ltd., Tokyo, Japan) equipped with an energy-dispersive spectroscopy system. X-ray photoelectron spectroscopy (XPS, Kratos ASIX Ultra DLD-600 W, Kratos Analytical Ltd., Manchester, United Kingdom; with Al Kα as the radiation source), corrected by the peak of C 1 s, was employed to examine the chemical states of the TiO₂ surface. The surface roughness and the features of thin films were checked by atomic force microscopy (AFM, Bruker Dimension EDGE, Bruker Corporation, Billerica, MA, USA).

2.4. Finite Element Analysis

This model adopts the metal–oxide–semiconductor (MOS) structure as the device’s fundamental building block. Defects and dangling bonds at the Si–oxide interface form interface traps or surface states. These traps modulate charge transport by trapping and emitting carriers, and their net surface charge density—along with fixed charges in the functional oxide layer—also affects the device’s electrostatic characteristics. All subsequent formulas are implemented in the COMSOL 6.2 simulation module to investigate the influence of interface traps on the device’s C-V characteristic curves.

Semiconductor module

$$\nabla \cdot \left(-{ϵ}_0{ϵ}_r\nabla V\right)=\rho$$

(2)

Boundary conditions of thin insulating gates

$$n\cdot D={\displaystyle \frac{{ϵ}_{\mathrm{ins}}{ϵ}_0}{d_{\mathrm{ins}}}}\left(V+\mathsf{\Phi }-V_0+V_{\mathrm{eq},\mathrm{adj}}\right)$$

(3)

$$n\cdot J_s=0$$

(4)

$$n\cdot J_p=0$$

(5)

The trap-assisted tunneling boundary conditions used in the simulation employ continuous trap energy levels. The specific formula can be found in the “Trap-Assisted Surface-Composite Boundary-Condition Setting” Section of the Supplementary Materials.

3. Results and Discussion

Comprehensive characterization of the as-prepared TiO₂ thin films was conducted using a suite of analytical techniques. Figure 1a presents the X-ray diffraction profiles of the TiO₂ film and its supporting substrate. The diffraction peaks of TiO₂ match well with the standard reference card for the anatase phase (PDF#21-1272), and exhibit two well-resolved characteristic diffraction peaks. One peak emerges at 25.3°, corresponding to the (101) crystal plane of anatase TiO₂, while the other is located at 55.1°, assigned to the (211) crystal plane. This unequivocally confirms the formation of highly crystalline anatase-phase TiO₂. Here, we would like to provide an additional clarification: although rutile is the thermodynamically stable phase of TiO₂, in this study, the TiO₂ film prepared by the sol-gel method ultimately formed the anatase phase. Due to the thermal expansion coefficients of the silicon substrate and the TiO₂ film being 3.9 × 10⁻⁶ K⁻¹ and 2.8 × 10⁻⁶ K⁻¹, respectively, the thermal expansion difference between them generated residual stress at the interface between the film and the substrate. As the annealing temperature increased, this stress gradually accumulated. Excessive residual stress is not suitable for the fabrication of devices. On the other hand, as the temperature rises, the grain size gradually increases, eventually leading to significant changes in the surface roughness of the film. However, the 600 °C annealing process adopted in this study precisely controlled the moderate growth of the grains, avoiding the deterioration of surface roughness caused by excessive grain growth. It is worth noting that the higher deposition temperature required to form the anatase phase enhances the reaction between the high-dielectric-constant material and the substrate, thereby forming titanium silicate at the interface, which will seriously damage the charge-storage performance of the device. Therefore, from the perspective of device functionality requirements, the process window selected in this study also tends to stabilize the anatase phase.

Atomic force microscopy (AFM) was utilized to characterize the surface morphology of the TiO₂ film. As illustrated in the 2D AFM micrograph in Figure 1b, the film surface is homogeneous and smooth with a vertical height variation ranging from 0.20 to 6.87 nm, suggesting low surface roughness. The 3D AFM image in Figure 1c further reveals a continuous and uniform film topology. This favorable morphology enhances interfacial contact, suppresses the formation of interfacial voids, and facilitates the subsequent deposition of the barrier layer, thus laying a solid foundation for the fabrication of high-performance devices. To clarify the chemical-composition and elemental-valence-state characteristics of the TiO₂ thin film, XPS was employed for characterization. Figure 1d shows the survey XPS spectrum of the TiO₂ thin film, where distinct characteristic peaks of Ti 2p and O 1s are clearly observed, along with a weak C 1s peak. The C 1s peak originates from adsorbed carbon contamination in the testing.

Environment and trace residues during sample preparation were used as a reference for the subsequent binding-energy calibration. The distinct and intense characteristic signals of the Ti and O elements confirm that the main component of the film is TiO₂. As shown in Figure 1e, the spectrum exhibits a typical doublet structure: the peak at 458.7 eV corresponds to the Ti 2p_3/2 orbital, and the peak at 464.4 eV is assigned to the Ti 2p_1/2 orbital. The binding energy difference between the two peaks is approximately 5.7 eV, which is consistent with the characteristic peak positions and peak separation of Ti⁴⁺ in TiO₂, indicating that the valence states of Ti in the film dominantly consist of tetravalence. Additionally, a weak satellite peak appears at ~457.5 eV, which is the characteristic signal of Ti³⁺ [18]. To quantify the stoichiometric defect degree, we performed Lorentz–Gaussian mixed fitting on the Ti 2p spectrum, and the results show that the relative content of Ti⁴⁺ is 94.2% and Ti³⁺ is 5.8%, corresponding to a Ti⁴⁺/Ti³⁺ ratio of ~16.2:1. This confirms the coexistence of Ti³⁺ and Ti⁴⁺ states in the TiO₂ thin film, directly reflecting the in situ formation of Ti³⁺ defects and oxygen vacancies during the crystallization of the anatase phase [19,20,21]. The underlying formation mechanism can be attributed to the partial reaction process of Ti-OH groups: during the high-temperature annealing treatment, the Ti-O-Ti network in the TiO₂ thin film undergoes crystallization and reconstruction to form the anatase-phase lattice, while the terminal Ti-OH groups on the film surface undergo desorption through a dehydration reaction, breaking the local stoichiometric balance and inducing the formation of Ti³⁺ defects [22]. To further clarify the chemical environment of oxygen in the TiO₂ thin film, peak deconvolution was performed on the high-resolution O 1s spectrum shown in Figure 1f, and the fitting results resolved into three symmetric characteristic peaks. Among them, the peak at ~529.5 eV is assigned to lattice oxygen bonded by Ti-O covalent bonds in the TiO₂ lattice, which is the main existing form of oxygen in the film. The peak at ~532.5 eV originates from hydroxyl (-OH) groups physically adsorbed or chemically bonded onto the film surface, which is usually associated with the deposition process or the water-vapor adsorption process when the sample is exposed to air [22,23]. The peak at ~531.5 eV corresponds to oxygen vacancy defects [24], whose appearance further confirms the presence of oxygen vacancies in the film.

The as-prepared TiO₂ thin film acts as the core functional layer of charge-trap memory devices. Au electrodes were deposited by thermal evaporation subsequent to barrier-layer fabrication. Material characterization details of the Al₂O₃ barrier layer are available in the “Characterization of Al₂O₃ Material” Section of the Supplementary Materials, while the full fabrication procedures are described in the Experimental Section. This process yields a Au/Al₂O₃/TiO₂/p-Si charge-storage device, as illustrated in Figure 2a. The cross-sectional SEM micrograph of the device in Figure 2b confirms relatively uniform thicknesses of individual functional layers, with distinct interfaces establishing a robust structural basis for subsequent performance characterization. PL spectroscopy was employed to further investigate defect states in the TiO₂ film. Under 320 nm excitation, the PL spectrum of TiO₂ annealed at 600 °C exhibits characteristic peaks in the energy ranges of 2.64 to 2.66 eV and 2.80 to 2.93 eV, as presented in Figure 2c. The band gap energy of the TiO₂ film is approximately 3.4 eV, calculated from the XPS data in Figure 2d, meaning that the PL peak energies are considerably lower than the band gap.

Direct band-to-band recombination, therefore, cannot explain these emission peaks. Instead, the multiple PL peaks originate from intrinsic defect states and exciton transitions of anatase TiO₂. Peaks at 422 nm, 442 nm, 465 nm, and 469 nm, corresponding to energies of 2.93 eV, 2.80 eV, 2.66 eV, and 2.64 eV, respectively, are associated with defect states, such as oxygen vacancies and Ti³⁺ centers, as well as band-edge emission or recombination from defect states to the valence band or from donor-to-acceptor defect states. These results confirm that the TiO₂ film contains a high density of defect states, which form the critical core of non-volatile memory by efficiently trapping and retaining charge carriers for long-term storage. Theoretical simulations of defect energy levels indicate that defect states in TiO₂ are predominantly donor levels rather than acceptor levels. Consistent with this, the strongest PL peak at 2.65 eV in Figure 2c is attributed to recombination from a donor state located 2.65 eV above the valence band maximum to the valence band of the TiO₂ film. A plausible mechanism involves electrons being excited to the defect state 2.65 eV above the valence band maximum, before recombining with holes in the valence band to produce luminescence. Collectively, these results suggest that the main defect state is located 2.65 eV above the valence band, as depicted in Figure 2e. The charge-storage mechanism is illustrated via an energy band diagram with charge-trapping and -detrapping processes shown in Figure 2e,f. Effective charge trapping in the CTM device is, thus, rationalized by charge transfer between defect states in the TiO₂ layer and the silicon substrate.

To elucidate the synergistic regulation of P/E cycles and electric field stress on device endurance and structural evolution, P/E cycle tests without additional stress were conducted. Figure 3a shows the device’s C-V curves after long-term P/E cycling, revealing severe consistency degradation and memory-window distortion, including a slight rightward shift of the programmed-state curve and a marked slope reduction in the erased-state curve. Figure 3b shows that as the number of P/E cycles increases, V_FB undergoes significant changes. V_FB is mainly determined by the work function of the metal and the charge state of the charge-trapping layer [25]. For the devices described above, with the same electrodes, the metal work function is the same, and there are a large number of traps in the charge-trapping layer. In summary, this change is mainly due to the imbalance of electron and hole injection in the oxide layer during the cycling process. This charge imbalance induces the memory window’s initial increase then decrease trend, summarized in Figure 3c. The primary cause of these phenomena is TiO₂ charge-trapping-layer bulk-defect evolution from repeated P/E cycling. Degraded oxides generate abundant defects, such as oxygen vacancies, silicon dangling bonds, and impurity ion traps, which form conductive paths triggering abnormal charge-carrier tunneling or drift. Consistent with this mechanism, the stability characteristics of the high- and low-state capacitances presented in Figure 3d exhibit a slight upward tendency in the high-state capacitance following multiple P/E cycles. This increment mainly derives from interface-state defect capacitance, which forms a parallel structure with accumulation-region capacitance during oxide degradation, leading to elevated high-state capacitance. Moreover, the degradation exhibits voltage–time cumulative characteristics, with defects continuously accumulating during charge-carrier trapping–detrapping cycles, potentially inducing time-dependent dielectric breakdown (TDDB) failure. To verify the electrical-stress-accumulation characteristic of P/E cycle-induced TiO₂ charge-trapping-layer bulk-defect evolution, an accelerated experiment was designed for verification. Figure 4a shows the C-V measurement pulse-timing diagram, with the experiment configured by varying Th (constant voltage-stress time applied during each cycle). Figure 4b indicates that, without CVS, the pulsed stress accumulation rate during P/E cycling is slow, leading to moderate oxide-degradation kinetics. To confirm the dominant role of electrical stress, a constant high voltage was pre-applied to the device before P/E cycling, as shown in Figure 4c. This pre-stressing strategy significantly enhances electrical-stress accumulation efficiency, thereby accelerating oxide degradation, consistent with the proposed stress accumulation hypothesis. A full P/E cycle involved applying 8 V for 10 s, followed by C-V scanning.

After 200 cycles, the C-V curve profile is comparable to that without pre-applied CVS (Figure 4d), while the cycle count for comparable degradation is significantly reduced, directly confirming accelerated degradation by pre-applied CVS. The variation trends of programmed-/erased-state V_FB and ΔV_FB are consistent with CVS-free conditions, with the key difference being an expanded memory window after CVS application (Figure 4e,f). This enhancement is attributed to increased TiO₂ bulk-trap density at a certain stress degradation stage, which provides more effective charge-trapping sites, improving device storage capacity. In addition to elevated bulk-trap density, the interface-trap density growth rate is significantly higher than that without CVS. Figure 4g shows a more pronounced increment in high-state capacitance after approximately 200 cycles. This is rationalized by interface state defect capacitance forming a parallel structure with the accumulation region capacitance during oxide degradation, leading to increased high-state capacitance.

Both CVS-induced bulk and interface defects exhibit irreversibility. Figure 4h presents memory window data under three conditions of no voltage stress (Th = 0 s), 200 P/E cycles, with pre-applied 8 V CVS (Th = 10 s) and post-CVS withdrawal cycling. The stress-free condition shows a smaller memory window with regular curves, while stress-assisted cycling results in a significantly expanded memory window and severe curve distortion, especially for the erased state. Withdrawing pre-applied stress leads to negligible memory-window change but substantial alleviation of curve distortion and slight reduction in oxide capacitance. These results confirm that most stress-induced interface traps are irreversible, and bulk traps are almost fully non-recoverable, consistent with the irreversible nature of oxide defects under high electrical stress. Prolonged electrical stress may induce TDDB in the device. The apparent late-cycle bulk-trap density reduction is misleading as continuous bulk-trap accumulation (e.g., oxygen vacancies) facilitates formation of micro-conductive paths and percolation channels in the TiO₂ layer. Figure 4i shows device leakage current characteristics pre- and post-cycling, revealing a significant leakage current increase after cycling, consistent with stress-induced leakage current or soft breakdown (SB) during oxide degradation. Prolonged stress may lead to hard breakdown (HB) after SB, as percolation channels expand into continuous conductive paths across the TiO₂ oxide layer. Detailed device breakdown data are available in the Supplementary Materials.

To clarify that stored charges originate mainly from bulk traps rather than interface traps in the charge-trapping layer, verification is achieved by leveraging the frequency dependence of interface traps [25]. Figure 5a shows stress-free C-V curves at different frequencies, with good morphological consistency across the tested range and decreasing C_OX with increasing frequency. This behavior stems from oxide traps, such as vacancies and Si/oxide interface states in high-k oxides [26]. Low-frequency AC signals enable full interface state response and charge exchange, while high frequencies reduce interface state contribution to C_OX [27]. Both interface and bulk traps induce C-V hysteresis, but memory windows vary significantly below 400 kHz and show minimal discrepancies above 400 kHz under the same scanning voltage (Figure 5b). G-V measurements at different frequencies were conducted to distinguish trap types via energy level distributions. According to the classic model by E. H. Nicollian, interface state conductance peaks localize near the depletion region flat-band voltage.

Peaks associate with inversion-region charge-trapping–detrapping energy loss [28]. Figure 5c shows dual conductance peaks near flat-band voltage and the inversion region, confirming the coexistence of interface and bulk traps. Figure 5d displays prominent interface state conductance peaks below 400 kHz [28]. Interface states compete for charge carriers, reducing bulk-trap charge trapping and the memory window at low frequencies. The small peak amplitude and minimal memory window variation at 1 MHz, where interface state contributions are negligible, indicate that stored charges predominantly originate from bulk traps, with interface states exerting limited influence [29]. To elucidate electrical stress accumulation effects on device performance, Figure 5e shows C-V curves with the constant voltage duration varied from 0 s to 10 s. The inversion region slope of the C-V curve shows Th-dependent variation, with the upper-half slope decreasing and the lower-half slope remaining nearly unchanged as Th increases, except for Th = 0 s. The upper inversion-region slope is governed by donor energy levels, and the lower half by acceptor energy levels [30]. The decreasing upper-half slope with increasing Th indicates rising donor-type interface state density, while the invariant lower-half slope implies negligible acceptor-type interface state density change. This reveals selective enhancement of donor-type defects under electrical stress. The classic interface state-charge coupling model is adopted to explain this phenomenon, positing distinct charge occupancy dynamics for donor-type and acceptor-type interface states [30]. Donor-type interface states are positively charged when unoccupied, releasing electrons while remaining positively charged when the Fermi level is below their energy level (E_d). Acceptor-type interface states are neutral when unoccupied, trapping electrons to become negatively charged when gate voltage elevates E_F above their energy level (E_a). This behavior modulates the dielectric-layer electric-field distribution, altering the C-V curve.

Charge-trapping/-detrapping dynamics correlate with C-V shifts as follows. Negative-gate-voltage scanning injects net holes, inducing a leftward C-V shift and reducing V_FB. Positive-gate-voltage scanning injects electrons, inducing a rightward shift and increasing V_FB. Rising Dit–donor density enhances net hole trapping, amplifying the leftward shift during negative scanning, while occupied Dit–donor states are neutral, minimizing the rightward shift during positive scanning. These effects induce an overall leftward C-V shift, with the magnitude scaling with Dit–donor density. This explains the negative V_FB shift of the programmed curve observed in Figure 5e,f, with shift magnitude scaling linearly and with Th confirming Dit–donor dominance in modulating device electrostatics.

To systematically clarify the distinct contributions of Dit–donor and Dit–acceptor to the curve slope, subsequent analyses proceed in three interrelated stages: theoretical modeling for underlying physics, rigorous validation via mathematical derivation, and visual confirmation through finite element simulations. This multi-dimensional verification ensures the proposed mechanism’s reliability. When the applied V_G is negative, the E_F is defined as the energy level, with an electron occupancy probability of 1/2. Defect levels higher than E_F significantly reduce electron occupancy probability at Ed, leading to positive charging of donor states. These positive interface state charges compensate for partial negative charges on the metal electrode, weakening band bending and hole accumulation. Conversely, positive V_G increases electron occupancy probability at E_d, resulting in negative charging of acceptor-type interface states. These negative charges similarly compensate for partial negative charges on the metal electrode, weakening band bending and electron accumulation while retarding inversion layer formation (Figure 6a,b). This charge compensation effect reduces the rate of capacitance variation, with voltage manifesting as a decreased C-V curve slope (Figure 6c). Collectively, the analysis demonstrates interface states exhibit a charging–discharging effect with applied bias, confirming increased interface states in charge traps.

Memory devices are displayed under the coupling of electrical stress and long-term P/E cycles [31]. Nevertheless, while the aforementioned theoretical analysis initially confirms increased interface state density from the coupling of electrical stress and long-term P/E cycles, further clarification of the quantitative correlation between the C-V curve slope and interface states is required. The intrinsic relationship between these parameters is systematically established via mathematical derivation based on ideal and non-ideal MIS device models (Figure 6d,e). Detailed formula derivation is provided in the Supplementary Materials Section on slope formula derivation under the interface state effect. Meanwhile, finite element simulations were conducted to investigate the influence of interface-trap energy-band distribution on device performance and support the in-depth experimental data analysis. The device structure was drawn and meshed to meet simulation requirements, followed by material parameter import and configuration of core simulation models, including the energy band model, carrier mobility model, recombination model, and trap model. The trap-assisted surface recombination boundary condition was specifically adopted to simulate trapped-charge effects and carrier-trapping emission processes. Further analysis focused on the specific impacts of different interface-trap types on the same device’s electrical performance.

A simple MOS structure was used as the simulation device model (Figure 7a). As a fundamental unit of silicon planar devices, the Si–oxide interface defects and dangling bonds form interface-trap surface states. These traps affect charge transport via carrier trapping and emission, and their net surface charge density affects device electrostatic characteristics [32]. Figure 7b shows that the increase in the donor-type interface state density leads to a gradual flattening of the transition region of the C-V curve from the accumulation region to the depletion region. Similarly, Figure 7c demonstrates that during the transition from the depletion region to the inverse region of the C-V curve, the increase in the acceptor-type interface state density causes the C-V curve to be “stretched”. These simulation results align with previous theoretical and mathematical derivation conclusions, unequivocally confirming that interface states flatten the C-V curve transition region, with the flattening trend becoming more pronounced as interface state density increases.

Oxide-layer defects share commonalities in types and basic characteristics, enabling similar research paradigms, but exhibit distinct individual differences due to material composition, preparation processes, and application scenarios, requiring case-specific analysis. Academically, it is widely accepted that oxide-layer charges mainly fall into four categories (Figure 8a), with universal basic characteristics applicable to various oxide semiconductor structures, including high-k oxides. TDDB denotes gate oxide breakdown under an electric field below the intrinsic breakdown strength [33]. Devices undergo catastrophic breakdown after an incubation period under voltage or temperature stress. Its core mechanism involves gradual defect nucleation, propagation, and agglomeration in the oxide layer during stress, eventually forming a continuous conductive percolation path across the dielectric.

Reliability requires TDDB lifetime testing of a statistically significant number of MOS capacitors or transistors to ensure data validity. In this study, the coupling of electrical stress and long-term P/E cycles induces device performance degradation accompanied by a memory window that first expands then shrinks. This reflects dynamic bulk-defect evolution: early degradation sees continuous bulk trap generation and accumulation—enhancing charge-trapping capacity to expand the memory window—while subsequent shrinkage is likely due to bulk-defect agglomeration into interconnected leakage paths, impairing charge retention and reducing the effective trapped-charge density. Figure 8b shows that the breakdown process initiates from pre-existing defect precursors (P) in the TiO₂ layer, with oxygen vacancies (Vo) recognized as dominant precursors in TiO₂-based dielectrics. A defect precursor P trapping two electrons reduces local bond order, significantly weakening adjacent Ti-O bonds. Synergistic electric field and thermal activation trigger Ti-O bond dissociation, forming Frenkel pairs, neutral oxygen vacancies (primary defect-assisted charge transport centers in dielectrics [34]), and oxygen ions (O²⁻) [35]. Newly generated Vo enhances leakage current and acts as new defect nucleation sites [36]. The trapping of two additional electrons by nascent Vo (forming Vo^2-) distorts the local electric field, promoting neighboring Ti-O bond dissociation and new Vo formation, constituting a self-sustaining autocatalytic defect evolution cycle. In TiO₂ systems, Vo plays a dual role in TDDB, acting as both a leakage-enhancing defect accelerating degradation and a precursor fueling further defect generation. Prolonged electric field stress drives continuous Vo-mediated defect propagation to the percolation threshold, triggering irreversible TDDB failure [37,38]. This work’s theoretical analysis of formula derivation and finite element simulations mutually confirm that the core device-degradation mechanisms under coupled electrical stress and long-term P/E cycles lie in synergistic nucleation and evolution of interface and bulk traps. Increased bulk-trap density elevates TDDB susceptibility and amplifies SILC, with these two factors synergistically deteriorating device electrical performance.

Previous studies confirm that coupled electrical stress and long-term P/E cycles induce device degradation, with interface state generation and evolution as a core cause [2,3,4]. Figure 8c shows that direct contact between high-k materials, such as TiO₂ and silicon substrates, thermodynamically favors interfacial reactions like oxidation and hydrolysis, forming a low-k transition layer mainly composed of amorphous SiO₂ or silicate [39]. This layer reduces the effective dielectric constant of the stacked structure, undermining high-k materials’ core advantage in leakage suppression and serving as an interface defect reservoir. Additionally, coupled electrical stress and long-term P/E cycles further degrade the transition layer, with bond cleavage and rearrangement generating additional interface defects such as silicon dangling bonds and oxygen vacancies, ultimately worsening electrical performance. Figure 8d illustrates interface state formation and evolution mechanisms under coupled stress, which can be elaborated on via dynamic Si-H bond cleavage and reconstruction. Negative-bias electric fields induce field-assisted dissociation of Si-H bonds (a bond energy of ~3.1 eV), forming hydrogen vacancies and silicon dangling bonds (Si•) [40]. Si• generation directly increases interface state density, enhancing hole trapping and exacerbating the threshold voltage drift. Dissociated hydrogen species (H⁺ or H•) exhibit high reactivity, tending to recombine into H₂ gas and desorb from the gate electrode on the one hand, and diffuse within the oxide layer, undergoing defect-mediated migration and potentially recombining with other Si• to form new Si-H bonds (Si-H bond reconstruction) on the other. Although Si-H bond reconstruction partially restores interface passivation and mitigates degradation, it fails to fully offset irreversible damage from initial bond cleavage, leading to a net Dit increase over repeated P/E cycles.

Further theoretical speculation and experimental evidence indicate that Si• defect energy levels lie near the silicon mid-gap, approximately 0.5 to 0.7 eV above the valence band maximum, and are energetically closer to the valence band. This favorable alignment facilitates hole trapping from the valence band equivalent to electron acceptance, rendering Si• acceptor-type traps. Combined with the previous device electrical characteristic analysis, acceptor-type interface states exert a more significant regulatory effect on device performance than donor-type counterparts [41]. In summary, dynamic Si-H bond cleavage and incomplete reconstruction, accompanied by acceptor-type interface state nucleation and accumulation, constitute one of the core mechanisms underlying device performance degradation after prolonged P/E cycles [6].

4. Conclusions

This work systematically investigates the performance degradation mechanisms of the Au/Al₂O₃/TiO₂/p-Si charge-trap memory under the coupling effect of P/E cycles and CVS. Device degradation is dominated by the synergistic evolution of bulk and interface defects. Specifically, oxygen vacancies in TiO₂ function as defect precursors, forming Frenkel pairs under electric field stress to promote self-sustaining defect accumulation, whereas electric-field-induced cleavage of interfacial Si-H bonds causes a net increase in the acceptor-type interface state density. These defects collectively induce threshold voltage drift, memory window distortion, and enhanced leakage current, ultimately triggering time-dependent dielectric breakdown. This study elucidates the synergistic mechanism of stress-induced bulk defects and interface defects in the reliability degradation of CTM, providing critical theoretical support for optimizing manufacturing processes to enhance the long-term stability of high-density CTM devices.