Recent Applications of Focused Ion Beam–Scanning Electron Microscopy in Advanced Packaging

Abstract

Advanced packaging represents a crucial technological evolution aimed at overcoming limitations posed by Moore’s Law, driving the semiconductor industry from two-dimensional toward three-dimensional integrated structures. The increasing complexity and miniaturization of electronic devices have significantly heightened the challenges associated with failure analysis during process development. The focused ion beam–scanning electron microscope (FIB-SEM), characterized by its high processing precision and exceptional imaging resolution, has emerged as a powerful solution for the fabrication, defect localization, and failure analysis of micro- and nano-scale devices. This paper systematically reviews the innovative applications of FIB-SEM in the research of core issues, such as through-silicon-via (TSV) defects, bond interfacial failures, and redistribution layer (RDL) electromigration. Additionally, the paper discusses multimodal integration strategies combining FIB-SEM with advanced analytical techniques, such as high-resolution three-dimensional X-ray microscopy (XRM), electron backscatter diffraction (EBSD), and spectroscopy. Finally, it provides a perspective on the emerging applications and potential of frontier technologies, such as femtosecond-laser-assisted FIB, in the field of advanced packaging analysis.

1. Introduction

The exponential growth of information technology has driven electronic devices toward high performance, miniaturization, and low power consumption. Consequently, device design, functionality enhancement, and materials research have become central topics in semiconductor development. Advanced packaging technologies, such as flip chips, bumping, wafer-level packaging (WLP), 2.5D packaging (interposers and redistribution layers), and 3D packaging (through silicon vias (TSVs) and through glass vias, (TGVs)), are key drivers for improving the functionality and diversification of high-end semiconductor products [1,2,3,4,5]. However, device miniaturization is directly correlated with increased complexity in failure analysis and reverse engineering. With TSV diameters continually shrinking, aspect ratios increasing, and hybrid bonding pitches reducing to the sub-micro level, traditional analytical methods face significant challenges, including (1) the precise localization of internal defects within complex three-dimensional structures, (2) insufficient understanding of nano-scale interfacial failure mechanisms, and (3) limited capabilities in characterizing thermomechanical stress within multi-material structures [6,7,8,9]. Accurate characterization methods and prompt feedback on structural process changes are essential to improve device yields and reduce manufacturing costs.

FIB-SEM technology integrates precise gallium ion beam etching (with ion beam resolutions of <2.5 nm) and high resolution FESEM imaging (with secondary electron resolutions of <0.6 nm), thus allowing material etching, deposition processing, and imaging functionalities. By taking advantage of its capabilities in morphological characterization, targeted processing, in situ analysis, and three-dimensional reconstruction, FIB-SEM has expanded from its initial use in failure analysis to encompass the entire process development cycle [10,11,12]. It has become a key tool for optimizing TSV-filling processes, assessing bonding interface quality, and elucidating electromigration mechanisms [13,14]. In TSV processes, FIB can directly expose the TSV structure through cross-sectioning, enabling the observation of copper-filling uniformity, voids, cracks, or over-plating issues, using ion beam imaging (e.g., combined with SEM). In bond interfacial failure analysis, FIB can precisely cut bonding interfaces (such as Cu-Cu hybrid bonding or solder interfaces), revealing micro/nano-scale delamination, voids, or intermetallic compound (IMC) anomalies. Oxygen contamination, fluorine residues, or electrochemical migration at the bonding interface can be identified using FIB-EDS coupled with spectroscopic techniques. In RDL processes, FIB’s high-resolution imaging can verify whether the critical dimensions (CDs) of RDL patterns meet design specifications, particularly for detecting overlay misalignment in multilayer stacking. FIB can locally remove the passivation layer above the RDL to expose metallic line defects (e.g., electromigration-induced open circuits or lithography-residue-induced short circuits) and repair interconnects via ion beam deposition. Cracks or voids in the interlayer dielectric materials of RDLs can be quickly located through FIB cross-sectioning combined with electron imaging. In summary, this article focuses on the innovative applications of FIB-SEM in advanced packaging, with the aim of providing technical references for the industry.

2. Evolution of Advanced Packaging Technologies and Characterization Challenges

Since the 1990s, packaging technology has undergone three revolutionary breakthroughs: ➀ 2.5D Packaging: Utilizing silicon interposers and RDLs to achieve horizontal, high-density interconnects for multiple chips, increasing the interconnect density to the order of 10⁴ interconnections/mm² and reducing the RDL linewidth to 2 μm. Although 2.5D packaging enables higher interconnect densities without increasing package sizes, RDLs remain constrained by substrate dimensions [15]. ➁ 3D Packaging: Employing TSV and TGV technologies to vertically stack heterogeneous chips with different functions, reducing interconnect distances to the micrometer scale and cutting the signal delay by 90 percent. The TSV vertical interconnect density has surpassed 10⁶ interconnections/mm². Figure 1 illustrates structural comparisons between 2.5D- and 3D-packaged chips, highlighting the higher spatial efficiency and compactness achievable through 3D methods [16]. ➂ Heterogeneous Integration: In 2016, the Institute of Electrical and Electronics Engineers (IEEE) and the International Semiconductor Industry Association (SEMI) jointly supported and initiated the release of the heterogeneous integration roadmap (HIR) [17]. This roadmap outlined the challenges in the field of future system integration technologies and proposed corresponding technical pathways: system-in-package (SiP), wafer-level packaging (WLP), and 3D interconnects. These approaches aim to enhance the overall system performance by integrating devices of different types and manufacturing processes without relying on traditional process scaling. For example, integrating logic chips and memory in a heterogeneous manner can shorten data transmission paths, reduce latency, and increase data throughput. In 2011, the TSMC introduced the CoWoS (chip-on-wafer-on-substrate) process based on 2.5D-packaging technology, providing solutions for high-performance products, like GPUs and FPGAs. NVIDIA’s GP100 and Google’s TPU 2.0 chips both adopted the CoWoS process. In 2019, Intel launched the TSV-based 3D Foveros technology, which uses a face-to-face chip-to-chip bonding process, treating the chip as an active interposer connected to upper and lower layers through TSVs [18]. This technology has been successfully applied to the Ponte Vecchio chip in Intel’s MAX-series GPUs. In 2020, Intel combined 2.5D EMIB (Embedded Multi-Die Interconnect Bridge) and 3D Foveros packaging technologies to release the high-performance GPU chip “Lakefield” [19,20]. Clearly, 2.5D/3D integration processes are playing an increasingly vital role in artificial intelligence and high-performance computing fields.

Despite the leap in chip performance achieved through technological breakthroughs, advanced packaging technologies still face multiple challenges. For instance, in 3D interconnection processes (such as TSV and TGV), issues like insulation layer damage [4,5], uneven dielectric layers, and electroplating filling defects can lead to yield reduction in advanced packaging processes [21,22,23]. In the bumping process, problems such as irregular bump shapes, excessive height differences, or poor connections with other components may cause instability in electrical performance and increase interference during signal transmission [24], thereby affecting the normal operation of the chip in subsequent uses. Poor bonding quality in flip-chip, interposer, and RDL processes, such as voids at bonding interfaces, insufficient interatomic bonding forces, or mismatched bonding materials, may lead to failures in internal circuit connections of the chip, resulting in signal transmission interruptions or errors, ultimately causing declines in the yields of packaged products [25,26,27]. These issues urgently require advanced characterization methods to achieve the non-destructive testing of three-dimensional structures, precise location of nano-scale defects, and in situ observation of dynamic processes. Only after a comparative analysis of interfacial structures under different process parameters can the optimal process conditions be identified, thereby improving the quality and efficiency of integration, enhancing the yield of process devices, and reducing the cost of wafer fabrication.

3. Core Applications of FIB-SEM in Advanced Packaging

3.1. Optimization of TSV/TGV Processes

Through-silicon-via (TSV) technology is widely adopted in three-dimensional integrated circuits, facilitating chip stacking and significantly improving the input/output (I/O) density and signal transmission performance [28]. In applications such as power amplifiers, traditional methods for reducing emitter inductance include wirebonding and flip-chip connections. Wirebonding (Figure 2a), though cost intensive, can suffer from poor contacts, leading to increased inductance. Conversely, flip-chip packaging (Figure 2b) enhances electrical performance but compromises thermal management because of the lower thermal conductivity of solder compared to those of the silicon substrates used in wirebonding. The introduction of TSV technology (Figure 2c) addresses these issues by effectively reducing inductance while preserving low-cost manufacturing and optimal thermal performance [29]. However, TSV fabrication processes are complex. Defects such as incomplete filling and voids in TSV blind holes negatively affect signal transmission efficiencies and yields.

Copper is commonly used for TSV filling because of its high electrical conductivity and excellent compatibility with multilayer interconnect processes. The substantial mismatch in the coefficients of thermal expansion (CTEs) between copper and silicon introduces significant thermomechanical stresses, leading to structural performance degradation. Particularly after thermal shock, the volume of copper increases and separates from the silicon substrate, accumulating interfacial shear stress, which leads to cracking within the TSV, ultimately causing TSV failure. To mitigate this stress, Dou et al. combined FIB and EBSD and found that cracks caused by CTE mismatch primarily propagate along Cu grain boundaries and that irregular Cu grains have the ability to hinder crack propagation [30]. Controlling the growth of irregular Cu grains poses a challenge for the electroplating process. Alternatively, annealing can relieve stress but may exacerbate copper protrusion, aggravating interfacial friction and posing reliability risks [31,32]. Li et al. investigated the structural changes in TSVs at different annealing temperatures and found that longer heating times result in greater copper protrusion. The Cu grains in TSVs are related to the thermal behavior, with grain size increasing as the thermal exposure time increases, although the grain orientation remains unchanged. This provides a theoretical basis for optimizing annealing conditions in TSV processes to enhance structural reliability [33]. Zhang and colleagues have also effectively corroborated this point through the application of an FIB. The electroplating-prepared TSV structures exhibited numerous micropores and cracks at the Cu/TiW interface (Figure 3a,b). Thermal cycling led to an increase in the dislocation density and a reduction in the grain diameter of TSV-Cu (Figure 3c,d). Annealing resulted in further interfacial cracking, which released residual stresses and increased the grain diameter of TSV-Cu (Figure 3e,f) [34]. Additionally, previous studies have shown that increasing the thickness of the SiO2 insulating layer can reduce the thermomechanical stress [35,36]. However, because of the unique stress distribution in TSV structures, the reduction in the thermomechanical stress is not linearly related to the thickness of the SiO₂ insulating layer [37]. Liu et al. combined finite-element-analysis (FEA)-based stress simulation and FIB-based characterization to study the effects of the thickness of the liner layer between Cu and Si (THKliner) and the thickness of the interlayer dielectric layer (THKILD) on the thermomechanical stress of TSV structures [38]. They proposed that setting the THKliner to 0.4 μm and the THKILD to 1.0 μm can significantly reduce the thermal stress, thereby improving the structural stability. These insights directly address practical engineering challenges in 2.5D/3D advanced packaging [38].

The composition of the electroplating solution is complex, and in situ microscopy in the electroplating process can provide direct experimental evidence for the development of high-performance electroplating solutions. FIB-SEM has the advantage of in situ observation after cross-section preparation, allowing for the convenient and effective real-time tracking of the morphological evolution during the growth of Cu pillars and facilitating mechanism research. Beyne et al. utilized a two-component chemical electroplating solution to inhibit the growth of Cu on the sidewalls and openings during the bottom-up growth of Cu pillars, achieving void-free Cu through-hole filling. By employing FIB cutting followed by SEM observation, they examined the morphological changes in Cu pillars within the holes at different electrochemical deposition times [39]. The results showed that with increasing electrochemical deposition time, the Cu pillars demonstrated excellent bottom-up growth while maintaining open tops, showcasing superior filling quality and stability. To enhance the stability of the electrochemically deposited Cu pillars and remove residual chemical impurities from the deposition process, high-temperature annealing was performed prior to CMP (chemical mechanical polishing). After annealing, defects within the TSV holes were further reduced, and a partial crystallization of Cu was achieved. This research provides a critical process window for high-density TSV design. Crystalline copper, characterized by high strength, high electromigration resistance, and high conductivity, is a strong candidate material for through-holes in next-generation high-density TSV processes. Currently, researchers have preliminarily achieved the controllable preparation of nano-twinned structures by adjusting the electrolyte formulation and DC electrodeposition process parameters. Utilizing in situ characterization and real-time observation techniques, they have conducted detailed observations and analyses of the morphological changes in and structural evolution of nano-twinned copper during through-hole growth, offering new possibilities for high-density through-hole interconnection processes [40,41]. By adjusting the electrolyte formulation and the parameters of the direct current electrodeposition process, the controllable fabrication of nano-twinned structures has been achieved. Figure 4 demonstrates the application of FIB cross-sectioning to characterize nano-twinned Cu in TSVs, RDLs, and Cu-Cu hybrid bonding, providing robust evidence for the use of nano-twinned structures in high-density interconnection processes [42,43,44].

Glass materials possess excellent insulation properties, low loss factors, low dielectric constants, high dimensional stability, and adjustable thermal expansion coefficients, making them highly promising for applications in radio frequency chips, micro-electromechanical system sensors, high-density system integration, and other fields [45,46,47]. Compared to TSV technology, TGV technology eliminates the need for an insulation layer preparation step because of the inherent insulating properties of the glass. This shifts the technical challenges of TGV to the processes of hole formation and filling. Similar to TSV hole filling, the electrodeposition of copper is commonly used to achieve TGV through-hole filling. Vertical TGV through-holes typically employ a high-acid, low-copper system for filling. When various organic additives are introduced to the electroplating solution, the distribution of the current density changes, causing the deposition rate at the center of the through-hole to be faster than that at the opening. This results in a butterfly-wing-shaped cross-section, known as the butterfly-filling technique, enabling the void-free filling of the through-holes [48,49]. Research on the regulation of basic plating solutions, additives, leveling agents, and the convective adsorption behavior in the electrolyte is a primary direction for achieving high-quality metal-filled TGV technology.

In addition to levelers, FIB-SEM also holds application prospects in studying the synergistic effects of inhibitors and accelerators [50,51]. To achieve the void-free and rapid filling of through-holes, FIB-SEM was utilized to obtain cross-sectional and surface morphological images of electroplated copper at different current densities and with different inhibitors, accelerators, and levelers at varying ratios to investigate the synergistic effects of inhibitors and accelerators [52]. The results revealed that when the ratio of inhibitor A, accelerator B, and leveling agent C was 50:1:1.25, the through-holes could be perfectly filled within 2.25 h at 1 ASD. As the electroplating current density was increased, the grain size of the copper gradually decreased, as the increased overpotential promoted the formation of nuclei. Further adjusting the ratio of A, B, and C to 60:1:1 enabled the electroplating to be completed within 1.5 h at 1.5 ASD, with excellent plating quality and uniformity.

Additionally, residual stress generated in the metal layer during the electroplating process can lead to the delamination of the glass–metal layer and glass cracking, which are two of the main technical bottlenecks in TGV. Shi et al. prepared several different Cu coatings on glass substrates by adjusting the current density, accelerator, inhibitor, and leveler ratios during the electroplating process [53]. XRD analysis revealed that these Cu coatings contained crystal orientations of (111), (200), (220), and (311), with the residual stress in the coatings being positively correlated with the content of the (111) crystal orientation. The following observations were effectively made utilizing FIB: (1) After annealing, the (220)-crystal-oriented grains in the Cu coating underwent recrystallization, and as the grain size increased, the residual stress decreased. (2) The microstructure of the (111) Cu grains showed almost no change before and after annealing, likely because of the presence of a large number of low-grain-boundary-energy nano-twins within the Cu film. These results further confirm that the controllable preparation of twin structures may be a core direction for high-density interconnection technology.

3.2. The Reliability Assessment of the Process

In the progress of integrating components, such as image sensor arrays, signal-processing circuits, and storage elements, into devices through high-density interconnection and bonding techniques, in situ microscopy research can provide direct experimental evidence for bonding accuracy and failure analysis during 3D integration [54], which is crucial for the development of high-performance heterogeneous integration chips. Hebras et al. utilized fine-pitch Cu-Cu hybrid bonding and high-density TSV technology to fabricate a new generation of three-layer stacked devices [55]. The cross-sectional morphology of the entire 3D stacked structure was analyzed using FIB-SEM. Neither of the bonding interfaces of F2F (face to face) and F2B (face to back) exhibited any significant voids, and the same applied to other visible regions in the images. Meanwhile, FIB was used to finely characterize the cross-sectional structure of the 1 μm × 10 μm TSV in the device. At the top of the TSV, a uniformly distributed interfacial structure between the TSV and the HBM solder joints can be observed; at the bottom of the TSV, the TSV has opened as expected on the metal line. At the bonding interfaces between F2F and F2B, FIB-SEM indicated the presence of some very small nano-voids. Because of the voids’ low number and volume, the authors believe that these voids would not affect the electrical measurements conducted on the post-manufacturing three-layer test structures. Lee et al. employed FIB to dissect and compare the cross-sectional structures of TSVs with and without exposure to a current stress of 1.5 × 10⁵ A/cm² over 20 days. As illustrated in Figure 5a, the right-side TSV (TSV2-R) that endured current stress (with electrons flowing from the bottom to the top) exhibited signs of the interfacial boundary between the TSV and the Cu cap shifting upwards. Moreover, a darker contrast was observed near the Cu cap adjacent to the TSV, which, in conjunction with EDS mapping, was determined to be due to the volumetric expansion caused by the substantial electromigration of Sn from the solder bump beneath the TSV along the direction of the electron flow (upwards). The combined FIB-EDS approach proved to be effective in identifying these phase-transformation-related microstructural volumetric increases, playing an indispensable role in the design and manufacturing of processes and packaging [56].

Typical controlled-collapse chip connection (C4) bumps are composed of a solder bump, UBM (under bump metallization), a Cu/Ti-sputtered film on the top side of the Si wafer substrate, and a polyimide film coated between the Si wafer substrate and the Cu/Ti-sputtered film [57]. The polyimide film serves as a buffer layer between the substrate and the UBM, playing a role in stress relief. However, the stress-induced cracking of the polyimide film often occurs in low-k IC packaging, leading to a decrease in the yield. Shi et al. used FIB-SEM and finite element methods to observe polyimide film cracks and stress modeling [58]. The results showed that polyimide films formed at higher curing temperatures and higher reflow cooling rates are more prone to cracking. Because of the mismatch in the coefficients of thermal expansion between the polyimide film and the adjacent UBM metal, cracks in the polyimide film are more likely to propagate to the underside of the UBM and its surroundings after the reflow process. The results indicate that lower curing temperatures, lower elastic moduli, lower reflow temperatures, and lower cooling rates enable the formed polyimide film to absorb more strain energy and flexibly adjust the internal stress, reducing the likelihood of cracking during thermal processes.

The C4 process commonly uses metal eutectic bumps to directly solder the chip onto the substrate pads, where the metal eutectic bumps serve as both physical and electrical connections to the substrate [59]. Copper pillar bump technology with solder caps offers advantages, such as high density, fine pitch, and cost effectiveness, driving its widespread application in the assembly of high-performance mobile devices [60]. The connection between the copper pillar bumps on the chip and the copper pads on the substrate is formed through soldering. Thermocompression bonding (TCB) combined with pre-applied underfill technology enables the precise alignment of bumps and pads while relieving the stress at the bumps’ roots, making it widely used in the fabrication of finer-pitch bump interconnects [61,62]. Ito et al. employed FIB three-dimensional imaging technology to obtain the true microstructure of micro-bumps at the copper wirebonding interface of a commercially available processor’s package substrate, and compared cross-sectional images of the bumps before and after thermal cycling tests [63]. By performing FIB cutting every 200 nm, 240 cross-sectional images of the bumps were captured, and these 240 slice images were used to reconstruct a 3D image. The FIB-SEM results clearly reveal the presence of filler inclusions and numerous voids between the purchased processor’s bumps and the copper pillars. After 1000 thermal cycles from −55 °C to 125 °C, the morphology of the connection significantly changed, with another type of void clearly observed at the interface between the copper pillar and the formed intermetallic compound. In addition to EPMA-imaging technology, the possibility of the void being caused by differences in thermal diffusivity between different metals during thermal cycling was ruled out, and the source of the void was identified as likely being volatile components in the electroplated copper pillars. This work provides an in-depth study of the microstructure and failure mechanisms of bumps in flip-chip interconnects, revealing the impacts of pre-applied underfill solder inclusions and volatile components in electroplated copper pillars on interconnect reliability.

With the reduction in the interconnect pitch in semiconductor processes, FIB milling may introduce localized heating and Ga ion implantation, leading to alterations in the morphology of beam-sensitive materials and the observation of artifacts. The introduction of liquid nitrogen cooling ensures that samples maintain a low temperature during preparation, mitigating adverse effects, such as localized heating and artifacts. Taking indium micro-bumps as an example, they are commonly used materials for interconnecting silicon-integrated circuits with infrared photodiode arrays. Indium has a low melting point and, like gallium, is a Group III metal, which can dissolve in the liquid phase. The introduction of cryogenic FIB can effectively avoid defects/voids caused by Ga ion milling. As shown in Figure 6a,b, the cross-section of the indium micro-bumps fabricated using FIB at room temperature and without a protective layer exhibited a large number of voids (marked as arrows (a)) and curtain effects; in addition, the interface between the indium and the intermetallic phases is marked by arrows (b), and the one between the platinum protection layer and indium is marked by arrows (c). It is possible that because of differences in crystal orientation, Ga ions may predominantly implant in these regions, forming defects (Figure 6a). The introduction of high-energy ions can also cause the collapse and deformation of indium micro-bumps (Figure 6b). Figure 6c shows the cutting of indium micro-bumps at 0 °C, where there are still a few voids at the interface, and the curtain effect at the bottom is reduced. This clearly indicates that the introduction of a protective layer and the low temperature significantly reduce the interfacial thickness, as indicated by arrows b and c. Figure 6d shows the cutting of indium micro-bumps at −193 °C, where no voids or curtain effects are observed at the interface after the FIB cutting, and the cross-section is smooth, revealing all the details within the micro-bumps [64]. This work experimentally demonstrates the importance of cryogenic FIB technology in semiconductor failure analysis, particularly its unique advantages when dealing with low-melting-point materials.

3.3. Research on RDL Failure Mechanisms

RDLs, as a core technology in wafer-level packaging, serve the functions of electrical extension and interconnection in the XY-plane. RDLs achieve circuit interconnection by altering the originally designed chip connection points (I/O points) through wafer-level metal-wiring processes and bump fabrication techniques, enabling the chip to adapt to different packaging forms. To achieve a higher number of I/O points, the linewidth and spacing of RDLs are becoming increasingly smaller. The dual damascene technique stands as one of the most promising technologies in the RDL process, wherein copper lines are embedded within high-resolution photosensitive polymers. One of the challenges of this technique is the inability of polymers to block atmospheric oxygen, leading to copper oxidation. Chery et al. proposed the usage of CVD and ALD to fabricate thin nano-layer protective coatings over copper RDL lines and utilized FIB to assess the morphological changes in the RDL before and after oxidation and corrosion stress tests [65]. Subjecting unprotected copper lines (Figure 7a) to high-temperature storage at 150 °C for 1000 h resulted in the formation of a 330 nm thick oxide layer on the surface (Figure 7b). When the thickness of the protective coating exceeded 8 nanometers, copper oxidation was completely prevented (Figure 7c). However, when the thickness of the protective layer was reduced to 6 nm, an 80 nm thick oxide layer appeared. These observations confirm that a 6 nm thin protective layer cannot fully seal the copper surface, likely because of the high density of defects still present in the thin ALD layer deposited at low temperatures. Figure 7e,f displays FIB cross-sections of the metal lines after the thermal cycling stress, showing that regardless of the type of protective layer, no oxidation of the Cu lines was observed at the end of the stress test when the thickness exceeded 8 nanometers. This indicates that the integrity of the protective layer is unaffected by thermal cycling and pressure, paving the way for integration in polymer-based RDL technologies.

The trend toward miniaturized packaging has brought about issues such as high current density and electromigration in RDLs [66]. Electromigration refers to the diffusion of metal atoms within a conductor when an electric current is applied, leading to mass transport, which causes void formation on the cathode side and hillock formation on the anode side [67]. To further understand the electromigration failure mechanisms in Cu RDLs, Kwon et al. used FIB to observe grain sizes and RDL cross-sectional morphologies before and after charging and discharging [68]. During this process, the increase in the RDL resistance exhibits two distinct phases: In the initial phase, the primary contributor to the resistance rise is the reduction in effective Cu cross-sectional area because of oxidation-induced void nucleation and growth. In the progressive phase, with prolonged electromigration testing, delamination occurs at the Cu/polyimide adhesive interface. This interfacial failure triggers accelerated void propagation, causing rapid resistance escalation where delamination-induced void coalescence becomes the dominant degradation mechanism. This indicates that delamination caused by void growth is the primary factor affecting subsequent resistance increases. Tsai et al. investigated the electromigration behavior of fine-line copper RDLs, using in situ SEM observation, and found that the electromigration lifetime of small-grained copper RDLs is significantly superior to that of large-grained copper RDLs. The results indicate that reducing the grain size is an effective strategy for enhancing the electromigration performance of fine-line copper RDLs under high-current-density conditions [69]. In addition to electromigration-induced RDL failure, Liu explored the influence of pattern dimensions on the structural stability of RDL electroplating. By electrodepositing pads, RDLs, and vias of varying sizes, FIB observations of Cu cross-sections revealed that as the pattern dimensions increased, the flatness of the pads and vias gradually improved, while the flatness of the RDLs progressively deteriorated. Additionally, vias could not be fully filled when the outer diameter of the RDL exceeded 60 μm. In addition to thermal shock testing, it was found that smaller-sized pads were more prone to failure. Therefore, to avoid significant thermal mismatch, it is recommended that the pad dimensions be maintained within the range of 55–90 μm.

4. Innovation in Multimodal Integration Technology

4.1. XRM-FIB 3D Navigation System

XRM can precisely locate internal defects in chips (resolution < 500 nm), and FIB can effectively repair these defects. The combination of XRM and FIB acts like a precision navigation system for chip failure detection and repair, significantly improving the efficiency and accuracy of chip fault handling [70]. With the advent of femtosecond-laser FIB, the processing rate of FIB has increased by nearly 5000 times, enabling its processing range to span from the micron to the centimeter scale, providing critical technical support for large-scale device processing and failure analysis. Taking the damaged solder balls inside an SOC (system-on-chip) device as an example, the workflow mainly includes ➀ Surface marking: Using FIB to create visible marks on the chip surface for subsequent positioning and reference, as shown in Figure 8a; ➁ XRM measurements: Performing XRM measurements on the SoC device to obtain surface mark data and internal data; ➂ Data correlation: Transferring the SoC device to the FIB chamber to acquire SEM data of the marks and correlating it with the mark positions in the XRM data, ensuring consistency between the coordinate systems. The target location (e.g., defect structure) inside the sample can then be located on the surface using the XRM data, as shown in Figure 8b,c; ➃ Milling and observation: Using femtosecond-laser FIB for top-down milling to remove excess material until the target location is exposed in the SEM image, as shown in Figure 8d; ➄ FIB polishing: Using a lower ion beam current to gently polish the target area, removing the curtains from the milling step and obtaining clear cross-sectional images, as shown in Figure 8e,f. Viswanathan et al. utilized XRM and femtosecond-laser FIB technology to dissect a 3D-packaged baseband modem, precisely locating a metallic line inside a chip that was 150 µm deep and 20 µm wide. High-resolution SEM cross-sectional images of the metallic line were obtained after local laser milling [71]. By scanning the milled modem with XRM, it was found that adjacent lines remained intact, further substantiating the significant application of the combined characterization techniques of XRM and FIB in the detection of fault isolation methods for failure analysis. In addition to femtosecond-laser FIB, gas-ion-source FIB technology has advanced rapidly in recent years, with PFIB (plasma-focused ion beam) and BIB (broad ion beam) being typical examples. PFIB utilizes a high-density xenon plasma source to generate an ion beam, offering a current density over 100 times higher than that of a gallium ion source, making it suitable for large-scale processing at the millimeter level. Compared to Ga ion FIB, inert gas ions, such as Xe ions, reduce sample contamination and lattice damage. However, because of its higher beam current, PFIB exhibits a more pronounced curtaining effect. Mitigating this effect requires more precise processing techniques, resulting in longer rocking milling times for sub-micron-scale fabrication. BIB employs inert argon ions to bombard the sample, with a beam spot size ranging from hundreds of micrometers to millimeters, making it ideal for global polishing applications. These include sample preparation for EBSD analysis, the removal of stress layers introduced by mechanical grinding, or interfacial exposure in multilayer materials. In the field of advanced packaging, micro/nano-fabrication and high-resolution characterization at the nano-scale still predominantly rely on Ga ion FIB or PFIB.

4.2. EBSD-FIB Crystallographic Analysis

After cutting the sample using FIB, EBSD can be employed to analyze the cross-sectional crystal orientation and grain size, while transmission electron microscopy (TEM) can be used to obtain high-resolution images. Zhang et al. utilized FIB to prepare a 100 nm thick Al sample with a high topological surface. Transmission EBSD characterization revealed that in the Al sample prepared using physical vapor deposition, 81 percent of the grains grew along the (111) direction aligned with or perpendicular to the silicon substrate, with an average grain size of 0.317 µm, and more than half of the grains were sub-micron in size [72]. Wang et al. utilized EBSD to investigate the barrier effect of a novel electroplated nickel layer on suppressing the growth of the IMC (intermetallic compound) layer in high-density packaging technology [73]. After the preparation of CuNi/SnAg bumps using the reflow-soldering process, they observed the crystal structure and grain orientation of the bump cross-sections stored at 150 °C for varying durations. By combining SEM morphological characterization with EBSD grain structure results (as shown in Figure 9), it was found that as the high-temperature storage time increased, the thickness of the IMC layer gradually increased, the grain size grew larger, and the grain orientation became more uniform. Cu gradually diffused into the nickel layer and reacted with Sn to form Cu₆Sn₅. This work provides new insights into the reliability of solder joints in high-density packaging technology, particularly the mechanism of IMC growth inhibition by the electroplated nickel layer.

Wakamoto et al. used FIB to pre-prepare inclined surfaces and cracks on the surfaces of s-Ag films. Through in situ SEM uniaxial tensile-loading experiments, combined with EBSD, they studied the changes in grains and voids before and after stretching the s-Ag films, revealing that the slip velocity of Ag atoms at grain boundaries determines the deformation and fracture mechanisms of s-Ag films. This provides a reference for the design of future high-performance electronic packaging materials [74]. The processing capability of FIB has also been applied to stress release. Auersperg et al. used EBSD to obtain changes in the crystal orientation within TSV copper pillars during five thermal cycles. By combining finite element analysis and digital image correlation algorithms, they derived the stress distribution within the copper pillars. They then used FIB to create micro-trenches in the copper pillars to release stress. Nano-indentation and bending measurements were employed to extract the Young’s modulus, temperature-dependent yield stress, and hardening coefficient of the copper pillars before and after thermal cycling. They proposed that the mismatch in thermal expansion coefficients between copper and silicon causes stress variations on the silicon surface around the TSV copper pillars and that copper pillar protrusion is a potential cause of post-process delamination and cracking; further optimization is needed to mitigate these risks. This work provides new insights into the reliability analysis and prediction of 3D-IC-integrated TSV processes [75].

4.3. FIB-TOFS In Situ Imaging

In many cases, X-rays can be used for the non-destructive testing of devices, chips, and electrical boards. However, when the material content in the packaging process is under the detection limit or the elements have very low scattering and emission coefficients, X-ray technology cannot directly detect them. The combination of FIB with spectroscopic techniques, such as TOF-SIMS (time-of-flight secondary ion mass spectrometry), represents an effective solution, offering robust support for internal failure analysis of devices. TOF-SIMS is a powerful surface analysis technique that determines ion masses and achieves elemental resolution based on the different flight times of secondary ions from the material surface. It offers ultrahigh surface sensitivity (1 nm) and detection sensitivity (from the parts per million to parts per billion levels) [76,77]. Costina et al. used FIB to prepare cross-sectional samples of Ta₂O₅ capacitor devices and applied TOF-SIMS to obtain a compositional analysis of the cross-sections [78]. During the anodization process, the electrode material, Cu, tends to diffuse into Ta and Ta₂O₅, which is the cause of the defects on the layered stack’s surface. By introducing a Ti:W barrier layer on top of the Cu layer, the diffusion of Cu can be prevented, enabling the growth of defect-free Ta₂O₅ dielectric layers. In their latest work, Klengel et al. combined FIB-SEM, non-destructive lock-in-thermography (LIT), X-ray imaging, energy-dispersive X-ray spectroscopy (EDX), and TOF-SIMS to conduct a comprehensive failure analysis of wirebonding contact failures, providing a typical example for advanced characterization methods in semiconductors’ advanced packaging failure studies [79]. First, LIT was used to stimulate defects with a periodic-pulsed voltage, generating periodic thermal responses to pinpoint the defect location. Next, FIB was employed to cut the Au-ball/Al-pad interface, and it was found that the contact interface between the intermetallic compound layer and the gold-bonding ball was almost completely delaminated. The intensity of the O peak signal in the EDX data could be used to gradually narrow down and locate the fault area. When the detection limit of the EDX was reached, TOF-SIMS was introduced, which has a lower detection limit and higher resolution for low-concentration elements. TOF-SIMS imaging of the area clearly showed the presence of I signals, confirming that halides caused the corrosion of the Au4Al metal wires. This study, through the combined application of multiple characterization techniques, demonstrated the critical roles of such methods in failure analysis. The successful application of this approach provides new solutions for the field of failure analysis, particularly in addressing challenges posed by the miniaturization of packaging systems, new material combinations, and harsh operating conditions.

5. Summary and Prospects

This article discusses recent advancements in the application of FIB-SEM, as well as multimodal integration approaches, in the field of advanced packaging. The combination of FIB-SEM and XRM (X-ray microscopy) enables the precise localization and efficient analysis of internal defects, making it suitable for the multi-scale analysis of devices containing diverse materials and complex structures, thereby providing in-depth insights into device failure mechanisms. The integration of FIB with EBSD technology can be used to analyze the interfacial structures between packaging materials and other materials (such as substrates or chips), assess the crystallographic matching and compatibility of interfaces, and identify grain discontinuities or defects at the interfaces, offering solutions for optimizing interfacial design and processes. The combination of FIB-SEM with TOF-SIMS, EDS, and other spectroscopic techniques allows for simultaneous characterization of structural and chemical compositional information, which is highly beneficial for optimizing surface treatment processes and improving material adhesion and corrosion resistance, and plays significant roles in material modification and the discovery of new packaging materials. Femtosecond-laser FIB, leveraging the high precision and non-thermal damage characteristics of femtosecond lasers, enables higher precision material processing and smaller heat-affected zones, giving it a distinct advantage in the semiconductor-packaging field. Currently, FIB-SEM is widely applied in advanced semiconductor packaging, offering high value in enhancing the reliability of packaging materials, optimizing packaging processes, and driving the development of new packaging technologies and materials. The increasing demands for processing precision and efficiency in advanced semiconductor-packaging processes are also driving the evolution of FIB-SEM technology. Through continuous innovation, FIB-SEM has developed into a comprehensive solution covering process development, failure analysis, and reliability assessment. With the advancement of integrated technologies and the rise of intelligent capabilities, its application in advanced packaging is transitioning from passive detection to active process optimization, providing critical support for next-generation technologies, such as 3D integration and chiplets.