Bae, M.; Choi, B.-S.; Kim, S.-H.; Lee, J.; Oh, C.-W.; Choi, P.; Shin, J.-K.
Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET. Proceedings 2017, 1, 338.
https://doi.org/10.3390/proceedings1040338
AMA Style
Bae M, Choi B-S, Kim S-H, Lee J, Oh C-W, Choi P, Shin J-K.
Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET. Proceedings. 2017; 1(4):338.
https://doi.org/10.3390/proceedings1040338
Chicago/Turabian Style
Bae, Myunghan, Byung-Soo Choi, Sang-Hwan Kim, Jimin Lee, Chang-Woo Oh, Pyung Choi, and Jang-Kyoo Shin.
2017. "Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET" Proceedings 1, no. 4: 338.
https://doi.org/10.3390/proceedings1040338
APA Style
Bae, M., Choi, B.-S., Kim, S.-H., Lee, J., Oh, C.-W., Choi, P., & Shin, J.-K.
(2017). Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET. Proceedings, 1(4), 338.
https://doi.org/10.3390/proceedings1040338