# CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators

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## Abstract

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## 1. Introduction

## 2. Fractional-Order Chaotic Oscillators

## 3. Approximation of the Fractional-Order Integrator by OTA Filters

## 4. CMOS Design of the OTAs, Multiplier, Nonlinear Function and Fractional-Order Integrator

#### 4.1. CMOS Operational Transconductance Amplifier (OTA)

#### 4.2. CMOS Multiplier Design

#### 4.3. Saturated Nonlinear Function (SNLF) Design

#### 4.4. Proposed CMOS Fractional-Order Integrator

## 5. Layout Design and Post-Layout Simulation Results

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**Portraits of the chaotic attractors of FOCO${}_{1}$ given in (4). Each plot shows the attractor among two or three state variables $x,y,z$.

**Figure 2.**Portraits of the chaotic attractors of FOCO${}_{2}$ given by (5). Each plot shows the attractor among two or three state variables $x,y,z$.

**Figure 4.**OTA-based first-order active filters taken from [33], to implement: (

**a**) ${H}_{1}\left(s\right)$ and ${H}_{2}\left(s\right)$, and (

**b**) ${H}_{3}\left(s\right)$.

**Figure 5.**Proposed OTA design of $\frac{1}{{s}^{0.9}}$ that is approximated by (7), and designed by cascading ${H}_{1}\left(s\right){H}_{2}\left(s\right){H}_{3}\left(s\right)$.

**Figure 10.**CMOS OTA taken from [36].

**Figure 11.**Fully differential four-quadrant multiplier taken from [38].

**Figure 12.**Multiplication of two signals using the CMOS design from Figure 11.

**Figure 13.**Proposed single-ended multiplier combining the fully-differential multiplier shown in Figure 11 and an OTA-subtractor.

**Figure 14.**CMOS design of the SNLF block taken from [36].

**Figure 17.**Comparison of the gain (up side) and phase margin (down side) responses of the fractional-order integrator $H\left(s\right)=1/{s}^{0.9}$, considering the ideal transfer function approximation in MATLAB, macro-modeling the OTAs, HSPICE simulation using MOS transistor models, and post-layout simulation.

**Figure 18.**Process–voltage–temperature (PVT) variation simulations of the CMOS fractional-order integrator shown in Figure 16.

**Figure 19.**Monte Carlo simulation of our proposed CMOS fractional-order integrator shown in Figure 16.

**Table 1.**Electrical characteristics and sizes of the CMOS OTA shown in Figure 10 to provide a $gm=500\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$A/V and $gm=350\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$A/V.

Parameter | gm = 500 u | gm = 350 u |
---|---|---|

DC GAIN (dB) | 61.232 | 61.125 |

GBW (KHz) | 425 | 419 |

PM (${}^{\circ}$) | 88.96 | 88.943 |

CMRR (dB) | 73 | 74 |

SR+ (v/$\mathsf{\mu}$s) | 0.098 | 0.095 |

SR- (v/$\mathsf{\mu}$s) | 0.106 | 0.105 |

PSRR+ (dB) | 89 | 89 |

PSRR- (dB) | 61 | 61 |

Power dissipation (mW) | 3.19 | 3.18 |

$Fo{M}_{s}$ | 1856.8 | 1843.6 |

$Fo{M}_{l}$ | 431.2 | 418 |

W(M1,M2) ($\mathsf{\mu}$m) | 20.16 | 20.16 |

W(M3,M14,M15) ($\mathsf{\mu}$m) | 39.6 | 39.6 |

W(Mb,M12,M13) ($\mathsf{\mu}$m) | 19.8 | 19.8 |

W(M4-M9) ($\mathsf{\mu}$m) | 61.2 | 61.2 |

W(M10,M11)($\mathsf{\mu}$m) | 122.4 | 122.4 |

L($\mathsf{\mu}$m) | 1.8 | 1.8 |

Ib ($\mathsf{\mu}$A) | 50 | 50 |

**Table 2.**Sizes of the OTA shown in Figure 10 to provide a $gm=800\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$A/V.

Transistor | $\mathit{W}(\mathsf{\mu}$m) | $\mathit{L}(\mathsf{\mu}$m) | Multiplicity |
---|---|---|---|

${M}_{1},{M}_{2}$ | 5.04 | 1.8 | 4 |

${M}_{3},{M}_{14},{M}_{15}$ | 9.9 | 1.8 | 4 |

${M}_{b},{M}_{12},{M}_{13}$ | 9.9 | 1.8 | 2 |

${M}_{4}-{M}_{9}$ | 30.6 | 1.8 | 2 |

${M}_{10},{M}_{11}$ | 30.6 | 1.8 | 4 |

**Table 3.**Sizes of the OTA shown in Figure 10 to provide a $gm=2\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$A/V.

Transistor | $\mathit{W}(\mathsf{\mu}$m) | $\mathit{L}(\mathsf{\mu}$m) | Multiplicity |
---|---|---|---|

${M}_{1},{M}_{2}$ | 1.26 | 1.8 | 4 |

${M}_{3}$ | 2.52 | 1.8 | 4 |

${M}_{b},{M}_{4}-{M}_{11},{M}_{12}-{M}_{15}$ | 2.52 | 1.8 | 2 |

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**MDPI and ACS Style**

Valencia-Ponce, M.A.; Castañeda-Aviña, P.R.; Tlelo-Cuautle, E.; Carbajal-Gómez, V.H.; González-Díaz, V.R.; Sandoval-Ibarra, Y.; Nuñez-Perez, J.-C.
CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators. *Fractal Fract.* **2021**, *5*, 122.
https://doi.org/10.3390/fractalfract5030122

**AMA Style**

Valencia-Ponce MA, Castañeda-Aviña PR, Tlelo-Cuautle E, Carbajal-Gómez VH, González-Díaz VR, Sandoval-Ibarra Y, Nuñez-Perez J-C.
CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators. *Fractal and Fractional*. 2021; 5(3):122.
https://doi.org/10.3390/fractalfract5030122

**Chicago/Turabian Style**

Valencia-Ponce, Martín Alejandro, Perla Rubí Castañeda-Aviña, Esteban Tlelo-Cuautle, Victor Hugo Carbajal-Gómez, Victor Rodolfo González-Díaz, Yuma Sandoval-Ibarra, and Jose-Cruz Nuñez-Perez.
2021. "CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators" *Fractal and Fractional* 5, no. 3: 122.
https://doi.org/10.3390/fractalfract5030122