Two-Dimensional Tunable Reactance Element Free from Electromagnetic Coupling

Abstract

A capacitor modeled as a parallel combination of a resistance ($\mathrm{R}$) and a capacitance ($\mathrm{C}$) exhibits three distinct operating regimes when both parameters depend on the applied voltage (V): a positive-capacitance regime ($\mathrm{d}\mathrm{R}/\mathrm{R}>\mathrm{d}\mathrm{V}/\mathrm{V}$), an Ohmic regime ($\mathrm{d}\mathrm{R}/\mathrm{R}=\mathrm{d}\mathrm{V}/\mathrm{V}$), and a negative-capacitance regime ($\mathrm{d}\mathrm{R}/\mathrm{R}<\mathrm{d}\mathrm{V}/\mathrm{V}$). In the limit ($\mathrm{R}\to \mathrm{\infty }$), the device behaves as a conventional permittivity-based capacitor, whereas in the limit ($\mathrm{R}\to 0$), negative capacitance emerges due to nonlinear current–voltage characteristics. To verify this mechanism, we fabricated nanometer-spaced two-electrode structures using multi-walled carbon nanotubes (MWCNTs) and Si crystals. The measurements confirmed negative capacitance consistent with theoretical predictions. Unlike ferroelectric negative capacitance, the effect demonstrated here arises solely from the nonlinear I–V characteristics at the electrode interfaces, without involving any ferroelectric polarization dynamics. This negative capacitance can be interpreted as an equivalent inductance, enabling a two-dimensional tunable reactance element (TDTRE) that operates without electromagnetic coupling and is compatible with conventional IC technologies.

1. Introduction

Classical circuits are composed of passive elements—resistors ($\mathrm{R}$s), capacitors ($\mathrm{C}$s), and inductors ($\mathrm{L}$s). The development of semiconductor devices and advanced materials has introduced active elements such as diodes and transistors, greatly expanding circuit functionality and application domains [1,2,3]. In recent years, unconventional passive elements such as negative resistance and negative capacitance have also been reported [4,5,6,7]. Early studies of nonlinear current–voltage (I–V) characteristics in vacuum tubes and gas-discharge devices revealed regimes in which current decreases with increasing voltage, forming the basis of negative differential resistance. The tunnel diode invented by Esaki et al. [8,9] exhibits a pronounced negative-resistance region and has inspired extensive research into its mechanisms and applications. As discussed below, negative resistance plays a critical role in the emergence of negative capacitance.

Recently, fully two-dimensional inductive elements that operate without coils or magnetic fields have been proposed [10,11]. Because their operating principles differ fundamentally from those of conventional inductors, they offer significant potential for integration and miniaturization. Planar implementations enable on-chip inductors suitable for high-frequency and resonant circuits. In the GHz bands used for RF communications and 5G/6G systems, conventional coil-type inductors face limitations in size and energy loss, making planar reactance elements a promising alternative. In coil-free power circuits, realizing inductance without wound coils for DC–DC converters and output filters could enable thinner and lighter power-supply designs.

This paper investigates the physical origin, quantitative characteristics, and implementation challenges of planar inductive elements. Building on this foundation, we propose a method for realizing a two-dimensional tunable reactance element (TDTRE), supported by both theoretical analysis and experimental validation.

2. Theory and Practice of Negative Capacitance

2.1. Definition and Background

The concept of negative capacitance has attracted considerable attention in recent years. In 1986, Jonscher discussed its physical origin and defined it as a phenomenon in which the current temporarily decreases in response to a voltage step in the time domain [12]. Since then, negative-capacitance effects in ferroelectric materials have been widely studied, particularly for transistor gate control. Since the 2010s, research groups at institutions such as Stanford and Bell Labs have demonstrated negative-capacitance field-effect transistors (NC-FETs), which are promising for low-power electronics [13,14].

Traditionally, negative capacitance has been attributed to intrinsic ferroelectric properties of a dielectric layer between electrodes, where the interplay between ferroelectric and dielectric responses can yield an effective capacitance that becomes either positive or negative [13,15,16]. Because a capacitor is inherently non-polar, negative capacitance is a phenomenological description of an apparent reduction or even a sign reversal of the effective capacitance.

In contrast, the present work reports negative capacitance that does not originate from ferroelectricity but from a circuit phenomenon produced by controlling the capacitor’s I–V characteristic. Specifically, negative capacitance appears when the current lags the voltage in phase. Because no free charge remains on the plates when power is removed, we refer to this behavior as volatile negative capacitance.

2.2. Ferroelectric-Origin Negative Capacitance

When ferroelectric material is used as the dielectric layer, its free-energy profile can produce responses that differ markedly from those of conventional capacitors. The free-energy landscape typically exhibits a bistable double-well shape as a function of polarization, with a region of negative curvature between the wells. In this region, the polarization response to an applied electric field—that is, the differential capacitance—can become negative [13,15,16,17].

Such negative capacitance is thermodynamically unstable in an isolated ferroelectric layer and is typically stabilized by connecting it in series with a paraelectric or dielectric layer. When the ferroelectric layer traverses the negative-capacitance region, the overall voltage response becomes nonlinear, resulting in internal voltage amplification. This effect is of particular interest for reducing the subthreshold slope (SS) of transistors below 60 mV/dec and is being actively pursued for NC-FET applications [18,19].

Domain structure, interface states, film thickness, and crystallinity strongly influence the manifestation of negative capacitance, and precise control of these factors is essential for stable operation. HfO₂-based ferroelectrics are particularly promising because of their compatibility with CMOS processes [15,20,21,22].

2.2.1. Basic Theory

Negative capacitance arises when the curvature of free energy with respect to polarization is negative. Let the free-energy density be F(P), and let the electric field $\mathrm{E}$ be given by the following [23]:

$$\mathrm{E}={\displaystyle \frac{\mathrm{d}\mathrm{F}}{\mathrm{d}\mathrm{P}}}$$

(1)

For a capacitor, the terminal voltage $\mathrm{V}$ is ($\mathrm{V}=\mathrm{E}·\delta$), where $\delta$ is dielectric thickness, and the terminal charge density corresponds to $\mathrm{Q}$. The differential capacitance is

$$\mathrm{C}\equiv {\displaystyle \frac{\mathrm{d}\mathrm{Q}}{\mathrm{d}\mathrm{V}}}={\displaystyle \frac{\mathrm{d}\mathrm{P}}{\mathrm{d}\mathrm{V}}}={\displaystyle \frac{\mathrm{d}\mathrm{P}}{\delta \mathrm{d}\mathrm{E}}}$$

(2)

Differentiating $\mathrm{E}=\mathrm{d}\mathrm{F}/\mathrm{d}\mathrm{P}$ with respect to $\mathrm{P}$ yields

$${\displaystyle \frac{\mathrm{d}\mathrm{P}}{\mathrm{d}\mathrm{E}}}={\left({\displaystyle \frac{{\mathrm{d}}^2\mathrm{F}}{{\mathrm{d}\mathrm{P}}^2}}\right)}^{-1}$$

(3)

Thus,

$$\mathrm{C}={\displaystyle \frac{\mathrm{d}\mathrm{P}}{\delta \mathrm{d}\mathrm{E}}}={{\displaystyle \frac{1}{\delta }}\left({\displaystyle \frac{{\mathrm{d}}^2\mathrm{F}}{{\mathrm{d}\mathrm{P}}^2}}\right)}^{-1}$$

(4)

Therefore, if ${\mathrm{d}}^2\mathrm{F}/\mathrm{d}{\mathrm{P}}^2<0$, then $\mathrm{d}\mathrm{P}/\mathrm{d}\mathrm{E}<0$, and the differential capacitance $\mathrm{C}$ becomes negative. In equilibrium, the free energy must be minimized, requiring ${\mathrm{d}}^2\mathrm{F}/\mathrm{d}{\mathrm{P}}^2>0$. Regions with negative curvature are unstable, and the system transitions to a nearby stable state via polarization switching or domain formation.

Experimentally observed negative capacitance often arises from transient rather than static equilibrium responses. Delayed processes associated with domain formation or polarization reversal (domain-wall motion, relaxation dynamics, or interfacial decay) can cause the current response to a voltage step to temporarily reverse [23].

2.2.2. Applications and Challenges

Ferroelectric negative capacitance has been widely explored for voltage amplification and low-power electronics [24]. Its underlying physical mechanisms have been investigated through theoretical modeling and TCAD simulations, which elucidate the ferroelectric energy landscape and device-level behavior [24]. In parallel, significant progress has been made in HfO₂-based ferroelectric thin films and interface engineering, improving material stability and compatibility with CMOS processes [25]. Despite these advances, several challenges remain.

A major challenge is hysteresis, which can arise from oxygen-vacancy dynamics, domain interactions, or interfacial charge trapping [26]. Achieving hysteresis-free operation requires careful control of ferroelectric thickness, interface states, and leakage pathways [25]. Furthermore, distinguishing between volatile and nonvolatile polarization responses is essential, as different applications—such as steep-slope transistors and memory devices—require different switching characteristics [27].

Overall, ferroelectric negative capacitance remains a promising pathway toward ultralow-power transistors and advanced memory devices, but continued progress in materials optimization, interface control, and device-level modeling is required to ensure stable and application-specific performance.

2.3. Negative Capacitance Originating from Current–Voltage Characteristics

In ferroelectric capacitors, voltage-induced changes in permittivity can reduce the effective capacitance due to intrinsic material nonlinearity. However, aside from specific ferroelectrics such as HfO₂, this effect is negligible in conventional dielectrics. A defining feature of such systems is the accumulation of nonvolatile free charge on both electrodes.

In this study, we demonstrate negative capacitance by deliberately introducing nonlinear I–V characteristics between electrodes. Specifically, we induce negative capacitance by driving field-emission currents at two electrode interfaces and tailoring the resulting I–V response [10,11]. Field-emission current follows the Fowler–Nordheim relation ($\mathrm{I}=a{\mathrm{V}}^2{e}^{-b/\mathrm{V}}$) [28], which strongly deviates from Ohm’s law. In our recent work, we observed negative capacitance in a capacitor formed by two electrodes separated by a vacuum gap. Unlike ferroelectric negative capacitance, this form is volatile because the accumulated free charge dissipates when power is removed.

2.3.1. Basic Theory

A conventional capacitor can be modeled as a parallel combination of a capacitance ($\mathrm{C}$) and a leakage-related resistance ($\mathrm{R}$). When a constant current source ${\mathrm{I}}_0$ is applied, the capacitor voltage is determined by the currents flowing through ($\mathrm{C}$) and ($\mathrm{R}$):

$${\mathrm{I}}_{\mathrm{C}}={\mathrm{I}}_0-{\mathrm{I}}_{\mathrm{R}}={\mathrm{I}}_0-{\displaystyle \frac{\mathrm{V}}{\mathrm{R}}}$$

(5)

The accumulated charge $\mathrm{Q}$ is

$$\mathrm{Q}=\underset{-\mathrm{\infty }}{\overset{\mathrm{t}}{\int }}{\mathrm{I}}_{\mathrm{C}} \mathrm{d}\mathrm{t}=\underset{-\mathrm{\infty }}{\overset{\mathrm{t}}{\int }}({\mathrm{I}}_0-{\displaystyle \frac{\mathrm{V}}{\mathrm{R}}})\mathrm{d}\mathrm{t}$$

(6)

Assuming ${\mathrm{I}}_0$ is constant and ($\mathrm{R}\left(\mathrm{V}\right)$) depends on the applied voltage, the differential capacitance becomes

$$\mathrm{C}={\displaystyle \frac{\mathrm{d}\mathrm{Q}}{\mathrm{d}\mathrm{V}}}=\underset{-\mathrm{\infty }}{\overset{\mathrm{t}}{\int }}{\displaystyle \frac{1}{\mathrm{R}}}({\displaystyle \frac{\mathrm{V}}{\mathrm{R}}}{\displaystyle \frac{\mathrm{d}\mathrm{R}}{\mathrm{d}\mathrm{V}}}-1)\mathrm{d}\mathrm{t}$$

(7)

In Equation (7), all differentials such as ($\mathrm{d}\mathrm{R}$) and ($\mathrm{d}\mathrm{V}$) are taken with respect to the DC bias voltage (V). That is, $\mathrm{d}\mathrm{R}\equiv (\mathrm{d}\mathrm{R}/\mathrm{d}\mathrm{V})·\mathrm{d}\mathrm{V}$, and ($\mathrm{d}\mathrm{V}$) represents an infinitesimal change in the DC bias.

Using this definition, the sign of the differential capacitance ($\mathrm{C}=$ differential capacitance) can be expressed unambiguously as follows:

$$\mathrm{I}.\mathrm{C}>0 \mathrm{i}\mathrm{f} {\displaystyle \frac{1}{\mathrm{R}}}·{\displaystyle \frac{\mathrm{d}\mathrm{R}}{\mathrm{d}\mathrm{V}}}>{\displaystyle \frac{1}{\mathrm{V}}},$$

(8)

$$\mathrm{I}\mathrm{I}.\mathrm{C}=0 \mathrm{i}\mathrm{f} {\displaystyle \frac{1}{\mathrm{R}}}·{\displaystyle \frac{\mathrm{d}\mathrm{R}}{\mathrm{d}\mathrm{V}}}={\displaystyle \frac{1}{\mathrm{V}}},$$

(9)

$$\mathrm{I}\mathrm{I}\mathrm{I}.\mathrm{C}<0 \mathrm{i}\mathrm{f} {\displaystyle \frac{1}{\mathrm{R}}}·{\displaystyle \frac{\mathrm{d}\mathrm{R}}{\mathrm{d}\mathrm{V}}}={\displaystyle \frac{1}{\mathrm{V}}},$$

(10)

Although Equation (7) contains a time integral, the sign of ($\mathrm{C}$) is determined solely by the differential relation between $\mathrm{R}\left(\mathrm{V}\right)$ and ($\mathrm{V}$), because the pre-factor ${\mathrm{I}}_0$ is positive and the integral kernel is strictly positive. Therefore, the sign of ($\mathrm{d}\mathrm{Q}/\mathrm{d}\mathrm{V}$) is governed by the relative variations of ($\mathrm{R}\left(\mathrm{V}\right)$) and ($\mathrm{V}$). These inequalities follow directly from Equation (7) by differentiating ($\mathrm{Q}\left(\mathrm{V}\right)$) with respect to ($\mathrm{V}$) and comparing the relative variations of ($\mathrm{d}\mathrm{R}/\mathrm{R}$) and ($\mathrm{d}\mathrm{V}/\mathrm{V}$).

In the small-signal limit, the device is modeled as a parallel RC element, and the admittance is written as $\mathrm{Y}\left(\mathsf{\omega }\right)=1/\mathrm{R}\left(\mathrm{V}\right)+j\mathsf{\omega }\mathrm{C}\left(\mathrm{V}\right)$. From the measured impedance $\mathrm{Z}\left(\mathsf{\omega }\right)$, the admittance is obtained as $\mathrm{Y}\left(\mathsf{\omega }\right)=1/\mathrm{Z}\left(\mathsf{\omega }\right)$. The differential capacitance is then extracted from the imaginary part of the admittance: $\mathrm{C}\left(\mathrm{V}\right)=\mathrm{I}\mathrm{m}\left\{\mathrm{Y}\left(\mathsf{\omega }\right)\right\}/\mathsf{\omega } (\mathsf{\omega }\to 0)$. The characteristic time constant is defined as $\mathsf{\tau }\left(\mathrm{V}\right)=\mathrm{R}\left(\mathrm{V}\right)·\mathrm{C}\left(\mathrm{V}\right)$, which corresponds to the relaxation time of the small-signal response.

Throughout the extraction procedure, we adopt a parallel RC representation for determining ($\mathrm{R}\left(\mathrm{V}\right)$) and ($\mathrm{C}\left(\mathrm{V}\right)$) from the admittance $\mathrm{Y}\left(\mathsf{\omega }\right)=1/\mathrm{Z}\left(\mathsf{\omega }\right)$. For interpreting the negative imaginary component of the impedance, we additionally use a series RLC representation. The sign of ${\mathrm{L}}_{eff}$ directly reflects the sign of the differential capacitance.

In the first regime, the relative change in resistance exceeds that of voltage. Rewriting the condition,

$$d \mathrm{l}\mathrm{n}\mathrm{R}-d \mathrm{l}\mathrm{n}\mathrm{V}>0 \mathrm{o}\mathrm{r} d \mathrm{l}\mathrm{n}\left({\displaystyle \frac{\mathrm{R}}{\mathrm{V}}}\right)>0$$

(11)

indicating that the ratio ($\mathrm{R}/\mathrm{V}$) increases with ($\mathrm{V}$). Consequently, the resistive current decreases, allowing charge to accumulate on the plates, which corresponds to positive differential capacitance.

High-resistance dielectric capacitors often exhibit conduction mechanisms such as polarization current [29], leakage current [30], thermally activated conduction (e.g., Poole–Frenkel or trap-limited) [30], space-charge-limited conduction (SCLC) [31,32], and tunneling conduction (e.g., Fowler–Nordheim) [26]. For many dielectrics, SCLC follows a power-law dependence:

$$\mathrm{I}\left(\mathrm{V}\right)\propto {\mathrm{V}}^m m>2$$

(12)

In the SCLC-dominated region, $\mathrm{d}\mathrm{R}/\mathrm{R}>\mathrm{d}\mathrm{V}/\mathrm{V}$, resulting in a positive, nonvolatile capacitance. In the limit $\mathrm{R}\to \mathrm{\infty }$, the dielectric approaches an ideal positive capacitor.

In the second regime $(\mathrm{d}\mathrm{R}/\mathrm{R}=\mathrm{d}\mathrm{V}/\mathrm{V})$, integrating yields $\mathrm{l}\mathrm{n}\mathrm{R}=\mathrm{l}\mathrm{n}\mathrm{V}+\mathsf{\alpha }$, where α is a constant, hence

$$\mathrm{R}=\mathsf{\beta }\mathrm{V},\hspace{1em}\mathsf{\beta }=e^{\alpha }>0$$

(13)

so, resistance is proportional to the applied voltage, and Ohm’s law holds. In this case, the capacitive contribution vanishes, and the equivalent circuit is purely resistive.

In the third regime $(\mathrm{d}\mathrm{R}/\mathrm{R}<\mathrm{d}\mathrm{V}/\mathrm{V})$, the relative change in resistance is smaller than that of $\mathrm{V}$. The relative change in the resistive current ${\mathrm{I}}_{\mathrm{R}}=\mathrm{V}/\mathrm{R}$ is

$${\displaystyle \frac{\mathrm{d}{\mathrm{I}}_{\mathrm{R}}}{{\mathrm{I}}_{\mathrm{R}}}}={\displaystyle \frac{\mathrm{d}\mathrm{V}}{\mathrm{V}}}-{\displaystyle \frac{\mathrm{d}\mathrm{R}}{\mathrm{R}}}$$

(14)

Thus, $\mathrm{d}{\mathrm{I}}_{\mathrm{R}}/{\mathrm{I}}_{\mathrm{R}}>0$: Increasing voltage increases the current through $\mathrm{R}$, implying that the effective resistance decreases. When $\mathrm{R}\to 0$ tunneling current dominates between electrodes.

As the applied voltage V increases, the current ${\mathrm{I}}_{\mathrm{R}}$ increases, and consequently the capacitor current ${\mathrm{I}}_{\mathrm{C}}$ decreases. Equation (6) therefore indicates a reduction in the stored charge ($\mathrm{Q}$), corresponding to the emergence of negative differential capacitance.

As an illustrative example, consider an ideal parallel-plate structure. When the plate separation is large and field-emission current dominates, the current follows the Fowler–Nordheim relation ($\mathrm{I}\left(\mathrm{V}\right)\propto {\mathrm{V}}^2{e}^{-b/\mathrm{V}}$), and the resistive (${\mathrm{I}}_{\mathrm{R}}$) increases rapidly with increasing V. In contrast, when the plate separation is reduced to a few nanometers and resonant quantum tunneling becomes dominant, electrons traverse the capacitor one at a time, and the effective capacitance becomes influenced by quantization effects. The capacitive current ${\mathrm{I}}_{\mathrm{C}}$ can be obtained numerically using the Landauer formula. Numerical calculations were performed using a resonant-tunneling model in which the electron transmission probability is $\mathrm{T}\left(\mathrm{E},\mathrm{V}\right)={\mathsf{\Gamma }}_n^2/({\mathsf{\Gamma }}_n^2+{(\mathrm{E}-{\mathrm{E}}_0)}^2)$ [33] and the current is given by $\mathrm{I}\left(\mathrm{V}\right)=(2e/h){\int }_{{\mu }_R}^{{\mu }_L}\mathrm{T}\left(\mathrm{E},\mathrm{V}\right)\mathrm{d}\mathrm{E}$ [34]. Here, ${\mathsf{\Gamma }}_n$ is the level broadening, ${\mathrm{E}}_0$ is the resonance energy level, and ${\mu }_L$ and ${\mu }_R$ are the chemical potentials of the left and right electrodes. The calculation conditions were a 1 nm plate separation, a resonance energy of 0.1–0.3 eV (depending on (V)), and room temperature. All computations were performed using SciPy.

Figure 1 shows the voltage dependence of the capacitive current ${\mathrm{I}}_{\mathrm{C}}$. In the low-voltage region, electrons cannot overcome the potential barrier, resulting in a low transmission probability. As the voltage increases, the electron energy approaches the resonant level, the transmission probability rises, and the current reaches a peak. There are further increases in voltage away from resonance, reducing the transmission probability and decreasing the current. Negative differential capacitance is expected in the voltage range where the current increases toward its resonant peak. This characteristic voltage dependence corresponds to the first resonant-tunneling peak through a single barrier.

2.3.2. Applications and Outlook

Ferroelectric-based negative capacitance is attractive for low-power electronic devices but is often limited by the high internal resistance inherent to ferroelectric materials. In contrast, negative capacitance originating from nonlinear current–voltage (I–V) characteristics allows deliberate engineering of the internal resistance and, in extreme cases, implementation using only two metallic electrodes. This flexibility broadens the applicability of negative-capacitance devices across a wide range of operating conditions and power levels.

Moreover, this form of negative capacitance can emulate inductive behavior, enabling the realization of coil-free two-dimensional tunable reactance elements (TDTREs). Although such devices may not fully replace conventional electromagnetic inductors, they provide new functional capabilities, particularly in applications where miniaturization, planar integration, or the elimination of magnetic coupling is advantageous.

3. Two-Dimensional Tunable Reactance Element Free from Electromagnetic Coupling

3.1. Basic Theory

Conventional inductors include 3D coils with magnetic cores [35,36] and near-2D coils [37]. The TDTRE eliminates constraints such as device height, volume, and magnetic-core dependence, enabling true on-chip integration and contributing to device miniaturization.

The impedance of a series circuit consisting of resistance $\mathrm{R}$, inductance $\mathrm{L}$, and capacitance $\mathrm{C}$ is

$$Z=\mathrm{R}+\mathrm{j}\left(\mathsf{\omega }\mathrm{L}-{\displaystyle \frac{1}{\mathsf{\omega }\mathrm{C}}}\right)$$

(15)

If $\mathrm{C}$ becomes negative, its contribution can be incorporated into the inductive term. The resulting effective inductance ${\mathrm{L}}_{eff}$ is

$${\mathrm{L}}_{eff}=\left(\mathrm{L}+{\displaystyle \frac{1}{{\omega }^2\mathrm{C}}}\right)$$

(16)

Although the contribution of the $1/\left({\omega }^2\mathrm{C}\right)$ diminishes at high frequencies $\mathsf{\omega }\to \infty$, in the low-frequency region, the effective inductance approaches $\mathrm{L}+1/\left({\omega }^2\mathrm{C}\right)$. Under appropriate conditions, the circuit elements $\mathrm{L}$ and $\mathrm{C}$ can be functionally interchanged, enabling transformations such as $-\mathrm{L}\leftrightarrow \mathrm{C}$ and $\mathrm{L}\leftrightarrow -\mathrm{C}$. Physically, if tunneling current is introduced into a capacitor that normally blocks charge transport, the resulting current–voltage relationship can resemble that of an inductor. This provides a theoretical basis for interpreting negative capacitance as an effective inductance. Furthermore, the ability to switch between positive and negative capacitances enables tunable reactance. The preceding theoretical analysis shows that this tunability depends on parameters such as the DC bias voltage and the AC signal frequency.

3.2. Experimental Realization

Our group is developing a TDTRE designed to eliminate electromagnetic interaction [10,11]. Publications and patents to date are limited to our work. Although this approach cannot replicate all functions of conventional electromagnetic inductors—such as magnetic-energy storage or energy isolation—it provides new device functionalities.

Conventional inductors typically serve roles such as magnetic-energy storage [38], filtering and noise suppression [30], tuning and frequency selection [39], impedance matching [39], energy isolation [38], and control of time constants and transient responses [40].

As an initial demonstration, we investigated reactance elements based on compressed pellets of multi-walled carbon nanotube (MWCNT) powder [10]. MWCNT pellets form a transport network combining one-dimensional quantum conduction within tubes and complex inter-tube contacts, tunneling junctions, and disorder. By adjusting the degree of pellet compression, tunneling conduction can be made dominant.

Using a 5 mm diameter, and an approximately 0.5 mm thick MWCNT pellet, we fabricated an electrode/MWCNT/interface/MWCNT/electrode structure [11]. This structure supports tunneling currents inside MWCNTs and at MWCNT/MWCNT interfaces. We measured the samples using an impedance analyzer and analyzed the frequency, AC amplitude, and DC bias dependence of inductance. By adjusting the contact distance between two pellets to modulate the contact area, we demonstrated control of the tunneling conduction component. Currents through MWCNT/MWCNT interfaces can be decomposed into conductive, polarization, and tunneling components; controlling the tunneling component clarified its contribution to inductance generation.

Below 1 kHz, inductance decreased monotonically with increasing frequency, reaching a maximum of approximately 0.3 mH at the lowest measured frequency. This frequency dependence is consistent with the ($1/{\omega }^2$) term in (${\mathrm{L}}^{\prime }$). We also observed that increasing the AC amplitude led to an increase in the inductance.

Next, we fabricated an electrode/Si/interface/Si/electrode structure using p-type Si (100) wafers (area $3 \mathrm{m}\mathrm{m}\times 3 \mathrm{m}\mathrm{m}$, thickness $520 \mathsf{\mu }\mathrm{m}$, resistivity $10 \mathsf{\Omega }·\mathrm{c}\mathrm{m}$). In this structure, tunneling current occurs exclusively at the Si contact interface, enabling a clear separation of interface and bulk contributions. We processed to produce undulating surfaces to the Si wafers and selected pairs such that contacts became point or line contacts when two wafers faced each other. Theoretical calculations indicate that the tunneling current is larger for point contacts than for line contacts. Under these conditions, we investigated the contribution of tunneling current to inductance.

Inductance analysis confirmed the presence of two-dimensional inductance in the electrode/Si/interface/Si/electrode structure. We found that the inductance can be controlled by frequency, AC amplitude, and DC bias. These results indicate that two-dimensional inductance is realized when tunneling current flows exclusively at the electrode interface.

As described above, the TDTRE originates from the combined behavior of a capacitor ($\mathrm{C}$) and a resistor ($\mathrm{R}$). Its effective inductance depends not only on ($\mathrm{C}$) and ($\mathrm{R}$), but also on the electric field strength $\mathrm{E}$ within the capacitor and the AC frequency $\omega$. Figure 2 illustrates a simple equivalent circuit of the TDTRE. The ratio of $-\mathrm{C}$ to $\mathrm{C}$ represents the efficiency of negative-capacitance generation. Negative capacitance is not just the capacitance with a negative sign; it is a function of several parameters, including $\mathrm{E}$, $\mathrm{V}$, $\mathrm{C}$, and $\omega$.

3.3. Challenges and Outlook

We utilized the distinctive current–voltage characteristics of field-emission current $\mathrm{I}\left(\mathrm{V}\right)$ from material surfaces to enable functional transformation between inductance and negative capacitance $\mathrm{L}\leftrightarrow -\mathrm{C}$, thereby achieving tunable reactance. Similar behavior is also expected in devices exhibiting negative differential resistance, such as Esaki diodes, resonant-tunneling diodes, Gunn diodes, high-frequency discharge devices, unijunction transistors, and certain classes of switching devices.

Advancing the research and development of two-dimensional negative-capacitance and inductive elements may open new scientific and technological frontiers. Potential applications include novel passive components for integrated circuits, miniaturized RF systems, and unconventional energy-handling devices. However, challenges remain in stability, reproducibility, and integration with existing semiconductor technologies. Continued progress into material selection, interface engineering, and circuit-level modeling will be essential for practical implementation.

4. Conclusions

By introducing a nonlinear current–voltage (I–V) characteristic between two electrodes, we have demonstrated the realization of volatile negative capacitance and two-dimensional inductance. Theoretical analysis and device characterization show that these elements can function either as standalone negative-capacitance components or as tunable reactance elements suitable for on-chip integration.

A capacitor modeled as a parallel combination of a resistance ($\mathrm{R}$) and a capacitance ($\mathrm{C}$) exhibits three distinct operating regimes when both parameters depend on the applied voltage V: a positive-capacitance regime ($\mathrm{d}\mathrm{R}/\mathrm{R}>\mathrm{d}\mathrm{V}/\mathrm{V}$), an Ohmic regime ($\mathrm{d}\mathrm{R}/\mathrm{R}=\mathrm{d}\mathrm{V}/\mathrm{V}$), and a negative-capacitance regime ($\mathrm{d}\mathrm{R}/\mathrm{R}<\mathrm{d}\mathrm{V}/\mathrm{V}$). When resistance dominates ($\mathrm{R}\to \mathrm{\infty }$), the system behaves as a conventional permittivity-based capacitor; when capacitance dominates ($\mathrm{R}\to 0$), negative capacitance emerges, governed by the nonlinear $\mathrm{I}-\mathrm{V}$ characteristic. Thus, low-resistance conditions favor the formation of negative capacitance.

Within circuit theory, negative capacitance can be interpreted as an effective inductance, with the equivalent inductance given by $\left|1/{\omega }^2\mathrm{C}\right|$. Unlike ordinary dielectric capacitors ($\mathrm{R}\to \mathrm{\infty }$), this inductance depends on both the operating frequency and the magnitude of the negative capacitance. The inductive effect is most pronounced at low frequencies and decreases rapidly with increasing frequency, following the ($1/{\omega }^2$) dependence.

The frequency response of the TDTRE is determined by the circuit time constant ($\mathrm{R}\mathrm{C}$). When R is sufficiently small, high-frequency operation becomes feasible; for example, with $\mathrm{R}=1 \mathrm{m}\mathsf{\Omega }$ and $\mathrm{C}=1 \mathrm{m}\mathrm{F}$, operation near 1 MHz is achievable.

Because the so-called two-dimensional inductance depends on DC bias and AC amplitude, establishing a quiescent operating point—analogous to transistor biasing—is essential for stable circuit performance.

TDTRE is a novel device that requires no coils or magnetic fields and holds promise for applications in integrated circuits, high-frequency communication systems, quantum technologies, and other emerging fields.