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Article

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

1
Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
2
German Research Center for Artificial Intelligence (DFKI), 67663 Kaiserslautern, Germany
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Authors to whom correspondence should be addressed.
Academic Editor: Donald Bailey
J. Imaging 2021, 7(9), 175; https://doi.org/10.3390/jimaging7090175
Received: 3 July 2021 / Revised: 28 August 2021 / Accepted: 29 August 2021 / Published: 3 September 2021
(This article belongs to the Special Issue Image Processing Using FPGAs 2021)
In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by 44× while achieving 2201× higher energy efficiency and a 3.8% increase in recognition accuracy. View Full-Text
Keywords: OCR; hardware-software co-design; FPGA; Zynq; hardware architecture; image processing; historical documents OCR; hardware-software co-design; FPGA; Zynq; hardware architecture; image processing; historical documents
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MDPI and ACS Style

Tekleyohannes, M.K.; Rybalkin, V.; Ghaffar, M.M.; Varela, J.A.; Wehn, N.; Dengel, A. iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing. J. Imaging 2021, 7, 175. https://doi.org/10.3390/jimaging7090175

AMA Style

Tekleyohannes MK, Rybalkin V, Ghaffar MM, Varela JA, Wehn N, Dengel A. iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing. Journal of Imaging. 2021; 7(9):175. https://doi.org/10.3390/jimaging7090175

Chicago/Turabian Style

Tekleyohannes, Menbere K., Vladimir Rybalkin, Muhammad M. Ghaffar, Javier A. Varela, Norbert Wehn, and Andreas Dengel. 2021. "iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing" Journal of Imaging 7, no. 9: 175. https://doi.org/10.3390/jimaging7090175

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