A Reproducible FPGA–ADC Synchronization Architecture for High-Speed Data Acquisition

Abstract

High-speed data acquisition systems based on field-programmable gate arrays (FPGAs) often face synchronization challenges when interfacing with commercial analog-to-digital converters (ADCs), particularly under constrained hardware routing conditions and vendor-specific clocking assumptions. This work presents a vendor-independent FPGA–ADC synchronization architecture that enables reliable and repeatable high-speed data acquisition without relying on clock-capable input resources. Clock and frame signals are internally reconstructed and phase-aligned within the FPGA using mixed-mode clock management (MMCM) and input serializer/deserializer (ISERDES) resources, enabling time-sequential phase observation without the need for parallel snapshot or delay-line structures. Rather than targeting absolute metrological limits, the proposed approach emphasizes a reproducible and transparent data acquisition methodology applicable across heterogeneous FPGA–ADC platforms, in which clock synchronization is treated as a system-level design parameter affecting digital interface timing integrity and data reproducibility. Experimental validation using a custom Kintex-7 (XC7K325T) FPGA and an AFE7225 ADC demonstrates stable synchronization at sampling rates of up to 125 MS/s, with frequency-offset tolerance determined by the phase-tracking capability of the internal MMCM-based alignment loop. Consistent signal acquisition is achieved over the 100 kHz–20 MHz frequency range. The measured interface level timing uncertainty remains below 10 ps RMS, confirming robust clock and frame alignment. Meanwhile, the observed signal-to-noise ratio (SNR) performance, exceeding 80 dB, reflects the phase–noise-limited measurement quality of the system. The proposed architecture provides a cost-effective, scalable, and reproducible solution for experimental and research-oriented FPGA-based data acquisition systems operating under practical hardware constraints.

1. Introduction

Speed, accuracy, and effective noise suppression while maintaining reasonable cost and stability are critical requirements in modern signal processing and data acquisition systems [1,2]. These objectives can be achieved through advanced signal-processing algorithms as well as reliable synchronization between hardware and software components [3,4,5]. In recent years, FPGAs have emerged as a robust platform for such applications due to their real-time processing capability, low latency, and flexible input/output (I/O) architectures [6,7,8]. Although advanced algorithms, including adaptive filtering and learning-based approaches, have significantly improved signal quality, the reliability, consistency, and reproducibility of acquired datasets depend not only on algorithmic performance but also on the stability and accuracy of the underlying hardware synchronization [9,10]. From a data acquisition perspective, insufficient synchronization between ADCs and processing hardware directly degrades timing accuracy and compromises dataset reliability; therefore, synchronization should be regarded as a fundamental system component rather than a secondary hardware detail.

FPGAs are widely adopted in real-time signal-processing applications such as imaging, communications, and radar due to their parallel processing capability and reconfigurable nature [11,12,13,14,15]. Numerous FPGA-based implementations have been reported to enhance signal acquisition and reconstruction from ADCs, resulting in high resolution and low noise [16,17,18,19,20,21]. However, while most existing studies primarily emphasize signal-processing performance, hardware-level synchronization between ADCs and FPGA platforms remains comparatively underexplored. In practical implementations, clock and frame alignment across different interface standards, such as low-voltage differential signaling (LVDS), complementary metal–oxide–semiconductor (CMOS), and JESD204x, poses significant challenges, particularly when clock-capable I/O resources are limited. Misalignment at this stage directly affects the integrity of digital interface timing, data reproducibility, and the validity of experimental results.

In previous works, the authors developed FPGA-based phase measurement systems for mechanical displacement interferometers, which demonstrated the feasibility of high-resolution digital phase extraction [22,23]. These and other studies mainly improved optical resolution through advanced signal-processing algorithms [22,23,24,25,26,27,28,29]. However, many commercial ADC/processing platforms impose fixed sampling rates and proprietary synchronization constraints, which limit the portability and reproducible reuse of acquisition workflows across different FPGA–ADC combinations.

Such limitations are common in commercial platforms, where ADCs and processors are tightly coupled through proprietary synchronization schemes, making upgrades costly and inflexible. Similarly, modern high-speed ADCs using LVDS or JESD204x interfaces (e.g., ADS42LB49 [30], AFE7225 [31]) are available as standalone devices with detailed documentation [32,33,34,35]; however, their practical deployment remains complex because most implementation guidelines and reference designs are tailored to expensive vendor-specific evaluation boards and software [36,37], thereby increasing cost and limiting scalability for custom FPGA designs.

Based on our understanding of the existing literature, synchronization has typically been addressed from two main points. At the architectural level, prior studies have focused on multi-channel alignment and system throughput [9,10,38,39], where clock synchronization is generally treated as an enabling condition rather than a design parameter to be evaluated. Closer to the scope of this work, synchronization has also been studied at the block level, where hardware synchronization and clock phase alignment are addressed within an FPGA [40]. Reference [40] targets hardware synchronization between different devices using an MMCM-based phase-shifting approach combined with time-delay-line phase comparison. In this approach, phase states are captured via a parallel snapshot mechanism, which requires a parallel phase-observation structure with associated logic and clocking resources. In contrast, the present work adopts a time-sequential phase observation strategy based on ISERDES. It integrates clock phase shifting directly into the ADC–FPGA acquisition chain, enabling synchronization to be examined from a system-level perspective under practical timing, clock-frequency, and hardware resource constraints.

To clarify the novelty and scope of this contribution, we note that a preliminary version of this research was presented in our earlier conference paper [41]. While that work demonstrated the feasibility of a phase-measurement prototype for a specific heterodyne interferometry setup, the present manuscript substantially extends that effort by shifting the focus from an application-specific instrument to a reusable, vendor-agnostic synchronization architecture for high-speed data acquisition. Accordingly, the novelty of this work lies in the generalizable FPGA–ADC synchronization framework, rather than solely in the phase-measurement performance, unlike the conference paper, which was limited to a single-frequency feasibility test at 12.5 MHz, where the ADC input was assumed to be provided by an internal test pattern. This study provides a complete and reproducible synchronization architecture tailored to the scope of the Data Journal.

In contrast to vendor-specific and application-tailored solutions, this work introduces a generalized and cost-effective synchronization methodology for FPGA-based data acquisition systems. The main contributions of this paper are summarized as follows:

• A system-level perspective on clock phase alignment in data acquisition, treating clock synchronization as a design parameter affecting digital interface timing integrity, capture margin, and data reproducibility in the ADC–FPGA chain.
• Direct integration of clock phase shifting into the ADC–FPGA data capture process, enabling synchronization performance to be evaluated through actual capture timing and acquired data rather than block-level feasibility alone.
• A time-sequential phase observation strategy based on ISERDES, replacing parallel snapshot-based phase comparison and reducing hardware overhead while improving scalability at higher clock frequencies.
• Experimental characterization of interface synchronization jitter as a measurable system parameter, supported by full-spectrum validation (100 kHz–20 MHz) and digital interface integrity verification, together with an open access, reproducible acquisition pipeline with phase-alignment logs and timing measurements.

This approach significantly lowers the entry barrier for implementing experimental timing-sensitive measurement and high-speed data acquisition systems while maintaining sub-nanosecond phase alignment accuracy. To provide an overview of the proposed synchronization framework for data acquisition, Figure 1 illustrates the conceptual architecture of the FPGA-based data acquisition system and the main clocking and data paths involved.

2. Asynchronous Condition of the Default LVDS Interface Between a Commercial ADC and a Custom FPGA

Contemporary high-speed ADCs predominantly employ the low-voltage LVDS interface as the standard for digital data transmission at the output. The widespread adoption of LVDS is attributed to its robust data transmission capabilities, superior energy efficiency, and exceptional noise immunity [42,43,44,45]. However, despite these advantages, a critical challenge for system designers lies in the improper routing of the original clock and frame signals from the ADC to the clock-capable I/O ports of the FPGA, which can compromise system synchronization and performance. The problem is explained in Section 3.

2.1. Default LVDS Interface Between ADC and FPGA

Generally, each LVDS transmission from the ADC includes (Figure 2) [32]:

• One or more data lines per channel: 1-wire mode uses one signal line, while two-wire mode uses two lines.
• Clock: A synchronous clock signal is phase-shifted by 90 degrees to the data signal. Two transmission modes affect the clock frequency:
  • Single data rate (SDR): One data bit is transmitted per original clock cycle and captured on the rising edge. Here, f_clock = f_data.
  • Double data rate (DDR): Two bits are transmitted per original clock cycle, captured on both the rising and falling edges of the clock. In this case, f_clock = 0.5f_data.
• Frame: This digitized replica is delayed and phase-shifted by 90 degrees relative to the original clock.

Figure 2. Timing diagram of an ADC using DDR, two-wire LVDS interface, illustrating the phase relationship between the input clock, frame signal, and serialized output data bits.

Figure 2. Timing diagram of an ADC using DDR, two-wire LVDS interface, illustrating the phase relationship between the input clock, frame signal, and serialized output data bits.

In this study, a commercial dual-channel ADC (Texas Instruments, AFE7225, 12-bit resolution with a maximum sampling rate of 125 MHz) is intentionally employed due to its standard LVDS output interface and strict clock–data alignment requirements. This choice allows the synchronization problem addressed in this work to be examined under practically relevant conditions, where the ADC clock and frame signals are constrained to general-purpose FPGA I/O pins rather than dedicated clock-capable inputs. A custom FPGA module equipped with an FMC-LPC interface (Figure 3) is used in combination with an FMC–ADC adapter that bridges the ADC’s LVDS outputs to the FPGA’s FMC connector [46,47,48]. The selected Kintex-7 FPGA platform provides sufficient clock-management and high-speed I/O resources while remaining representative of cost-sensitive and research-oriented custom designs. This hardware configuration deliberately avoids reliance on vendor-specific evaluation boards or ideal clock-routing assumptions, thereby enabling an objective evaluation of the proposed FPGA–ADC synchronization architecture.

2.2. Clock-Capable Input/Output (I/O) of FPGA

Figure 3 illustrates the system setup and the raw input data captured by the original clock and frame. Modern FPGAs provide dedicated clock-capable pins to receive external clock signals. These pins are designed to distribute timing references from devices such as ADCs to the internal routing network, ensuring proper synchronization. Although routing the ADC timing lines to clock-capable pins represents the optimal hardware design, this configuration is often impractical in low-cost, educational, industrial, or custom boards with fixed pin assignments.

As shown in Figure 3b,c, the original clock and frame from the ADC are not connected to the clock-capable ports of the custom FPGA through the FMC–ADC adapter. Instead, they are routed to general-purpose I/O (GPIO) banks, interpreted as ordinary data lines rather than timing references. Consequently, the A- and B-channel data cannot be correctly digitized or aligned with the original clock and frame, leading to random distortion in the output signals (Figure 3a).

The design process becomes more complex when the ADC timing signals are connected to GPIO pins instead of dedicated clock-capable pins. Traditional synchronization methods often struggle to maintain stable timing alignment in these situations due to two main challenges.

The first challenge is that the internal routing capabilities are specific to the vendor. For instance, in some architectures, such as Intel devices using the Altera clock control (ALT-CLKCTRL) primitive [49], a GPIO signal can connect to the global clock network. However, other major architectures, such as our Xilinx 7-series platform, which uses an input delay control block [50], do not permit this. Direct route from a GPIO pin to the leading internal clocking resource on these platforms is considered architecturally invalid.

The second challenge is that, even when bridging is possible, this new clock path introduces a routing delay (skew) compared to the data signals, which follow standard I/O paths [32,49]. This skew is highly unpredictable and varies each time; its exact value relies on the specific hardware layout and the uncertain outcomes of the place-and-route algorithms that optimize the entire design of the vendor, not just this one path. Therefore, this skew cannot be reliably adjusted with static timing constraints, as it may change with any minor design modification. It is also likely to differ across various hardware layouts, which limits portability. This combination of vendor inconsistency and timing skew restricts the use of traditional synchronization methods.

Although the asynchronous condition is not ideal for high-speed data acquisition, it offers a valuable opportunity to examine how timing discrepancies propagate through the data path and affect signal integrity. Such analysis is essential for designing robust timing-recovery schemes suited to cost-sensitive and reconfigurable FPGA platforms. Related studies on clock accuracy and jitter effects in high-speed circuits are presented in [51]. The present study focuses on this non-optimal yet practical configuration to overcome this limitation. Section 3 details the proposed synchronization method.

3. Proposed Solution of a Modified LVDS Interface Between a Commercial ADC and a Custom FMC-Integrated FPGA

Figure 4 presents the overall flow of the proposed synchronization method designed to interface a commercial high-speed ADC with a custom FMC-LPC-integrated FPGA for high-speed data acquisition and signal processing. Building upon the asynchronous configuration analyzed in Section 2.2, this method reconstructs timing signals internally within the FPGA and establishes synchronization with the external ADC through four successive functional stages:

• Clock and frame generation: A pair of internal timing references, including clock and frame, is generated from the onboard crystal oscillator;
• New clock phase shift alignment: The phase of the newly generated clock is dynamically adjusted to coincide with that of the incoming ADC clock signal;
• New frame alignment: Based on the original frame, adjust the received message from the new frame signal to align with the newly generated clock signal;
• Data synchronization and distribution: The adjusted clock and frame signals are then used to synchronize the A- and B-channel data paths inside the FPGA, providing stable and coherent inputs for subsequent phase computation.

Figure 4. The flowchart of the proposed solution with four main functional blocks.

Figure 4. The flowchart of the proposed solution with four main functional blocks.

This four-stage architecture forms the foundation of the proposed synchronization system. The detailed implementation of each functional block is described in the following subsections.

3.1. Overview of the Hardware Synchronization System Built on High-Performance ADCs and Custom Low-Cost FPGAs

Figure 5 presents a detailed system schematic that integrates the proposed synchronization solution. The setup comprises three primary hardware components: a high-speed dual-channel ADC (AFE7225), an FMC-ADC adapter, and a custom Kintex-7 FPGA (XC7K325T) board. The ADC receives an external reference clock and two analog input signals, A and B, for digitization and subsequent signal processing. This study selects a carrier frequency of 100 MHz to illustrate the synchronization procedure; however, other frequencies can also be employed depending on the specific ADC configuration or application requirements. The ADC converts the analog inputs into 12-bit digital data streams and outputs them, along with the original clock and frame signals, through the FMC-ADC adapter interface. Acting as a passive interconnect board, the adapter bridges the ADC’s LVDS output pairs to the FPGA’s FMC-LPC port, preserving signal integrity during high-speed transmission. Inside the FPGA, an internal crystal oscillator provides a local timing reference (100 MHz in this implementation) from which the new clock and frame signals are generated. This frequency corresponds to the default setup of the current platform; other internal clock sources or operating frequencies can also be adopted, depending on the FPGA configuration. These internally derived timing references replicate the nominal characteristics of the ADC’s clock and frame lines, serving as the foundation for the synchronization process. The LVDS data lines entering the FPGA are routed through dedicated input buffers that convert differential pairs into single-ended logic levels compatible with the FPGA fabric. The converted signals include Frame, Clock, 6-bit Input A (low), 6-bit Input A (high), 6-bit Input B (low), and 6-bit Input B (high). These signals are then delivered to the synchronization module illustrated in Figure 6 for phase-shift and frame-alignment processing.

Figure 6 illustrates the FPGA-level synchronization architecture that reconstructs and aligns the timing and data streams received from the ADC. This internal structure implements the synchronization concept introduced in Figure 4 and corresponds to its four sequential stages (new clock & frame generator, new clock phase shift alignment, new frame alignment, and data reception). The synchronization block accepts eight input signals, including the internal 100 MHz FPGA clock, reset, original clock, and frame from the ADC, as well as four 6-bit LVDS data lines representing the low and high portions of Input A and Input B. It produces five outputs: the regenerated clock and frame, a data-ready flag, and two 12-bit parallel outputs corresponding to the reconstructed input channels A and B. At this level, the design logic operates as a unified module that regenerates internal timing references, then performs phase and frame alignment before reconstructing synchronized data streams. This organization ensures that the ADC’s external timing and data signals (originally routed through non-clock-capable I/O pins) are properly realigned to the FPGA’s internal clock domain. As a result, the entire data-acquisition path maintains consistent timing integrity and reliable communication between the ADC and FPGA.

3.2. New Clock and Frame Generator

Figure 7 illustrates the new clock and frame generator, which creates internal synchronization references within the FPGA. This block includes three input signals (phase-shift enable, phase-shift increase/decrease, and the 100-MHz FPGA clock signal) and four output signals (new clock, new frame, clock creation done, and phase-shift done). The generator operates based on the MMCM (Mixed-Mode Clock Manager) module, available in all Xilinx 7-series FPGAs. The MMCM takes the 100 MHz reference clock produced by the onboard crystal oscillator and synthesizes two new timing signals: a new clock and a new frame. Once both are initialized, the “clock creation done” flag is asserted, allowing subsequent phase-alignment stages to begin. Dynamic phase-shift control signals (increase/decrease, enable, done) are then used to adjust the output phase with high resolution in later synchronization processes. The reset input reinitializes the module to its default state when required.

3.2.1. Determining the Original and Frame Clock Frequencies of the LVDS Protocol

Accurate estimation of the ADC’s original timing frequencies is essential before synthesizing the new internal clock. The original (f_{originalclock}) and frame (f_{originalframe}) clock frequencies can be calculated [32]:

$$f_{original clock}={\displaystyle \frac{ADC\text{\_}bit\text{\_}number\times sample\text{\_}rate}{Bit\text{\_}per\text{\_}clock\text{\_}cycle \times num\text{\_}of\text{\_}wire \left(wire\right)}} ,$$

(1)

$$f_{original frame}=sample\text{\_}rate ,$$

(2)

where the ADC_bit_number, sample_rate, bit_per_clock_cycle, and num_of_wire are the ADC resolution, the user-selected sample rate of ADC, the bit per one clock cycle, and the number of wires per channel. In this design, with ADC_bit_number (Texas Instrument, AFE7225, full sampling rate = 125 MS/s) = 12 bits, sample_rate = 100 MS/s, bit_per_clock_cycle = 2, num_of_wire = 2, the frequencies are f_{originalclock} = 300 MHz and f_orginalframe = 100 MHz.

Recognizing that handling DDR signals poses several challenges for system configuration and signal processing, the newly generated clock should have a frequency twice that of the original clock to transition the system to operate solely in SDR mode. Therefore, the frequencies of the new clock (f_newclock) and frame (f_newfrane) signals are required as

$$f_{new clock}=2\times f_{original clock}=600 \mathrm{M}\mathrm{H}\mathrm{z},$$

(3)

$$f_{new frame}=f_{original frame}=100 \mathrm{M}\mathrm{H}\mathrm{z},$$

(4)

3.2.2. Adjust the New Clock and Frame Signal Frequencies Using MMCM to That of the Original Clock and Frame Signals [52]

Figure 8 presents the MMCM’s frequency-synthesis principle. The module performs programmable multiplication and division of the input clock by coefficients feedback multiplication (M), input division (D), and output division (O), respectively, to achieve the desired output voltage-controlled oscillator frequency (f_VCO) according to

$$f_{VCO}=f_{CLKIN}\times {\displaystyle \frac{M}{D}} ,$$

(5)

$$f_{out}={\displaystyle \frac{f_{VCO}}{O}}=f_{CLKIN}\times {\displaystyle \frac{M}{D\times O}} ,$$

(6)

where f_VCO, f_out, M, D, and O are the VCO frequency generated, the fundamental clock frequency of the crystal oscillator, the multiplying and dividing coefficients of the VCO output frequency, the input FPGA clock frequency, and the setting coefficient of the output MMCM clock frequency, respectively.

To satisfy the timing requirements of the Kintex-7 XC7K325T FPGA, the selected coefficients are M = 12, D = 1, O = 2 for the new clock signal, and O = 12 for the new frame signal. Substituting into (5) with crystal oscillator frequency f_CLKIN = 100 MHz, we obtain

$$f_{VCO}=100\times {\displaystyle \frac{12}{1}}=1200 \mathrm{M}\mathrm{H}\mathrm{z},$$

(7)

$$f_{new clock}=100\times {\displaystyle \frac{12}{1\times 2}}=600 \mathrm{M}\mathrm{H}\mathrm{z},$$

(8)

$$f_{new frame}=100\times {\displaystyle \frac{12}{1\times 12}}=100 \mathrm{M}\mathrm{H}\mathrm{z}.$$

(9)

This selection satisfies the required frequency (see Equations (3) and (4)).

In practice, the MMCM accepts a wide input frequency range of 10 MHz to 800 MHz, while maintaining a valid VCO operating range of approximately 600 MHz to 1440 MHz [53]. Therefore, it enables the FPGA to receive and synchronize external ADC clock signals whose frequencies, when multiplied, fall within the 600–1440 MHz VCO region. The frequency multiplication and division factors (M, D, O) are therefore selected such that the internal VCO stays within the 1.2 GHz region, ensuring stable locking and minimal phase jitter even if the ADC reference clock deviates by a few kilohertz from the nominal value. Hence, the proposed synchronization does not require both devices to share the same physical clock source; their frequencies need only to fall within the MMCM’s capture and tracking range.

It should be noted that the proposed clock generation and synchronization scheme does not impose a fixed maximum allowable frequency difference between the ADC clock and the FPGA clock. Instead, the tolerable frequency offset is determined by the capture range and dynamic tracking capability of the MMCM, together with the available timing margin for reliable data sampling.

In practice, stable synchronization can be maintained if the relative frequency difference results in a phase drift that can be compensated for by the clock alignment mechanism. If the frequency offset exceeds this capability, the system may temporarily lose lock and subsequently re-acquire synchronization through the state machine.

3.3. New Clock Phase-Shift Alignment

Although the newly generated clock and frame signals share the same frequency and duty cycle as the original ADC timing, a phase difference still exists due to routing delays and independent clock domains. Therefore, the phase of the regenerated clock must be precisely aligned with that of the original clock to ensure accurate synchronization between the ADC and FPGA.

Figure 9 illustrates the structure of the new clock phase-shift alignment block. It receives six inputs—new clock, new frame, clock-creation-done, phase-shift-done, reset, and original clock—and produces three outputs: phase-shift-enable, phase-shift-increase/decrease, and clock-copied. The block comprises two functional submodules: an ISERDES [50] unit that samples the reference clock and a phase-shift controller that dynamically adjusts the MMCM phase. The ISERDES captures the original clock as data across six consecutive 1-bit intervals (Q0–Q5). The phase-shift controller uses these sampled values to determine whether the regenerated clock is leading or lagging relative to the original. The controller then asserts the appropriate control signals (phase-shift-enable and phase-shift-increase/decrease) to tune the phase incrementally until both clocks are in sync. Once alignment is achieved, the “clock-copied” flag is set high to activate the subsequent synchronization stages. Because the original ADC clock is connected to a GPIO, it cannot be used directly for synchronous sampling within the FPGA. Therefore, it is treated as a reference data signal for phase comparison, while the regenerated clock serves as the active sampling clock.

3.3.1. Phase-Shift Controller

The phase-shift controller operates on the rising edge of the new frame and starts when the clock-creation-done signal from Section 3.2 is asserted. The controller achieves fine-grained tuning of the clock phase using the MMCM’s dynamic phase-shift feature, with a resolution defined as one-fifty-sixth of the VCO period:

$$Phase-shift resolution= {\displaystyle \frac{1}{56f_{VCO}}}\left(ps\right),$$

(10)

$$Phase-shift resolution={\displaystyle \frac{1}{56f_{VCO}}}\times f_{new clock}\times 360\left(degree\right).$$

(11)

With f_VCO = 1.2 GHz and f_newclock = 600 MHz, the achievable phase-shift resolution is approximately 14.88 ps or 3.214 degrees per step, enabling highly accurate phase alignment. It should be emphasized that the ISERDES operates as a shift-register-based deserializer, capturing the incoming reference clock across six consecutive bit positions (Q0–Q5). This behavior is equivalent to a serial-in/parallel-out shift register clocked at 100 MHz, allowing the system to observe the phase relationship between the original and regenerated clocks at discrete sampling instants. However, the 14.88 ps resolution derived above corresponds to the internal dynamic phase-shift granularity of the MMCM’s VCO, which runs at 1.2 GHz. In other words, while the ISERDES updates its logic state every 10 ns, the MMCM can finely adjust the output phase in 14.88 ps steps, providing sub-nanosecond alignment accuracy beyond the ISERDES sampling period.

Figure 10 depicts the finite state machine transition diagram of the phase-shift controller. The controller is implemented as a Moore-type FSM, in which the control outputs depend only on the current state to ensure glitch-free operation of the MMCM phase-shift mechanism. The FSM operates across six states: initial, update, detect, increase, decrease, and lock. The six outputs Q5–Q0 from the ISERDES store consecutive samples of the original clock and are used to determine the phase relationship between the regenerated and reference clocks. This phase-comparison process serves as the core of feedback in the synchronization loop. It enables the controller to identify whether the FPGA-generated clock is leading, lagging, or aligned with the ADC clock and to issue the corresponding phase-shift command to the MMCM. The MMCM then performs phase adjustment with the fine resolution previously described (≈14.88 ps per step), allowing precise alignment of the regenerated clock with the ADC reference. Through this closed-loop operation, the system maintains stable synchronization and prevents sampling errors during high-speed data acquisition. The edge_var variable encodes this relation into one of three categories:

(1)

late—new clock lags (phase delayed);

(2)

soon—new clock leads (phase advanced);

(3)

same—aligned or 180° out-of-phase.

Figure 10. Moore-type finite state machine (FSM) transition diagram of the phase-shift controller (PSC) used for clock phase alignment and synchronization.

Figure 10. Moore-type finite state machine (FSM) transition diagram of the phase-shift controller (PSC) used for clock phase alignment and synchronization.

When a reset is received, the FSM enters the Initial state, clearing all registers. Six consecutive 1-bit samples are loaded into the Q registers during the Update state. Based on the resulting pattern, the controller enters one of the three operational branches:

• 1st Case—Phase Decreasing (“late”):

If the pattern Q5–Q0 = “101010”, the new clock is slower than the original (its phase is delayed), as shown in Figure 11. The controller asserts phase-shift-enable = 1 and phase-shift-increase/decrease = 0 for one frame cycle, causing the MMCM to decrement the phase. Once phase-shift-done is set, the FSM returns to update for verification (Figure 12).

• 2nd Case—Phase Increasing (“soon”):

If Q5–Q0 = “010101”, the new clock leads the reference, as illustrated in Figure 13. The controller asserts phase-shift-enable = 1 and phase-shift-increase/decrease = 1 for one frame cycle, incrementing the MMCM phase. After the phase-shift-done is received, control loops return to Update (Figure 14).

• 3rd Case—Case–Phase Lock (“same”):

When the sampled Q pattern alternates as “0x0x0x” or “1x1x1x”, the phase detector indicates an edge-coincidence condition between the regenerated and original clocks. In this case, the system may lock to either a 0° alignment (rising–rising edge coincidence) or a 180° alignment (rising–falling edge coincidence). These represent two alternative but equally valid lock states of the synchronization controller, as illustrated in Figure 15. Under this condition, the FSM transitions into the Lock state, indicating that the phase-alignment criterion has been satisfied.

In this state, the clock copied signal is asserted, enabling synchronized data acquisition, while the MMCM maintains the aligned phase through its internal feedback mechanism (Figure 16). Importantly, the Lock state does not represent a fixed or static phase condition. After phase confirmation, the controller deliberately returns to the Update state, where the FSM resumes its regular Update–Detect cycle. During this cycle, the ISERDES continuously samples the reference clock pattern (Q5–Q0), and the controller periodically evaluates potential phase deviations.

3.3.2. Sensitivity to Frequency Offsets and Phase-Tracking Mechanism

In the Lock state, the residual frequency mismatch between the ADC reference clock and the regenerated clock inside the FPGA is defined as

$$∆f=\left|f_{original clock}-f_{new clock}\right|,$$

(12)

Since these two clocks are generated from independent oscillators, a small but unavoidable frequency mismatch is inevitable. This mismatch leads to a gradual relative phase drifting between the two clock domains over time. Over a monitoring interval T_m, the accumulated phase difference can be expressed as [54]

$$∆\varphi \left(T_m\right)=2\pi ∆{fT}_m,$$

(13)

This phase drift can be equivalently represented as a time offset (i.e., the delay of the regenerated clock relative to the original ADC clock) given by

$$\tau \left(T_m\right)={\displaystyle \frac{\Delta \varphi \left(T_m\right)}{2\pi f_{original clock}}}={\displaystyle \frac{\Delta f}{f_{original clock}}}\times T_m ,$$

(14)

In the proposed system, the phase controller evaluates the lock condition periodically with a minimum monitoring interval of approximately T_m ≈ 120 ns (corresponding to 12 frame-clock cycles). Because Δf mainly originates from the ppm-level tolerance of independent crystal oscillators, the accumulated phase drift within each monitoring interval is small and varies slowly. By leveraging the MMCM dynamic phase-shift mechanism, the controller compensates for this drift through discrete phase adjustments with a minimum resolution of 14.88 ps, corresponding to approximately 3.214° at f_newclock = 600 MHz.

To maintain stable tracking, the drift per monitoring interval must remain within the compensation capability of the phase-shift mechanism. Denoting the effective allowable correction per monitoring interval by Δt_allow, the tracking condition is:

$$\tau \left(T_m\right) \le \Delta t_{allow},$$

(15)

where the relationship between the maximum frequency offset Δf_max and Δt_allow is

$$\Delta f_{max}={\displaystyle \frac{\Delta t_{allow}}{T_m}}\times f$$

(16)

In our implementation, with a MMCM dynamic phase-shift resolution Δt_step of ~14.88 ps, a minimum monitoring T_m of 120 ns, and f = f_newclock = 600 MHz, the maximum frequency offset is Δf_max = 74.4 kHz. This corresponds to 124 ppm relative to 600 MHz. If we use a stricter criterion (e.g., half-step margin, ∆t_allow = ∆t_step/2), the bound becomes Δf_max = 37.2 kHz (≈62 ppm). These values are comfortably above typical crystal oscillator tolerances (tens of ppm), explaining why slow drift can be continuously tracked in our experiments.

Therefore, the Lock state should not be interpreted as fixing the sampling phase at a single value, but rather as maintaining the sampling phase within a bounded safe region. When slow phase drift causes the ISERDES-sampled pattern to temporarily correspond to characteristic sequences such as “010101” or “101010”, the controller detects this deviation in subsequent Detect states and automatically performs fine phase correction. This closed-loop Lock–Detect–Realign mechanism enables stable long-term tracking and compensation of phase drift without requiring hard frequency locking between the ADC and FPGA clocks.

3.4. New Frame Alignment

Once the newly generated clock is phase-aligned with the reference, the next step is to realign the frame signal so that data packets from the ADC are correctly delimited within each frame period. This phase adjustment could also be performed using another MMCM block controlled by the same phase-shift controller described previously. However, such an approach would considerably increase FPGA resource usage because the number of available MMCM blocks per I/O bank is limited [49]. Using an MMCM from a different I/O bank may be a workaround, but it introduces additional routing delays and signal-management complexity. Fortunately, modern FPGAs provide dedicated ISERDES primitives with an internal bitslip mechanism, allowing bit-level alignment without requiring an additional MMCM. This section introduces an alternative frame-alignment strategy that leverages the bitslip capability to efficiently re-synchronize incoming data packets.

Figure 17 shows the block schematic of the frame-alignment module, which operates on the rising edge of the newly generated frame signal. The frame-alignment process begins after the completion of the clock phase-shift alignment, ensuring that the received 6-bit data packets are correctly synchronized so that all bits within one frame cycle belong to the same ADC sample. This block includes six inputs (new clock, new frame, clock copied, reset, bitslip, and original frame) and two outputs (data ready and bitslip). The bitslip signal sequentially shifts bits within the deserialized stream to achieve timing alignment. At this stage, the block coordinates two submodules: the ISERDES, which deserializes the original frame signal, and the frame-arrangement unit, which performs pattern detection and alignment control.

Similar to the clock phase-shift alignment, the ISERDES in this stage uses the new clock to sample the original frame before passing the deserialized bits to the Frame-arrangement unit. The latter dynamically adjusts the bitslip signal according to the captured bit sequence. The bitslip signal propagates through two paths: one loops back to the input ISERDES to refine packet alignment. At the same time, the other connects to the ISERDES modules in the data-receive block, which process the A- and B-channel data streams. The data-ready signal is asserted only when the system verifies that all bits received within one new-frame period correspond to the same ADC sample, thereby ensuring accurate data reconstruction. Finally, the reset signal restores the block to its initial state.

3.4.1. Frame-Arrange Operator

Figure 18 illustrates the difference between the packets captured by the new frame signal before and after the alignment process using the new frame alignment function. Initially, the exact bit position that marks the start of each captured packet is unknown, making it impossible to determine the sample boundaries. To align each received packet into a complete ADC sample, the frame clock is treated as a regular data signal and processed with the other data paths (DA_in1, DA_in0, DB_in1, DB_in0). As shown in Figure 18, a complete sample is successfully captured only when the system detects the unique bit sequence “000111” corresponding to the frame clock pattern. This detection condition causes the bitslip signal to remain active until the correct sequence is received. At this point, the system locks, and alignment is finalized.

3.4.2. Bitslip Submodule of ISERDES

Figure 19a illustrates the data-reception process without the bitslip operation, where the ISERDES functions as a 6-bit serial-to-parallel shift register. In this configuration, each 6-bit word is deserialized sequentially on the rising edge of the new clock signal, and the last bit of one packet immediately becomes the first bit of the next. For instance, sample N–1 spans bits’ a’ through ‘f’, while sample N begins at ‘g’ and ends at ‘l’. On the other hand, Figure 19b demonstrates the reception process when bitslip is activated. Upon detecting a frame or word-boundary mismatch, the bitslip control triggers a one-bit shift within the ISERDES chain during the next clock cycle. As a result, the current packet temporarily contains an additional deserialized bit ‘m’, which is discarded, while the subsequent packet realigns to start at the correct boundary ‘n’.

This time-domain adjustment enables the ISERDES to maintain proper word alignment despite initial or accumulated bit-offset errors. The bitslip submodule ensures that every 6-bit segment remains synchronized with the new clock and frame signals by monitoring the frame pattern on each clock cycle. Through this mechanism, the frame alignment ensures that all deserialized bits are correctly grouped into complete samples, providing consistent and reliable data reconstruction before the data-reception stage.

3.5. Data Reception

Figure 20 shows the Data reception block, which reconstructs complete 12-bit digital samples for both Input A and Input B channels after frame alignment. This block becomes active once the Data is ready and clock-copied signals are asserted, indicating that the clock and frame have been fully synchronized. It receives ten inputs (data ready, clock copied, new frame, new clock, reset, and bitslip) together with four LVDS data lines corresponding to the upper and lower six-bit segments of each channel (6-high-bits-input-A, 6-low-bits-input-A, 6-high-bits-input-B, 6-low-bits-input-B). Each data line is connected to an ISERDES module that deserializes the incoming six-bit word on the rising edge of the new clock signal. When the data ready signal is asserted, the data capture block concatenates the high- and low-bit segments to form a complete 12-bit sample for each channel. The resulting data words are then forwarded to the phase-measurement module for subsequent digital processing and display.

The reception process starts on the rising edge of the new frame and proceeds synchronously within the adjusted clock domain. The bitslip, provided by the frame-alignment stage, maintains correct word boundaries in case of residual bit offsets. The reset signal, shared across all synchronization modules, also reinitializes the data reception logic to ensure proper synchronization at startup. Through this coordinated operation between the ISERDES, bitslip, and data capture modules, the FPGA continuously receives and reconstructs two coherent 12-bit data streams from the ADC, achieving fully synchronized data acquisition across both channels.

3.6. Timing Uncertainty and Jitter Estimation

Maintaining timing integrity is crucial in high-speed data acquisition systems, as timing fluctuations can impact both the precision of phase-based measurements and the robustness of digital data acquisition. In the proposed FPGA–ADC synchronization architecture, timing uncertainty is therefore analyzed, clearly separating two distinct domains with different roles:

• ADC sampling-domain jitter, which determines the temporal uncertainty of ADC conversion instants and limits the achievable SNR of phase- or time-based measurements;
• FPGA-side synchronization and retiming uncertainty, which affects acquisition amplitude, data alignment, and the correctness of digital data acquisition at the ADC–FPGA interface.

Although both effects may influence the quality of the digitally processed signal, they serve different purposes in evaluation. ADC sampling-domain jitter is used to characterize the phase-noise-limited performance of measurements. In contrast, FPGA-side synchronization uncertainty determines whether the digital interface operates correctly and is therefore evaluated using digital integrity metrics, such as bit error rate (BER).

3.6.1. ADC Sampling-Domain Jitter and Phase-Noise-Limited SNR

In the present setup, ADC conversion is controlled exclusively by an external reference clock. The ADC clock routed into the FPGA (the original clock) is treated as a regular input signal (not as a synchronous capture clock for the receive logic). It is used only for internal reconstruction and alignment. Consequently, internal FPGA clocking does not influence the ADC conversion instants or the intrinsic analog performance of the converter [55]. The ADC sampling-domain jitter (σ_samp) can be expressed as [54]

$${\sigma }_{samp}^2={\sigma }_{ADC clock input}^2+{\sigma }_{ADC, Apterture}^2,$$

(17)

where σ_{ADC clock input} is the jitter of the external sampling clock source, and σ_aperture is the intrinsic sampling aperture uncertainty of the ADC. For the AFE7225, σ_aperture = 250 fs RMS [28], while modern MHz-range clock sources typically exhibit sub-picosecond jitter [56,57,58]. Applying Equation (17) yields σ_samp = ~1.0 ps RMS.

For phase- or time-based measurement applications, this sampling-domain jitter contributes directly to phase noise and limits the achievable SNR according to [54]:

$${SNR}_{samp}=-20log\left(2\pi f_{in}{\sigma }_{samp}\right),$$

(18)

where f_in is the signal-carrying frequency. With f_in = 20 MHz, the SNR is SNR_samp = ~77 dB. This value represents the intrinsic phase-noise floor of the sampling process and is independent of the FPGA–ADC synchronization mechanism.

3.6.2. FPGA-Side Synchronization Correctness

After conversion, the ADC outputs digital data and frame signals to the FPGA. In the proposed architecture, these signals are not routed to clock-capable inputs, necessitating internal clock reconstruction and alignment. As a result, FPGA-side synchronization/retiming uncertainty, denoted as σ_sync, becomes relevant at the digital interface level and can be expressed as [54]

$${\sigma }_{sync}^2={\sigma }_{MMCM output clk}^2+{\sigma }_{PSC}^2,$$

(19)

where σ_{MMCM output clk} and σ_PSC are the residual jitter of the MMCM/VCO and the quantization uncertainty introduced by the discrete phase-shift controller (PSC), respectively. When the MMCM operates in internal feedback mode at a 1.2 GHz VCO frequency, σ_MMCM is conservatively estimated to be within 5–8 ps RMS. The PSC resolution of 14.88 ps corresponds to σ_PSC ≈ 4.3 ps RMS [59]. Applying Equation (19) yields σ_sync ≈ 9.1 ps RMS.

This uncertainty reduces the available setup/hold margin for digital data capture and alignment at the ADC–FPGA boundary. However, it is much smaller than the nanosecond-scale timing window and the ADC’s specified interface timing requirements [31], and is therefore not expected to limit the correct reception of data.

3.6.3. Phase-Noise Contribution Versus Synchronization Correctness

From a phase-noise perspective, both σ_samp and σ_sync may contribute to the total phase uncertainty of the digitally processed signal. Accordingly, a combined timing uncertainty

$${\sigma }_{total}^2={\sigma }_{samp}^2+{\sigma }_{sync}^2,$$

(20)

may be used to provide a conservative upper bound on the phase-noise floor in FPGA-domain phase or displacement measurements. However, it is essential to note that this combined metric is not used to evaluate the correctness of synchronization. While σ_samp and σ_sync may both affect the quality of the recovered phase (e.g., phase-noise floor), only σ_sync governs reliable data capture and alignment at the digital interface.

Table 1. Summary of timing-uncertainty components, including sampling-domain jitter (SNR limit) and interface-domain synchronization/retiming uncertainty.

Uncertainty Category	Jitter/Timing Uncertainty	RMS Estimation Value (ps)
Sampling-domain (phase-noise-limited SNR)	ADC clock input	<1
	ADC aperture	0.25
	Total sampling jitter (σsamp)	~1.0
Interface-domain (synchronization correctness)	MMCM output clock	≤8
	Synchronization/retiming	4.3
	Total sync uncertainty (σsync)	9.1

The sampling-domain jitter components define the phase-noise-limited SNR of the measurement. In contrast, the digital interface domain uncertainties are used exclusively to assess the correctness of synchronization and the integrity of data acquisition.

summarizes the estimated timing-uncertainty components in the proposed acquisition chain, separating sampling-domain jitter and interface-domain synchronization/retiming uncertainty.

3.6.4. Interface Integrity Validation Using BER Measurements

The functional correctness of the proposed clock synchronization scheme is evaluated exclusively in the digital domain, where synchronization errors manifest as bit-level capture faults rather than as analog noise. While sampling-domain jitter limits the intrinsic phase-noise performance of the ADC, the correctness of clock and frame alignment at the ADC–FPGA boundary is determined solely by the integrity of the received digital data.

The BER is defined as

$$BER={\displaystyle \frac{N_{err}}{N_{bit}}} ,$$

(21)

where N_err is the number of detected bit errors over N_bit evaluated bits. In the absence of observed errors, an upper bound on BER is reported. Assuming Poisson statistics for rare error events, a 95% confidence upper bound is given by

$${BER}_{95\%}={\displaystyle \frac{3}{N_{bit}}} ,$$

(22)

Section 4.2.3 applies these metrics to the ADC test-pattern captures to quantify interface integrity under the proposed synchronization scheme.

Beyond timing-related effects, the performance of high-speed ADCs is commonly characterized by intrinsic parameters, including differential nonlinearity, integral nonlinearity, total harmonic distortion, and offset. These parameters describe the static linearity and analog distortion behavior of the converter and are primarily determined by the ADC architecture and silicon implementation. In the proposed system, the synchronization of the architecture operates independently of these intrinsic ADC characteristics. Standard evaluation procedures for the aforementioned parameters, such as code-density testing and single-tone spectral analysis, therefore, remain directly applicable and are not affected by the clock reconstruction or alignment strategy. Consequently, the present analysis focuses on timing integrity and synchronization-induced effects, while assuming that intrinsic ADC performance follows the manufacturer’s specifications.

4. Simulation and Experimental Results

The performance of the FPGA-based signal acquisition system is assessed based on four primary criteria: the resource efficiency in signal synchronization, the preservation of signal integrity, the influence of SNR on the quality of the acquired signals, and the consistency and coherence of multi-channel signals within the acquired dataset.

4.1. Resource Efficiency in Signal Synchronization: Low Resource Consumption and Flexibility

One of the critical factors in FPGA-based design is accurately estimating resource utilization. A well-optimized design efficiently utilizes resources while fully meeting the requirements set forth by the designer. This directly impacts the maximum workload that the processing core can handle. The more streamlined the design, the greater the number of distinct tasks an FPGA can accommodate.

Table 2. Comparison of resource utilization between the new hardware synchronization method and the manufacturer-provided synchronization method [32].

Resource	Utilization		Reduction (%)
	(This Work)	[32]
MMCM	1	0	−100
Input-delay control	0	1	100
Input-delay	0	1	100
Look-up table	43	195	78
Look-up table random-access memories	0	32	100
Flip flop	59	258	77

presents a quantitative comparison between the proposed hardware synchronization architecture (Method 1) and the standard vendor reference design (Method 2, based on Xilinx XAPP524 [32]). Reference [32] describes a vendor-specific implementation under ideal clock-routing assumptions, relying on dedicated IDELAY and IDELAYCTRL primitives, which consume significant routing resources.

In contrast, the proposed architecture addresses the challenge of constrained I/O routing, where clock-capable inputs are unavailable. By leveraging the MMCM block for phase alignment instead of rigid delay lines, the system achieves substantial efficiency gains. Quantitatively, as shown in Table 2, the proposed method requires only 43 Look-Up Tables (LUTs), representing a 78% reduction compared to the 195 LUTs used in the vendor reference design. Furthermore, it eliminates the need for LUTRAMs (0 vs. 32) and reduces Flip-Flop usage by approximately 77% (59 vs. 258). These results confirm that the proposed strategy delivers comparable functionality with significantly lower logic overhead, validating its suitability for resource-constrained custom FPGA designs.

4.2. The Signals Collected by the FPGA-Based Signal-Processing System After Synchronization

4.2.1. Record Clean Signals at Different Amplitudes and Carrier Frequencies

Figure 21 presents the experimental setup used to evaluate the signals collected by the synchronized signal system implemented in this study. After the ADC–FPGA acquisition stage, a dedicated Butterworth band-pass filter is applied to suppress out-of-band noise in the preprocessed carrier signals over the frequency range from 100 kHz to 20 MHz. For each carrier frequency, different filter bandwidths are selected, resulting in different processing gains (Gp), as illustrated in

Table 3. Filter bandwidth and process gain for each input signal.

Carrier Frequency at 100 MS/s (MHz)	Bandwidth (MHz)	Process Gain (Gp) (dB) [3]
0.1	15	5
1	15	5
5	5	10
10	1.5	15
20	0.5	20

. After acquisition and filtering, the signals are transmitted to the integrated logic analyzer (ILA) for visualization and subsequently stored as CSV files for offline analysis.

In the experiment, the FPGA-based data acquisition system recorded a pure 100-MHz original clock signal and an A-channel sine-waveform signal with its carrier frequencies of 100 kHz, 1 MHz, 5 MHz, 10 MHz, and 20 MHz and amplitudes of 1 mV, 2 mV, …, 10 mV, 20 mV, …, 90 mV, 0.1 V, 0.2 V, …, 0.9 V, and 1 V, respectively, which are generated by a function generator (Moku: lab, a multifunction instrument by Liquid Instruments, in function generator mode, 16 bits, full sampling rate 500 MS/s). The carrier frequencies of 100 kHz, 1 MHz, 5 MHz, 10 MHz, and 20 MHz were selected to validate the synchronization performance across a wide dynamic range representative of typical analog front-end and FPGA operating limits. These values span the low-frequency region (100 kHz), where timing skew effects are negligible, to the high-frequency boundary (20 MHz), where phase alignment and sampling jitter become dominant. The intermediate frequencies (1–10 MHz) correspond to the working range of many dual-channel ADCs and heterodyne interferometric systems used in precision metrology. This selection therefore provides a comprehensive validation of the proposed synchronization method under both low- and high-frequency conditions.

The capture results of the FPGA system within a 10 ns time range, along with the corresponding frequency domain analysis using fast Fourier transform (FFT), are shown in Figure 22, Figure 23, Figure 24 and Figure 25 and the Supplementary Material. Here, the A-channel signals were recorded with a sample number of 40,960 data points at a sampling rate of 100 MS/s. Figure 22, Figure 23, Figure 24 and Figure 25 present the measurement results of the 100 kHz-, 1 MHz-, 5 MHz-, 10 MHz-, and 20 MHz-sine-waveform signals, with amplitudes of 1 mV and 1 V, respectively, at a sampling rate of 100 MS/s. In Figure 22, the results for 100 kHz signals with 1 mV and 1 V are presented, achieving an SNR of greater than 85 dB. The subsequent results of the 1 MHz, 5 MHz, 10 MHz, and 20 MHz signals with amplitudes of 1 mV and 1 V, respectively, that are shown in Figure 22, Figure 23, Figure 24 and Figure 25 can also be obtained with an SNR of ~80 dB and up to 90 dB. This indicates that the FPGA-based data acquisition system can effectively capture and preserve signals within the carrier frequency range of 100 kHz to 20 MHz, maintaining a high SNR above 80 dB.

The experimentally measured high SNR values, reaching up to 91 dB, align well with the refined jitter-based estimation in Section 3.6. Based on a total effective jitter of approximately 1.03 ps at 20 MHz, the theoretical jitter-limited SNR is about 77 dB. After applying a digital Butterworth band-pass filter with a process gain (Gp) of 20 dB, the total theoretical SNR rises to approximately 97 dB [3]. The observed 6 dB discrepancy is expected, as it represents typical hardware implementation losses and residual noise components that are not accounted for in the idealized jitter-limited model. However, the signals acquired by the FPGA-based system still exhibit slight distortion or amplitude modulation, which may result from (i) the carrier frequency or primary signal falling outside the filter’s passband due to an excessively narrow bandwidth, or (ii) phase distortion and uneven amplitude attenuation caused by the filter’s steep roll-off when the carrier frequency fluctuates slightly during acquisition.

Figure 26 illustrates the linear relationship between the analog input and the digitized output of Channel A. It demonstrates that the FPGA-based system accurately preserves signal amplitude across carrier frequencies of 100 kHz and 20 MHz, and input levels ranging from 1 mV to 1 V, at a sampling rate of 100 MS/s. To quantitatively evaluate the agreement between the acquired digital result and the corresponding analog input reference, the relative error is defined as

$$relative error={\displaystyle \frac{\left|acquired result-input signal\right|}{input signal}}\times 100\%,$$

(23)

is also represented in the same graphs for each case. For low input amplitudes (below 0.05 V), the relative error lies within 10–31%. As the signal amplitude increases beyond 0.1 V, the error falls below 5%, indicating improved signal-to-noise performance of the acquisition system. The fitting functions in each case follow the linear form y = ax, where a ≈ 1, with an R-squared value close to 1. Accordingly, the FPGA-based system successfully recovers carrier signals with amplitudes from 1 mV to 1 V across the 100 kHz–20 MHz band. It exhibits a highly linear response with negligible distortion during the analog-to-digital conversion process. This crucial first step enables the FPGA-based system to retain carrier or interferometric signals with high fidelity, thereby providing a reliable foundation for subsequent precise computations. For completeness, results obtained at intermediate frequencies of 1 MHz, 5 MHz, and 10 MHz are reported in Appendix A (Figure A1).

4.2.2. Record Clean Signals of the Two A and B Synchronized Channels

In this experiment, the FPGA-based system received a pure 100 MHz original clock signal and two sine-wave A- and B-channel signals with carrier frequencies of 100 kHz, 1 MHz, 5 MHz, 10 MHz, and 20 MHz and amplitudes varying from 1 mV to 1 V at a sampling rate of 100 MS/s, similar to case (Section 4.2.1). Representative measurement results for the two channels are presented in Figure 27 and Figure 28, corresponding to the lowest (100 kHz) and highest (20 MHz) carrier frequencies. Additional results obtained at intermediate frequencies of 1 MHz, 5 MHz, and 10 MHz are provided in Appendix A (Figure A2 and Figure A3) for completeness.

In Figure 27, the two acquired signals exhibit nearly identical amplitudes and phases, demonstrating precise synchronization between the ADC channels. Minor amplitude or phase deviations (5–30%) can be attributed to analog-path losses and unequal BNC cable lengths between the function generator and the FPGA system. Because these discrepancies remain constant over time, they can be compensated through phase-deviation and amplitude-correction algorithms implemented in the subsequent FPGA processing stage.

Figure 28 compares the amplitude response of both channels for input voltages from 1 mV to 1 V. Each channel follows a linear relationship (y = ax, a ≈ 1) with R² values close to 1, confirming high linearity and consistent gain across the full input range. The relative error is 10–31% for low amplitudes (below 0.05 V) and decreases to below 5% once the amplitude exceeds 0.1 V. The consistency of this behavior between channels A and B demonstrates uniform analog-to-digital conversion and reliable two-channel synchronization at high sampling rates.

The detailed amplitude-fitting results for all tested frequencies are summarized in

Table 4. The amplitude relationship between the input two-channel signals generated by the function generator and the measured result of the FPGA-based system. This two-channel system is investigated at carrier signal frequencies of 100 kHz, 1 MHz, 5 MHz, 10 MHz, and 20 MHz, with amplitudes ranging from 1 mV to 1 V, over a sampling frequency of 100 MHz.

Carrier Signal Frequencies (MHz)	Channel A		Channel B		Sampling-to-Carrier Ratio
	Fitting	Error (%)	Fitting	Error (%)
0.1	y = 1.0307x, R2 ≈ 1	<10	y = 1.0201x, R2 ≈ 1	<10	1000
1	y = 1.0733x, R2 = 1	<15	y = 0.9961x, R2 = 1	<20	100
5	y = 1.0139x, R2 = 1	<12	y = 0.9605x, R2 = 1	<31	20
10	y = 1.0256x, R2 ≈ 1	<20	y = 0.899x, R2 ≈ 1	<32	10
20	y = 0.9931x, R2 = 1	<27	y = 0.9922x, R2 = 1	<31	5

. The fitting coefficients verify that the linearity of the two-channel acquisition remains excellent across the entire 100 kHz–20 MHz range, with R² ≈ 1 in every case. The relative error is below 1% for input amplitudes above 0.1 V, below 10% for amplitudes between 0.01 V and 0.1 V, and below 30% for the lowest range of 0.001 V to 0.01 V. These results indicate that the FPGA-based acquisition system achieves high reconstruction accuracy for input signal amplitudes greater than 0.1 V. In addition, the error decreases as the sampling-to-carrier ratio increases. This occurs because a higher ratio provides more sampling points per signal period, allowing more accurate waveform reconstruction and reducing the influence of jitter and phase misalignment. These quantitative results are consistent with the graphical responses in Figure 27 and Figure 28, confirming that the proposed synchronization method maintains stable, uniform performance for both ADC channels. Consequently, the FPGA-based acquisition platform can simultaneously and accurately recover paired carrier signals from 1 mV to 1 V across the 100 kHz–20 MHz band, ensuring a robust foundation for precise phase computation in subsequent processing stages and providing a reliable synchronized two-channel dataset that can serve as a foundation for downstream phase measurement in interferometric applications (demonstrated in prior works [23,60]).

4.2.3. Bit-Error Verification

To verify digital interface integrity, two specialized ADC test patterns (CONFIG128, address 0x337 [31]) were utilized at a 100 MHz clock frequency, as shown in Figure 29. The data was captured directly via the ILA, enabling real-time inspection of 65,536 consecutive samples for each pattern at the hardware level. The alternate pattern (alternating between 010101010101₂ (1365) and 101010101010₂ (2730)) was used to stress the interface under a high toggle rate, while the data ramp pattern (incrementing by one every four cycles) was used to verify sample-to-sample continuity. Following Section 3.6.4, with N_samples = 65,536 samples per pattern and N_bits/sample = 12 evaluated bits per sample, the total number of inspected bits is N_bit = N_samples × N_bits/sample = 786,432. As observed in Figure 29a, the clean transitions between the two logic states confirm stable data latching, while Figure 29b shows a continuous linear ramp without apparent disruptions. No bit errors or sequence disruptions were observed over the inspected window (zero-error observation). Therefore, the 95% confidence upper bound on BER defined in Equation (22) is reported as BER_95% < 3.82 × 10⁻⁶. Crucially, this value reflects the statistical limit imposed by the FPGA’s ILA memory depth rather than the intrinsic error rate of the interface. Considering the zero-error observation, consistently high SNR, and long-term stable operation (Section 4.3), the effective BER is expected to be orders of magnitude lower than the reported upper bound and may approach the 10⁻¹⁰ level typically expected for properly operating high-speed digital interfaces. The results indicate that the proposed reconstruction and synchronization scheme maintains reliable digital interface operation and that the synchronization and retiming uncertainty does not introduce observable bit-level degradation under the tested conditions.

4.3. Long-Term Stability Evaluation

To evaluate the long-term stability of the proposed synchronization and acquisition workflow, we operated the system continuously for 12 h while applying a 1 MHz single-tone input at Input A. A short acquisition snapshot was recorded every 30 min, and the SNR was computed using a standard single-tone FFT-based method (excluding DC and harmonic bins consistently across all snapshots). As shown in Figure 30, the measured SNR remains nearly constant over the 12 h run, staying within a narrow band of approximately 88–91 dB (≈3 dB peak-to-peak difference). The average SNR is 89 dB with a standard deviation of ~1 dB. No loss of lock was observed during the run, indicating that the closed-loop Lock-detect behavior successfully tracks slow drift between the independent ADC reference clock and FPGA oscillator, while ensuring timing integrity at the ADC–FPGA boundary.

The demonstrated stable synchronization at sampling rates up to 125 MS/s and accurate signal reception over the 100 kHz–20 MHz range correspond to the operating point of the current experimental platform. Under this configuration, the achievable sampling rate and signal bandwidth are governed by the selected ADC devices, the timing margins of the LVDS interface, and the phase-shift resolution of the MMCM-based alignment mechanism. From an architectural standpoint, the proposed synchronization framework is defined at the level of clock reconstruction, alignment, and data capture, and is therefore applicable to FPGA–ADC platforms operating under comparable routing and interface constraints. Accordingly, the proposed synchronization framework is not inherently tied to the current sampling rate and can be extended to ADC devices operating at higher sampling rates.

5. Cost Efficiency of the Phase Measurement System Implemented with the Proposed Method

Table 5. Representative signal acquisition platforms and indicative hardware cost ranges.

Data Acquisition System	ADC Resolution	Sample Rate	SNR (dB)	Cost ($)
Moku: Lab [61]	12-bit	1.25 GS/s	70 to 80	~5000
NI PCI-5122 [62]	14-bit	100 MS/s	75 to 85	>15,000
NI 5733 (ADC) + FPGA PXIe-7972R [25]	16-bit	120 MS/s	85 to 95	~24,000
VDD-650 (Polytec) [63]	12-bit	Down conversation and 5.12 MS/s	65 to 75	>10,000
AFE7225 [31] + TSW1400EVM [37]	12-bit	Up to 125 MS/s	Around 70	~20,000
AFE7225 [31] + custom Kintex7 FPGA [64] (this work)				<800
ADS42LB49 [30] + TSW1400EVM [37]	14-bit	Up to 250 MS/s	Around 73.2	~20,000
ADS42LB49 [29] + custom Kintex7 FPGA [64]				<800

summarizes representative signal acquisition platforms used for phase measurement in heterodyne interferometry, along with indicative hardware cost ranges. The listed commercial systems, including PXIe-based solutions, standalone interferometric instruments (e.g., from NI or Polytec), and integrated data acquisition platforms, are typically designed as turnkey instruments for industrial or metrology-grade applications and therefore feature a high level of system integration. While they offer high performance, they effectively act as proprietary “black boxes”, where internal processing logic is inaccessible to researchers. In contrast, the proposed system adopts a fully reproducible “white box” architecture. This design emphasizes flexibility at the component level, allowing different ADC devices and FPGA platforms to be substituted with minimal modification to the synchronization scheme. Such flexibility reduces dependency on proprietary hardware and facilitates cost-effective implementation.

Within this framework, Table 5 illustrates that the proposed FPGA–ADC architecture enables high-speed data acquisition with moderate hardware complexity. For example, a configuration based on the ADS42LB49, combined with a Kintex-7 FPGA, supports sampling rates of up to 250 MS/s with an SNR of approximately 73.2 dB. In contrast, an AFE7225-based configuration achieves sampling rates of up to 125 MS/s with comparable signal quality. Crucially, it achieves this comparable signal quality at approximately 4–5% of the cost of high-end alternatives (e.g., <$800 versus >$20,000). These results highlight the feasibility of implementing high-speed phase measurement architectures using flexible and accessible hardware platforms, which can significantly reduce implementation costs in custom and research-oriented designs without relying on highly integrated commercial instruments.

6. Conclusions

This paper has presented a reproducible, vendor-independent synchronization architecture for high-speed FPGA-based data acquisition systems. By shifting the focus from proprietary, application-specific designs to a generalized “white box” framework, we successfully addressed the challenge of interfacing high-speed ADCs with FPGAs under constrained I/O routing conditions where dedicated clock resources are unavailable. The proposed method utilizes a closed-loop phase-shifting mechanism based on MMCM and ISERDES to reconstruct and align clock and frame signals internally, ensuring timing integrity and data reproducibility.

Experimental validation on a custom platform, comprising a Kintex-7 FPGA and an AFE7225 ADC, demonstrated robust synchronization at sampling rates of up to 125 MS/s. The system achieved consistent signal acquisition across a frequency range of 100 kHz to 20 MHz. Digital interface integrity was verified through bit-error-rate measurements, which confirms error-free data capture and correct clock/frame alignment under the proposed synchronization scheme. In addition, the measured interface-level timing uncertainty remains below 10 ps RMS, while the observed signal-to-noise ratio exceeding 80 dB reflects the phase-noise-limited measurement quality of the system rather than the correctness of synchronization. Furthermore, the resource utilization analysis confirmed that our architecture reduces logic overhead by approximately 78% compared to standard vendor-provided reference designs.

A key contribution of this work is the provision of a cost-effective and transparent alternative to commercial “black box” instruments. While high-end proprietary systems offer integrated performance, they often limit user accessibility and customization. In contrast, our proposed architecture delivers comparable signal quality and synchronization stability at a significantly lower implementation cost (under $800 versus over $20,000 for comparable commercial setups), as highlighted in the comparative analysis. This approach significantly lowers the entry barrier for advanced experimental research, enabling the community to implement, verify, and extend high-speed data acquisition workflows using accessible hardware components. Future work will focus on extending this synchronization framework to multi-channel, multi-board synchronized arrays, supporting large-scale distributed measurement applications.